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C to VHDL converter in a codesign environment

Conference Paper · June 1994

DOI: 10.1109/VIUF.1994.323960 · Source: IEEE Xplore

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 C to VHDL Converter in a Codesign Environment

Matthew F. Parkinson, Paul M. Taylor and Sri Parameswaran

Department of Electrical and Computer Engineering

University of Queensland, St. Lucia 4072
Brisbane, Queensland, Australia
email : [email protected]

Abstract initially identifies the critical code segments within the

Automation of the Hardware/Software Codesign software. These code segments are then used to provide a
methodology brings with it the need to develop near optimal partition between hardware and software
sophisticated high-level synthesis tools. This paper implementations. By next applying the process of
presents a tool which is the result of such development. synthesis to the partitioned code it is possible to achieve
This tool converts standard C code into an equivalent significant acceleration of the algorithm.
VHDL behavioural description. This description is used to The automation of this partitioning process also
generate a chip-level hardware interconnect of identical permits the design to be independent of the final hardware
functionality to the original C code. required for execution. The actual hardware
implementation is determined through cost and resource
constraints. This easily allows the designer to take
advantage of emerging technologies without the requisite
1 Introduction redesign of the system from the ground up. An example
of a proposed hybrid architecture is outlined in Figure 2.
Automated design methodologies in digital systems Acceleration of the algorithm is achieved by converting
have until recently been limited entirely to the design of the high-level language description of the hardware
hardware. Automated Hardware/Software Codesign (HSC) partition into VHDL 12] code. By then passing the
offers a design methodology for a total system (ie. both
hardware and software). VHDL code through the package SYNT 131, we have
For a totally hardware oriented design (eg. ASICs) the both a hardware description of the partition, as well as
feedback on the cost in terms of chip area, and execution
development time is prohibitive in bringing fresh and
time. This cost is related to implementing the algorithm
affordable products to the market. Equally restrictive is a
totally software based solution which will perform slowly on a XILINX FPGA.
As our system is specified in C, a tool was constructed
due to the use of a generalised computing architecture (ie. a
RISC based microprocessor). This is where designing for to turn sections of C code into behavioural VHDL 12].
a hybrid between a hardware and software bascd From VHDL we construct hardware using the behavioural
implementation can be of particular advantage. level synthesis tool SYNT 131. The tool described here is
A codesign methodology enables the specification of an the C to VHDL converter.
algorithm totally in software. Through an automated Section 3 details the C to VHDL synthesis tool, while
design process the algorithm is optimally partitioned into Section 4 details a large example.
both hardware and software, thus allowing the designer to For a complete description of the HSC process as it is
be distanced from the hardware specific techniques of applied above, please refer to L1land L41.
improving an algorithm's performance. This in turn
allows the designer to concentrate on the algorithm's 2 C to VHDL converter
design.
Algorithm bottlenecks are usually limited to a small The process of converting C code to VHDL isn't
portion of the actual code. By converting these critical restricted to the area of Hardware/Software Codesign. As a
code segments into hardware, an ideal partitioning of thc general synthesis tool, C2VHDL provides the means of
algorithm's execution into both hardware and software is transferring C algorithms to FPGA interconnect. For
achieved. An overview of the automated custom-chip solutions it provides a good front-end tool to
Hardware/Software Codesign methodology is brielly
thc SYNT packagc.
outlined i n Figure 1 . This automated partitioning process

100
0-8186-6215" $03.00 0 1994 IEEE
 Algorithm
(High Level Language
e.g. C)

- ----- - __ _ Automatic
_ _ _CA_D Tools
_
71

Synthesis
Process

Figure 1 - Automated HardwareKoftware Codesign Methodology

(Other Microprocessors,
floating point units,
transputers, etc.)

Timing
Circuitry

to switch
between
processors

- Address bus

(=?+ Control bus

Data bus

Figure 2 - Hybrid Architecture Configuration

101
 The consistent use of a familiar language such as C The structure of the code produced by C2VHDL is
means design time for products is greatly reduced. In turn, influenced by the nature of the HSC process, as well as the
time to market for profit oriented products is minimised. limitations imposed by SYNT, in the form of SynVHDL.
By employing testability and simulation in the design A section of C code is converted to VHDL with a single
process, off-the-shelf algorithms may be used in future ENTITY ... PORT description, and a single
products. It is important to reduce design effort through ARCHITECTURE body. SYNT can only synthesize for a
the reuse of standard algorithms. single VHDL process, and requires a totally behavioural
The ability to perform automated design of hardware is VHDL description. The ARCHITECTURE is therefore
essential to the HSC process. The code is initially composed in a behavioural fashion, consisting of only one
described using the C language. VHDL is derived from the process.
language ADA. Consequently it is similar to C as far as The PORT description details the transfer of
standard high-level constructs are concerned. The process information across the hardwarekoftware boundary. In the
we use in C2VHDL is based around this fact. The design case of HSC, the software partition must transfer data
of the system is based on GNU CC [51, and its GCC across this PORT interface. The current implementation
compiler (version 2.4.3.1). The GCC code is centred of SYNT doesn't allow the use of PROCEDURES or
around a YACC 16] description of the C language. FUNCTIONS in VHDL. This will not present a great
The YACC parser (c-parse.y) is composed of problem as far as the HSC process is concerned. Its
productions. When these productions are triggered, the C interest is in converting compound code sections to
code associated with them is executed. By strategically hardware. As chip area is at a premium, it isn't necessary
placing C code on the productions which parse variable to convert larger sections of code. This is in keeping with
declarations, the identifiers and their types are recorded. the concept that critical bottlenecks will consist of several
Once the declaration section is finished this information is compound code sections.
written to the VHDL output file, with the appropriate The conversion to VHDL of assignment constructs
change in style to suit the VHDL code. The same involving various combinations of operators is performed
procedure is applied to all of the C constructs to produce a by firstly breaking the statement into the individual
complete VHDL description of the original C code. calculations. This is achieved by creating temporary
The VHDL code produced from this parsing process is variables for each term in the calculation. This not only
consequently passed through the synthesis package SYNT. maintains the precedence of operators, but also prevents
The form of VHDL implemented by SYNT is called calculations being placed in the conditional clause of IF ...
SynVHDL. It is a proper subset of VHDL, in that there THEN statements and the like.
have been no additions made to the VHDL language. It The size of data types and variables is maintained
does however fail to embrace all of the constructs found in throughout the conversion. By using pointers when
standard VHDL. This in turn limits the ability for passing information across the chip boundary, the data
C2VHDL to convert all constructs found in the C transfer interface is minimised. This is also reflected in
language successfully to VHDL. As SynVHDL improves chip-area utilisation. Usually, the smaller the data
on its subset of VHDL, so too will C2VHDL improve on interface, the fewer the on-chip registers that are required.
its ability to support the full constructs of the C language. The conversion to VHDL of conditional statements is
The limitations aren't seen to be of great significance reasonably straight-forward. The use of temporary
however, with most major C constructs being supported. variables can be seen in the example of Figure 3.

as-IO := g;
as-11 := 3;
IF as-10 > a-1 1 THEN
g := 4;
p <= 6 ;
ELSE
g := 5 ;
p <= 2;
END IF;
~ ~~ ~

Figure 3 - IF .. ELSE conversion

102
 The temporary variables are optimized out in the before the update, is used in the actual expression. In
synthesis package SYNT. general, all of the standard operators may be applied.
Another example is the switch on case statements
which are converted to CASE on WHEN statements. Each
case must end in a break at this stage. This is to prevent 3 An example
flow on to the next case statement, as this isn’t directly
supported in VHDL. The default is converted to a WHEN The Appendix in section 7 at the end of this paper,
OTHERS construct. It isn’t necessary to include the includes two separate descriptions. The first is a C
default statement, as WHEN OTHERS will be included program listing. The second is the VHDL description
regardless. It isn‘t necessary to have any statements after which our C2VHDL converter has produced. C2VHDL
the default if so desired. If multiple case options are placed does not produce code for all C.
at the same statement in the code, this is handled by As we are limited by the VHDL subset that SYNT
ORing the options together in the equivalent WHEN takes, only those constructs which SYNT can handle have
statement, as can be seen in the example of Figure 4. been implemented. For instance SYNT cannot handle
The handling of f o r loops is through conversion to a floating point numbers, therefore we have not allowed
WHILE loop, with ST1 going before the loop, ST2 is the floating point numbers in C. The VHDL description
conditional of the loop itself and ST3 going as the last which results from this program also does not have an
statement of the loop. This works even for multiple “entity” section. This is because the program can be
statements in any of STI or ST3, as can be seen in the tailored for differing types of input output (such as serial
examples in Figure 5. input output or parallel input output) using the same
The other types of loops are handled similarly. The architecture. Finally, there are a large number of
handling of pre and post incrementing is handled with temporary values. These are removed by SYNT when it
temporary variables. If the post operation occurs within does register allocation. These temporary values also help
other expressions, it is handled by updating the variable SYNT achieve a more efficient hardware synthesis.
itself. The temporary variable, which holds the value

switch (g) { CASE g IS

case 1 : WHEN 1 =>
a=a+b; as-1 := a;
break; a s 2 := b;
case 2 : a := as-1 + as-2;
a=a+c; wHEiN2=>
break, as-3 := a;
case 3 : as-4 := c;
case 6 : a := as-3 + as-4;
case 9 : WHEN 3 16 I 9 =>
a=a+d; a s 3 := a;
break, as-6 := d;
case8: ‘ a := a s 3 + as-6;
a=a+e; WHEN 8 =>
break, as-7 := a;
default : as-8 := e;
I a := as-7 + as-8;
WHEN OTHERS 3
NULL,
END CASE;

Figure 4 - SWITCH .. CASE conversion

103
 for (STl; ST2;ST3) { STl;
WHILE ST2 LOOP
I e
ST3;
END LOOP;

b = 2346; b := 2346;
for (a = 1; a < 10; b = b + 4, a++) { a:= 1;
b=b!3; as-62 := a;
1 as-63 := 10;
WHILE as-62 < as-63 LOOP
as-67 := b;
a s h 8 := 3;
b := as-67 I as-68;
as-64 := b;
as-65 := 4;
b := as-64 + as-65;
as-66 := a;
a : = a + 1;
END LOOP;

Figure 5 - FOR conversion

4 Future research 6 References

We are presently experimenting with another synthesis Matthew F. Parkinson, Paul M. Taylor, and Sri
tool, AMICAL, which has the capability to synthesize Parameswaran, "An Automated Hardwarelsoftware
VHDL procedures and functions. At this preliminary stage Codesign (HSC) using VHDL," Proceedings of the First
Asia Pacific Conference on Hardware Description
it would appear that AMJCAL [11] removes a number of Languages and their Applications (APCHDLSA '931,
other limitations imposed on us by SYNT. Hence any December 1993.
limitations imposed are a direct result of the synthesis tool P. Ashenden, "VHDL Cookbook," - Intemet
used. Mats Fredriksson, Ahmed Hemani, Kurt Nordqvist,
We are in the process of building working systems "SYNT 1 .O USERS GUIDE," - Internet
using the C2VHDL tool at present. This is incorporated Matthew F. Parkinson, Paul M. Taylor, and Sri
in the overall hardware software codesign project. It is Parameswaran, "A Profiler for Automated Translation of
here that problems such as referencing variables which Signal Processing Algorithms into High Speed
exist in main memory will need to be resolved. Hardware/SoftwareHybrid Architectures," Proceedings of
Microelectronics '93, October 1993.
GNU CC, Reference Manual - Intemet
5 Conclusions YACC, Reference Manual - Internet
B. Bose, M. E. Tuna, and S. D. Johnson, "System
Factorisation in Codesign," Proceedings of the 1993
We have presented a tool which converts C programs to IEEE International Conference on Computer Design
VHDL. This tool was developed as part of the hardware (ICCD '93), October 1993.
software codesign project at the University of Queensland. P. M. Athanas, and H. F. Silverman, "Processor
Since the tool is used for synthesis, only those constructs Reconfiguration Through Instruction-Set
which the VHDL synthesis tool allows are included in this Metamorphosis," Computer IEEE, pp. 11-18, March
system. As the synthesis tools become more 1993.
sophisticated, a larger subset of C can be converted to R. Ernst, J. Henkel, "Hardware-Software Codesign of
VHDL. Embedded Controllers Based on Hardware Extraction,"

104
 Handout from First Int'l Workshop on Hardware-Software [ 111 K. O'Brien, M. Rahmouni, P. Kission, M. Aichouchi, A.
Codesign, Estes Park, Colo., 1992. Jemai, H. Ding, A. A. Jerraya, "AMICAL - Interactive
[lo] R. Gupta, CC. Coelho, and G. De Micheli, "Synthesis Architectural Synthesis Based on VHDL - User's
and Simulation of Digital Systems Containing Manual," System-Level Synthesis Group, Laboratoire
Interacting Hardware and Software Components," Proc. TIMMNPG, 46, Avenue Felix Viallet, 3803 1, Grenoble
DAC, IEEE CS Press, Los Alamitos, Calif., Order No. CEDEX, FRANCE
2822, 1992, pp. 225-230. (email: obrien @rhone.imag. fr).

7 Appendix

t--;
#include <stdio.h> continue;
g = g + 1 ;
int i; 1 while (t > OL);
while (t > OL) (
int A(char *h, short j, char r) ( t--;
unsigned char matt; t++;
char s[231; break;
int 8; g=g+1;
long a; I
int b = 46; if ( g > 10)
char d; g = 4;
unsigned char *e; else
char f[157]; g = 5;
long t; (g > 10) ? (g = 4) : (g = 5 ) ;
a = 10 + sizeof(int);
matt = 'a' + 3; a = 15 - sizeof(1ong);
b = i + 4 ; a = 24 sizWf(char);
i = 1; a = 24 / sizeof(float);
b = 1; a = 56 % sizeof(typeof(f)1 ;
i = i + b ; a = sizeof(f);
j=j*5; a = 12 * (-34 && sizeof(typeof(char))) + 52;
j = 5 * j ; a = 12 (-34 I 1 sizeof(typeof(char))) + 52;
g = 0; a = (34 & 23) / 45;
switch (g) ( a = (34 I 23) / 45;
case 1: a += I; a = -34 3;
break; a = 35 4;A

case 2: a += 2; a=a+l;
break; a = a + (b 62);
case 3 : a = a << 3;
case 9: a += 3; a = a >> 2;
break; a / = (7 + b);
case 4: a=a*7;
case 8: a += 4; a = 4 + -7 + !a + -a;
break; a = 4 + !7 + ! O + !a;
1 a = --b;
switch (g) ( b = 2346;
case 5: b / = 3 ; for (a = 1; a < 10; b = b + 4, a++) (
break; b=b/3;
1 I
switch ( g ) { for (a = 1; a < 10; b = b + 4, a++)
case 5 : b=b/3;
for (t = 0; t < 10; tt+) ( if (a < b) (
a * = 4; a = 3;
break; b++ ;
1 I else t
break; b = 4;
default: a++;
a++; )
1 1
do (

Figure 6 - Original C code

105
 a := a + 3;
ARCHITECTURE behaviour OF C2VHDL IS
BEGIN WHEN 4 I 8 =>
PROCESS a := a + 4;
VARIABLE ftell : long;
VARIABLE i : int; WHEN OTHERS =>
VARIABLE h : varpointer; NULL;
VARIABLE j : short; END CASE;
VARIABLE r : char;
VARIABLE matt : unsignedchar; CASE g IS
VARIABLE g : int; WHEN 5 =>.
VARIABLE a : long; as-11 := b;
VARIABLE b : int := 46; as-12 := 3;
vARIABLJ3 d : char; b := as-11 1 as-12;
VARIABLE e : varpointer;
VARIABLE t : long; WHEN OTHERS =>
NULL;
VARIABLE as-1 : int4; END CASE;
VARIABLE as-2 : int4;
VARIABLE as-3 : int4; CASE g IS
VARIABLE a s 9 : int4; WHEN 5 =>
VARIABLE 86-5 : int4;
VARIABLE as-6 : int4; t := 0;
VARIABLE as-7 : int2;
VARIABLE as-8 : int4; as-13 := t;
VARIABLE as-9 : int4; as-14 := 10;
VARIABLE as-10 : int2; WHILE as-13 < as-14 LOOP
a := a 4:
and so on .. .
_- EXIT;
VARIABLE as-142 : int4; as-15 := t;
VARIABLE as-143 : int4; t := t + 1;
VARIABLE as-144 : int4; END LOOP;
WHEN OTHERS =>
BEGIN NULL;
as-1 := 97; as-16 := a;
a s 3 := 3; a := a + 1;
matt := as-1 + as-2; END CASE;

as-3 := i; as-17 := '1';

as-4 := 4; WHILE (as-17 = '1') LK3P
b := as-3 + as-4; as-18 := t;
t := t - 1;
i := 1; -- NEXT;
as-19 := g;
b := 1; as-20 := 1;
g := as-19 + as-20;
as-5 := i;
as-6 := b; as-21 := t ;
i := as-5 + as-6; as-22 := 0;
IF (as-21 > as-22) THEN
as-7 := j; as-17 := '1';
as-8 := 5; ELSE
j := as-7 as-8; as-17 := '0';
END IF;
as-9 := 5; END D P ;
as-10 := j;
j := as-9 as-10; as-23 := t;
as-24 := 0;
g := 0; WHILE as-23 > as-24 W P
as-25 := t;
t := t - 1;
CASE g IS as-26 := t ;
WHEN 1 => t := t + 1;
a := a + 1; _- EXIT;
as-27 := g;
WHEN 2 => as38 := 1;
a .:= a + 2: g := as-27 + as-28;

I WHEN 3 I 9 =>

106
 a := as-52 + as-53;
END LOOP;
a s 3 4 := - 34;
as-29 := g;
as-55 := 1;
as-30 := 10;
IF NOT(as-54 = 0 ) OR NOT(as-55 = 0) THEN
IF as-29 > a s 3 0 THEN
as-56 := 1;
g := 4;
ELSE
a s 3 6 := 0;
ELSE
END IF;
g := 5;
a s 3 7 := 12;
as-58 := (as-56);
END IF;
as-59 := a s 3 7 as-58;
as-60 := 52;
as-31 := g;
a := as-59 + as-60;
as-32 := 10;
IF (as-31 > as-32) THE&'
as-61 := 34;
g := 4;
as-62 := 23;
IF as-61 < 0 THEN
ELSE
as-61 := as-61 + 2147483647;
g := 5;
as-61 := as-61 + I;
END IF;
END IF;
IF as-62 < 0 THEN
a s 4 2 := as-62 + 2147483647;
a s 2 3 := lo;
as-62 := as-62 + 1;
a s 2 4 := 4;
END IF;
a := as-33 + as-34;
as-63 := 0;
a s 3 5 := 15; as-64 := 1;
FOR as3 IN 0 To 31 LOOP
as-36 := 4;
IF ((as-61 / 2) /= ((as-61 + 1) / 2)) AND
a := a s 3 5 - as-36;
((as-62 / 21 /= ((as-62 + 1) / 2)) THEN
as-63 := as-63 + as-64;
as-37 := 24;
END IF;
as-38 := 1;
as-61 := as-61 / 2;
a := as-37 * as-38;
as-62 := as-62 / 2 ;
as-64 := as-64 * 2;
as-39 := 24;
END LOOP;
as-40 := 4;
as-65 := (as-63);
FOR a s j IN 0 TO 31 LOOP
as-66 := 45;
IF ((as-39 / 2) /= ((as-39 + 1) / 2)) THEN
FOR a s 2 IN 0 TO 31 LOOP
as-4lfasj) := '1'
IF ((as-65 / 2) f = ((as-65 + 1) / 2)) THEN
ELSE
as-67fasj) := '1'
as-4ltasj) := ' 0 '
ELSE
END IF;
as-67tasj) := '0'
IF ((as-40 / 2) /= ((as-40 + 1) / 2)) THEN
END IF;
as-42(asjt := '1'
IF ((as-66 / 21 /= ((as-66 + 1) / 2 ) ) THEN
ELSE
as_68(asjt := '1'
as-42fasj) := '0'
USE
END IF;
as-68tas3) := ' 0 '
END m P
a := as-44;
END IF;
END LOOP
a := as-70;
as-45 := 56;
as-46 := 157;
as-71 := 34;
a := a s 9 5 MOD as-46;
as-72 := 23;
IF as-71 -z 0 THEN
a := 157;
as-71 := as-71 + 2147483647;
as-47 := - 34; as-71 := as-71 + 1;
END IF;
as-48 := 1;
IF as-72 -z 0 THEN
IF NOTlaS-47 = 0) AND "(as-48 = 0) THEN
as-72 := as-72 + 2147483647;
as-49 := 1;
as-72 := as-72 + 1;
ELSE
END IF;
as-49 := 0;
as-73 := 0;
EM) IF;
as-74 := 1;
as-50 := 12;
FOR a s j IN 0 TO 31 LOOP
a k 5 l := (as-49);
IF ((as-71 / 2) /= ((as-71 + 1) / 2)) OR
as-52 := as-50 as-51;
(as-72 / 2 ) /= ((as-72 + 1) / 2)) THEN
as-53 := 52;
as-73 := as-73 + as-74;
END IF;
as-71 := as-71 / 2;

107
 as-72 := as-72 / 2; as-101 := a;
as-74 := as-74 2; as-102 := 7;
END LOOP; a := as-101 * as-102;
as-75 := (as-73);
as-76 := 45; as-103 := 4;
FOR a s 2 IN 0 TO 31 Ixx)P as-104 := (2147483647 - 7);
IF ((as-75 / 2) /= ((as-75 + 1) / 2 ) ) THEN IF a = 0 THEN
as_77(asj) := '1' as-105 := 1;
ELSE ELSE
as-77(asj) := ' 0 ' as-105 := 0;
END IF; END IF;
IF ((as-76 / 2) /= ((as-76 + 1) / 2)) THEN as-106 := as-103 + as-104;
as_78(asj) := '1' as-107 := as-105;
ELSE as-108 := as-106 + as-107;
as,78(asj) := ' 0 ' as-109 := (2147483647 - a);
END IF; a := as-108 + as-109;
END LOOP
a := as-80; IF 7 = 0 THEN
as-110 := 1;
as-81 := - 34; ELSE
as-82 := 3; as-110 := 0;
a := as-81 as-82; END IF;
as-111 := 4;
as33 := 35; as-112 := as-110;
as-84 := 4; IF 0 = 0 THEN
IF as-83 < 0 THEN as-113 := 1;
as-83 := as-83 + 2147483647; ELSE
as-83 := as-83 + 1; as-113 := 0;
PID IF; END IF;
IF as-84 < 0 THEN as-114 := as-111 + as-112;
as-84 := as-84 + 2147483647; as-115 := as-113;
as34 := as-84 + 1; IF a = 0 THEN
END IF; as-116 := 1;
a s 3 5 := 0; ELSE
as-86 := 1; as-116 := 0;
FOR a s j IN 0 TO 31 LOOP END IF;
IF ((as-83 / 2) / = ((as-83 + 1) / 2)) XOR as-117 := as-114 + as-115;
((as-84 / 2) / = ((as-84 + 1) 1 2)) THEN as-118 := as-116;
as-85 := as-85 + as-86; a := as-117 + as-118;
END IF;
a s 3 3 := as-83 / 2; b := b - 1;
as-84 := as34 / 2; a := b:
as-86 : = as-86 2;
END L m P ; b := 2346;
a := as-85;

as-87 := a; a := 1;
as-88 := 1;
a := a s 3 7 + as-88; as-119 := a;
as-120 := 10;
as-89 := b; WHILE as-119 < as-120 LOOP
as-90 := 62; as-124 := b;
as-91 := a; as-125 := 3;
as-92 := (as-89 as-90); FOR a s 2 IN 0 TO 31 LOOP
a := as-91 + as-92; IF ((as-124 / 2 ) / = ((as-124 + 1) / 2 ) )
THEN
as-93 := a; as-126(as-j) := '1'
as-94 := 3; ELSE
a := as-93 * (2 ** as-94); as-126(as-j) := '0'
END IF;
as-95 := a; IF ((as-125 / 2) / = ((as-125 + 1) / 2 ) )
as-96 := 2; THEN
a := as-95 / (2 ** as-96); as_127(asj) := '1'
ELSE
as-97 := 7; as-127(as-j) := '0'
as48 := b; PID IF;
as-99 := a; PID LOOP
as-100 := (as-97 + as-98); b : = as-129;
a := as-99 / as-100;

108
 b := as-140;
as-121 := b;
as-122 := 4; as-132 := b;
b := as-121 + as-122; as-133 := 4;
b := as-132 + as-133;
as-123 := a;
a := a + 1; as-134 := a;
END LOOP; a := a + 1;
END LOOP;
a := 1;
as-141 := a;
as-130 := a; as-142 := b;
as-131 := 10; I F as-141 < as-142 THEN
WHILE as-130 < as-131 LQOP a := 3;
as-135 := b;
as-136 := 3; as-143 := b;
FOR a s 2 IN 0 TO 31 LOOP b : = b + 1;
I F ((as-135 / 2) / = ((as-135 + 1) / 2 ) ) ELSE
THEN
b := 4;
as-137 (as-j) := ' 1 '
ELSE as-144 := a;
as_137(asj) : = ' 0 ' a := a + 1;
END I F ; END IF;
I F ((as-136 / 2) / = ((as-136 + 1) / 2 ) )
THEN WAIT ON clk UNTIL (in-rdy = '1');
as-138(as-j) := '1' END PROCESS;
ELSE END behaviour;
as,138(as-j) := ' 0 '
END I F ;
END LOOP

Figure 7 - Converted VHDL code

109

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