Course Title: Digital Electronics Course Code: ECE 205 Credit Units: 4 Level: UG L T P/ S SW/F W Total Credit Units
Course Title: Digital Electronics Course Code: ECE 205 Credit Units: 4 Level: UG L T P/ S SW/F W Total Credit Units
Course Title: Digital Electronics Course Code: ECE 205 Credit Units: 4 Level: UG L T P/ S SW/F W Total Credit Units
Course Objectives:
This course is an introduction to the basic principles of digital electronics. At the conclusion of this course, the student will be able to quantitatively identify the
fundamentals of computers, including number systems, logic gates, logic and arithmetic subsystems, and integrated circuits. They will gain the practical skills
necessary to work with digital circuits through problem solving and hands on laboratory experience with logic gates, encoders, flip-flops, counters, shift
registers, adders, etc. The student will be able to analyze and design simple logic circuits using tools such as Boolean algebra and Karnaugh Mapping, and will
be able to draw logic diagrams.
Prerequisites:
An Introduction to Modern Electronics, Basic Algebra
Pedagogy for Course Delivery: The course would be covered under theory and laboratory. In addition to assigning project–based learning, early exposure to
hands-on design to enhance the motivation among the students. It incorporates designing of problems, analysis of solutions submitted by the students groups
and how learning objectives were achieved. Continuous evaluation of the students would be covered under quiz, viva etc.
To design half adder, full adder, half subtractor, full subtractor using gates and verify their truth tables.
To implement control circuit using multiplexer..
To design a BCD to seven segment decoder converter and verify the truth table.
To design a 4-bit BCD to Excess-3 code converter .
To verify the truth table of R-S , D , J-K and T-flip flops.
To design a 3-bit asynchronous UP-counter using J-K flipflops.
To design a 3-bit synchronous Down counter using J-K flip flops
To design a 4-bit serial in serial out shift register.
To design and study a sequence detector.
Weightage
(%)
10% 7% 8% 5% 70%
CT: Class Test, HA: Home Assignment, S/V/Q: Seminar/Viva/Quiz, EE: End Semester Examination; A: Attendance
Weightage
(%)
5% 10% 10% 5% 70%