Application of Rns in The DSP Architecture

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APPLICATION OF RNS IN THE DSP ARCHITECTURE
We know that for a circuit to implement major three criteria that we should take in account,They
are
• Minimize power consumption

• ,Minimize area and
• Maximize the speed.
So there are many ways to reduce power consumption while dealing with any circuit.Many
scientists proposed different methods to reduce power consumption in any circuit.
❖ POWER REDUCTION IN DSP ARCHITECTURE
One of the method is to use Residue Number Systems in in DSP architecture implementation. As
we all know the DSP Architecture consists of FIR Filters .Mainly this filters are implemented by
using Two’s Complement system and Residue number system. Many experiments showed a large
power reduction while using RNS representation.So we can say that one of the major application
of using RNS Systems is to decrease the power consumption in DSP Architectures.So that it will
able to minimize the whole configuration..
As we told that when we use RNS system ,it will reduce the power consumption and thus increase
the speed of operation.
❖ SMALL OVERVIEW OF RNS SYSTEMS
RNS System can be defined by the set of P relatively prime numbers {m1,m2….mn} quoted as
RNS base.
Any no: has unique RNS representation given by,,

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❖ HOW TO REDUCE POWER BY USING RNS SYSTEM
Different types power optimization level can be done in a circuit,
• Algorithm level .
• Architecture level .
• Arithmetic level .
• Implementation level *
• Technology level
Since RNS is all about number system ,so that we can reduce the power in terms of arithemetic
level.
As said RNS systems gives a greater advantages in implementing DSP Architectures These
advantages are mainly related to the absence of carry propagation among modular blocks.Due to
this there will be several other advantages too that
• Structure will be simpler

• So that speed will be higher
• signals are more local (in fact signals are bounded inside each modular block) The main
objective of this paper is to evaluate
As a general condition, we can observe that different technologies have different characteristics
with respect to power consumption model. In particular: .
• ASIC-SC (Standard Cells) are characterized by very variable logic and interconnect
structures. .
• FPGAs have, on the other hand, fixed structure with CLBs, clock and interconnects.
Consequently, the general evaluation of power consumption contributions is more
complex for ASICS
Consider Ax and P1 represent the area and the power consumption of filter, and x identifies the
number system representation used in the actual implementation. As said , x can take the two
values RNS or TCS.
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The constants k1 represent the offset of the plots (two different values apply for area and power)
while k2 are the growing rate values.
Graph has plotted in these equation.

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From these plots, we observe that the RNS has less power consumption This is related to the
presence of input and output converters. Similarly Area needed for RNS implementation is less
compare to TNS System.
Implementation to reduce power consumption
As said ,more complex structure is ASIC-SC System,The power consumption in the

implementation can be found bu number of analysis.
Power consumption contributions are divided between local and global interconnects. While local
interconnects route signals inside a functional block, global interconnects route signals among
different blocks .This contribution of power can be divided in to three sets
1) power required for gate charging

2) power required for interconnect capacitance
3) power required for charging diffusion capacitances
These the are important power drawing parameters in a circuit.As we decreasing theses we can
minimize the power,at some other cost.
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Now let us calculate the power consumption by using RNS systems. In ASIC-SC technology,
carry propagation properties of RNS potentially give the following area-power benefits:
1) reduction ofcomplexity (number of gates - area),
2) reduction of interconnection capacitance
The comparisons of power minimization by RNS and TNS canbe found from the power ratio as
Power minimization in FPGA
In FPGA implementations factor weights are quite different. An analysis oft he FPGA power
consumption identifies three main contributions ,
1) power consumption in logic and IOB;
2) power consumption in clocking structure;
3) power consumption in interconnects
Thus by using RNS System power usage can be reduced in great extend.
REFERENCES
[1] G.C. Cardarilli, A. Nannarelli and M. Re. "Reducing Power Dissipation in FIR Filters using
the Residue Number System", Proc. of43rd IEEE Midwest Symposium on Circuits and Systems,
p. 320-323, Lansinig, USA, Aug. 2000
[2] Gian Carlo Cardarilli(l), Alberto Nannarelli(2), Marco Re(') “Residue Number systems for
Low Power Application” )Dept. of Electronic Engineering University of Rome "Tor Vergata" (2)
Department of Informatics & Math Modelling Technical University of Denmark

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17MVD0089

APPLICATION OF RNS IN THE DSP ARCHITECTURE

• Minimize power consumption

❖ POWER REDUCTION IN DSP ARCHITECTURE

❖ SMALL OVERVIEW OF RNS SYSTEMS

Any no: has unique RNS representation given by,,

❖ HOW TO REDUCE POWER BY USING RNS SYSTEM

Different types power optimization level can be done in a circuit,

• Structure will be simpler

Graph has plotted in these equation.

Implementation to reduce power consumption

As said ,more complex structure is ASIC-SC System,The power consumption in the

1) power required for gate charging

1) reduction ofcomplexity (number of gates - area),

2) reduction of interconnection capacitance

Power minimization in FPGA

1) power consumption in logic and IOB;

2) power consumption in clocking structure;

3) power consumption in interconnects

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