Verilog HDL

coding style for Synthesis

 Modeling/Coding style?

 Modeling style have a marked impact on the type of netlist

generated after logic synthesis.

 Current synthesis tools can accept only a subset of constructs of

Verilog or VHDL.

 The subset may vary from one synthesis tool to another.

 Functionally equivalent simulation models need not necessarily

produce same synthesis outputs
 Inferring Combinational Logic

 Combinational logic can be inferred from Verilog codes in several

ways.

 Based on the type of variable declaration (reg or wire), always block

and assign statements can be used to infer COMBO.

 Care should be taken in the choice of the Verilog constructs used to

infer COMBO.
Inferring a Multiplexer using if-else statement
a
reg d_out ; M
always @ (a or b or en) U
if (en) X d_out
b
d_out = a ;
else
d_out = b; en
a
 The if ... else construct is completely specified.

 The modeled logic is a combinational b

multiplexer.

en
 Priority encoded Multiplexer using if-else if
statement
 Depending on the choice of “select” inputs, if - else if can be effectively used to
model priority encoded “cascading” multiplexers.

always @(a or b or c or d or en)

en[2] en[1] en[0]
if (en[2] == 1’b1)
out = a; 0 0 0
else if (en[1] == 1’b1) 0 0 1
0 1 0
out = b; 0 1 1
else if (en[0] == 1’b1) 1 0 0
out = c; 1 0 1
1 1 0
else 1 1 1
out = d;
 Priority encoded Multiplexer using if-else if
statement

 Priority encoded “cascading” multiplexers.

d 0

c 1
0
en[0]
b 1
0
en[1] out
a 1

en[2]
 Synthesis of Case statements

 Case statements can synthesize to combinational or sequential logic.

 This depends upon whether the case alternatives are completely

specified or not.

 A completely specified case construct can infer purely combinational

multiplexers with its select lines activated on a priority basis.

 Incomplete case specification infer latches.

Inferring a Multiplexer using Case statement
 Case statements infer faster and “large” (occupy more silicon area)
multiplexers.

always @(a or b or c or d or en)

begin
case (en) a
2’b00 : d_out = a; M
b
2’b01 : d_out = b; U
2’b10 : d_out = c; c X d_out
default : d_out = d; d
2
endcase
end en
 Incomplete case statements infer latches
 When a case statement specifies only a partial list of alternatives, a latch is
inferred.

• In this sample code, the

always @(a or b or c or en) case alternative for en = 11 is
begin not specified.
case (en) • This makes the synthesis
2’b00 : d_out = a; tool to infer a latch to store
2’b01 : d_out = b; the previous value of d_out
2’b10 : d_out = c; when en = 11 is encountered.
endcase
end
 Avoiding inference of latches in Case
statements
 Latch inference can be avoided by either an unconditional assignment or
using default statements.

always @(a or b or c or en) always @(a or b or c or en)

begin begin
d_out = a; case (en)
case (en) 2’b00 : d_out = a;
2’b00 : d_out = a; 2’b01 : d_out = b;
2’b01 : d_out = b; 2’b10 : d_out = c;
2’b10 : d_out = c; default : d_out = a;
endcase endcase
end end
 Tips to avoid unintentional latches in Case & if-else if
statements

 For both Case and if-else if statements, it is necessary to specify all

clauses (alternatives).

 It is also necessary to specify all outputs for every alternative in Case

and if - else if statements.
Synthesis of For loops
 for loops can be used to infer cascaded combinational logic blocks.
 for loops cannot contain any timing or event control constructs.

integer k; will be synthesized as a series of sequential

assignments as follows:
always @ (x or y)
sample[0] <= x[0] or y[4];
begin sample[1] <= x[1] or y[3];
for ( k = 0; k < 5; k = k + 1) sample[2] <= x[2] or y[2];
sample[k] = x[k] | y[4 - k]; sample[3] <= x[3] or y[1];
sample[4] <= x[4] or y[0];
end
Equivalent gate level representation
sample[0]
x[0]
y[4]

x[1] sample[1]
y[3]

sample[2]
x[2]
y[2]

sample[3]
x[3]
y[1]

sample[4]
x[4]
y[0]
Synthesis of For loops
integer k;
for ( k = 0; k <= 7; k = k + 1)
{ c_temp, sum[k] } = a_in[k] + b_in[k] + c_in;
c_out = c_in;
end

• The above piece of for loop code would typically synthesize

to an 8-bit ripple carry adder.
 The assign statement
 The assign statement in Verilog can be used to synthesize
combinational logic.

assign d_out = (a | b) & c; translates to:

a
b

c d_out

If a, b, c and d_out are multi-bit vectors, say 3-bit vectors, then,

three identical circuits as above would be generated.
The ternary ? operator

 The ternary conditional operator ? typically infers a combinational

multiplexer circuit.

assign d_out = (en ? b : a);

d_out
b

en
General coding guidelines for
efficient synthesis
General coding guidelines for efficient synthesis

 Do not mix positive and negative edge triggered flip-flops in the same
design

 assign statements typically result in random COMBO logic, gate

instantiations in structured COMBO logic.

 Choice between assign & gate instantiations depends on optimization

strategy, concise representation, complexity of design and technology
re-targeting.
Instantiation of MUX Vs. Case & if-else

 Instantiating a multiplexer is preferred than using an if - else or case

statement when structured implementation with faster synthesis
results are needed.

 But instantiation makes it technology dependent and elaborate RTL

description.

 if-else and Case statements create technology independent and

concise representations.
 Use of arithmetic operators Vs. Design blocks

 Arithmetic operators lead to large gate level logic, but result in

concise representation of code in a technology independent
manner.

 Designing custom blocks for arithmetic functions can take longer

duration, but makes it more technology dependent.
 Use of Parentheses

 Parentheses plays vital role in the type of logic implemented.

a b c d
F = a + b + c + d;
would typically be
implemented as:

(a + b) is grouped together
by default,
then c and d are added one
at a time.
z
 Use of Parentheses

F = (a + b) + (c + d);
would typically be implemented a b c d
as:

Parentheses use leads to a

faster implementation of the
addition.
z
 Order dependency Non blocking Vs.
blocking
• Blocking statements are executed in the order which they have
been represented.
• Non-blocking assignments are executed independent of the order
of specification

always @(negedge CK)

begin
a <= x | y; x
D Q D Q c
y D Q
b <= a;
c <= b; CK

end
 Order dependency Non blocking Vs.
blocking
• In the sample code shown, the order of the non-blocking
assignments have been changed.
• But an identical logic will be generated by the synthesis tool.

always @(negedge CK)

begin
c <= b; x
D Q D Q c
y D Q
b <= a;
a <= x | y; CK

end
 Order dependency Non blocking Vs.
blocking
•Blocking assignment example

always @(negedge CK)

begin
a = x | y;
b = a;
c = b;
x c
end y D Q

CK
 Order dependency
Non blocking Vs. blocking
•A blocking assignment with order changed

always @(negedge CK)

begin
c = b; x
D Q D Q c
y D Q
b = a;
a = x | y; CK

end
 Non blocking Vs. blocking assignments with
multiple drivers

• Multiple blocking assignments are evaluated as they occur.

• Multiple non-blocking assignments are scheduled, hence only the last

assignment is synthesized.

• Synthesis tools generally do not support both blocking and non-blocking

assignments to the same signal.
Use of Non blocking & blocking
assignments
• It is recommended to use non-blocking assignments exclusively
within sequential always blocks.

• In combinational logic blocks, it is recommended to use as much

blocking assignments as possible.
 Inferring a level sensitive latch

reg d_out ;

d_in d_out always @ (d_in or en)

Latch
begin
if (en == 1’b1)
d_out = d_in ;
end

en

 When “en” is not true, the previous value of d_out is stored.

 Since there is no specification of a clock edge using posedge or

negedge, a latch is inferred.
 How to avoid a Latch inference ?

always @ (d_in or en)

begin
d_in COMBO d_out
if (en)
d_out = d_in;
else
d_out = 0;
end
en

 When “en” is not true, the d_out is assigned to 0, i.e...

d_out is assigned a value under all conditions, avoiding a
latch inference.
 Inferring a Level sensitive Latch with Set and Reset
reset set

reg data_out ;
always @(d_in or en or set or reset)
if (set) d_in d_out
d_out = 1’b1 ; Latch
else if (reset)
d_out = 1’b0 ;
else if (en)
d_out = d_in;
en

 d_out is assigned to data_in only when set

and reset are inactive and en is active.
Inferring a Level sensitive Latch with Set
and Reset
 Edge sensitive D-Flip flop

reg d_out ;
always @ (posedge clk) Edge
d_out = d_in; d_in sensitive d_out
Flip-flop

 An edge triggered flip-flop is inferred if a clk

variable assignment is executed only on the
leading or trailing edge of another variable.
en
 posedge and negedge are Verilog keywords
used to represent leading and trailing edges
respectively.
 Edge sensitive D-Flip flop with
Synchronous Set and Reset
reg d_out ; reset set
always @(posedge clk)
if (set)
d_out = 1’b1 ;
Edge
else if (reset) d_in sensitive d_out
d_out = 1’b0 ;
Flip-flop
else
d_out = d_in; clk

 Conditional assignments to d_out is done inside the if clause and they

translate into combinational logic in front of the D-input of the flip-flop.
 The sensitivity list should contain only clk variable.
Edge sensitive D-Flip flop with Synchronous Set and
Reset - Hardware
Edge sensitive D-Flip flop with Asynchronous Set and
Reset

reset set
reg d_out ;
always @(posedge clk or
posedge set or posedge reset)
Edge
if (set) d_in sensitive d_out
d_out = 1’b1 ;
else if (reset) Flip-flop
d_out = 1’b0 ; clk
else
d_out = data_in;
en
Edge sensitive D-Flip flop with
Asynchronous Set and Reset -Hardware
 Edge sensitive D-Flip flop with
Asynchronous Set and Reset

 For asynchronous set and reset, both the set and reset variables must be in
the sensitivity list.

 Asynchronous assignments can be done using else if clauses and they should
occur first based on priority.
 Synchronous assignments should come last one in the if clause.

 A flip-flop is generated for each signal that is assigned in the synchronous

assignment.

 The asynchronous clauses result in combinational logic that drives the set
and reset inputs of the flip-flops.
 General limitations of D-Flip flop inference

 The signal in an edge expression of the always block cannot be

an indexed.
always @ (negedge clk[1]) ---> clk is indexed.

 Set - Reset conditions must be constructed only using single bit

variables.

 Set and reset conditions cannot use complex expressions.

 How to get good results in Flip-flop inferences ?

 A flip-flop is generated for each signal that is assigned in the

synchronous assignment.

 i.e.. an always block that contains a clock edge in the

sensitivity list infers a flip-flop for each variable assignment that
block.

 It is necessary to make sure the HDL description builds only as

many flip-flops as the design requires.
 How to get good results in Flip-flop inferences ?
• In this example, the
always block includes
module count (CLK, RST, AND_L, OR_L, XOR_L); assignments to
input CLK, RST; calculate the reduction
output AND_L, OR_L, XOR_L; AND, OR and XOR logic.
reg AND_L, OR_L, XOR_L;
reg [2:0] CNT; • The reduction AND,
always @(posedge CLK) begin OR and XOR outputs
if (RST) solely depend on the
CNT = 0; registered output CNT.
else
begin • Hence it is not
CNT = CNT + 1; necessary to register
AND_L = & CNT; the logic outputs again,
OR_L = | CNT; instead an asynch.
XOR_L = ^ CNT;
always block with CNT
end
endmodule
variable is sufficient.
Recommended Coding style for FSMs

• A single case statement may be preferred for Mealy

machines where the outputs depend on the the current state
as well as the primary inputs.

• Separate case statements are more suited for Moore

machines where the outputs depend only on the current state.

• Coding one FSM per module is recommended.

 Recommended Coding style for FSMs

• Use parameters to describe the state names.

• Logic which do not affect the outputs of the FSM should not

be part of the FSM module.

• Resetting the FSM to a desired state must be included.

 Recommended Coding style for FSMs
• If case default state transitions are not important, then state and
output values can be assigned with ‘x’, so that they are treated as
don’t cares.
• Inclusion of more don’t cares leads to better optimization.
• Do not code a default statement as
default: next_state <= current_state;
 Recommended Coding style for FSMs

• Instead, a valid state (say to RESET) and a constant output

value should be assigned.

• It is recommended that the outputs in the FSM are expressed

explicitly in each state for better optimization.
 1. Samir Palnitkar,”Verilog HDL: A Guide
to Digital Design and Synthesis”
Prentice Hall, Second Edition,2003
2. T.R.Padmanabhan and B.Bala Tripura
Sundari, “Design Through Verilog
HDL” Wiley Student Edition
3. J.Bhaskar, “ Verilog HDL Synthesis”
BS publications

Reference