International Journal of Computer Applications (0975 – 8887)

Volume 70– No.9, May 2013

Design of Low Power Digital FIR Filter based on

Bypassing Multiplier

Prabhu E Mangalam H Saranya K

Assistant Professor, ECE Professor & Head, ECE PG Student
Amrita schools of Engineering, Sri Krishna college of Engineering Sri Krishna college of Engineering
Coimbatore and Technology, Coimbatore and Technology, Coimbatore

ABSTRACT processing algorithms performance is generally determined by

Low power design promotes longer battery life in portable the performance of the multiplier. Many multiplier design
applications and reduces heat dissipation in high performance based on the reduction of the switching activities reported in
applications. Multiplication is one of the important operations literature. Basically there are many approaches for designing a
in digital signal processing and their power dissipation is the low-power multiplier [4]; one is by designing a low-power FA
prime concern. Many earlier multiplier designs were analyzed in an array multiplier. The second approach is by reducing the
to reduce the switching transition. Bypassing technique is partial product computation [6]. The other important approach
mainly used to reduce the switching power of the multiplier. to reduce the power dissipation is by the architectural
Various bypassing multipliers such as Row bypassing, modification via bypassing techniques. A finite impulse
Column bypassing, Two-dimensional bypassing and Row- response (FIR) filter is a type of a signal processing filter
Column bypassing based multipliers were designed based on whose impulse response is of finite interval, because it settles
the simplification of the incremental adders and half adders to zero in finite time [11]. This is in disparity to infinite
instead of full adders in an array multiplier. In these impulse response (IIR) filters, which have internal feedback
multipliers extra correction circuits are required to obtain and may keep on responding for an indefinite period.
accurate results. The extra hardware in conventional design Multiplier is one of the basic functional units in FIR filter
results in more power consumption. So, to overcome the design which consumes most of the power. So, it is necessary
drawback of conventional methods, the proposed low power to design low-power multiplier for FIR filters. This paper
bypassing based multiplier uses a simplified addition presents a low power FIR filter based on bypassing multiplier.
operation to reduce the switching activity and it achieves The rest of this paper is organized as follows. Section 2
38.7% and 25.2% of area and power reduction respectively. reviews the Braun array multiplier design and previous work
By taking the advantage of low power bypassing based on multiplier with bypassing methods. Section 3 describes the
multiplier, a digital FIR filter is implemented. The low power bypassed based multiplier design for digital FIR
experimental results show that our proposed low power digital filter. The Section 4 gives simulation results and discussion.
FIR filter saves 51% and 7% of area and power reduction Finally, Section 5 offers a brief conclusion.
respectively by using low power bypassing based multiplier.
2. RELATED WORK
General Terms 2.1 Braun array Multiplier
VLSI design. The Braun array multiplier [8] consists of three functions:
partial-product generation, partial-product accumulation, and
Keywords final addition. First, partial-product generation requires N×N
Bypassing logic, Low power design, FIR filter design, AND gates of two inputs. Second, partial-product
Switching activity reduction. accumulation requires (N−1) rows of carry-save adders, in
which every row consists of (N−1) full adders, and the final
1. INTRODUCTION addition that contains a (N−1) bit ripple-carry adder in the last
Low power design is necessary to extend the operating time of row is for carry propagation. Therefore, an N×N bits array
integrated circuits (ICs) as well as to reduce the packaging multiplier requires N× (N−1) full adders. Because Braun array
and cooling costs [1, 2]. As the scale of integration keeps multipliers have higher switching activity, one way to reduce
growing, more and more complex signal processing systems dynamic power, is to avoid redundant switching transitions.
are being implemented on a VLSI chip. These signal The following section describes four bypassing multiplier
processing applications consume considerable amount of designs to reduce dynamic power, and explains the area
energy. The trade-off of performance and area remain to be overhead problem in the conventional bypassing multiplier
the two major design factors, high power consumption is design.
critical in today’s VLSI system design. The need for low-
power VLSI system arises from two main forces. First, Static
power dissipation is due to the leakage current. Second, 2.2 Braun multiplier with row bypassing
Dynamic power dissipation is due to the transition activity For a low-power row-bypassing Braun multiplier [6] the
that dominates the total energy dissipation due to charging addition operations in the j-th row can be disabled to reduce
and discharging of capacitors. Multiplication is a fundamental the power dissipation if the bit bj in the multiplier is 0. In the
operation in most signal processing algorithms [3]. Multipliers multiplier design, each modified FA in the CSA array is
have large area, long latency and consume considerable attached by three tri-state buffers and two 2-to-1 multiplexers.
power. Therefore low-power multiplier design has been an Because the addition operations of the rightmost FAs in the
important part in low- power VLSI system design. The CSA rows are able to be bypassed, the extra correcting

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 International Journal of Computer Applications (0975 – 8887)
Volume 70– No.9, May 2013

circuits must be added to correct the multiplication result. The 2.4 Braun multiplier with 2-dimensional
4X4 Braun multiplier with row bypassing is shown in Fig. 1.
bypassing
For a low-power 2-dimensional bypassing-based multiplier
[4], it is desired that the addition operations in the (i+1)-th
column or the j-th row can be bypassed if the bit, ai, in the
multiplicand is 0 or the bit, bj, in the multiplier is 0. To
correct the carry propagation in the multiplication result, the
carry bit must be considered in the bypassing condition as
follows: If the bit, ai and bj, are 0 and the carry bit, ci,j-1, is 1,
the addition operations in the (i+1)-th column or the j-th row
cannot be bypassed. Hence, the bypassing circuit must be
added into the necessary FA to form a correct adder cell (AC).
However, the inserted bypassing circuit in AC is so
complicated that the ability of the power reduction is
decreased. The 4x4 Braun multiplier with 2-dimensional
bypassing is shown in Fig. 3.

Fig. 1 4x4 Braun multiplier with row bypassing [6]

2.3 Braun multiplier with column

bypassing
For a low-power column-bypassing multiplier [5], the
addition operations in the (i+1)-th column can be bypassed if
the bit, ai, in the multiplicand is 0. In the multiplier design, the
modified FA is simpler than that in the row bypassing
multiplier. Each modified FA in the CSA array is only
attached by two tri-state buffers and one 2-to-1multiplexer. As
the bit, ai, in the multiplicand is 0, their inputs in the (i+1)-th
column will be disabled and the carry output in the column
must be set to be 0 to produce the correct output. Hence, the
protecting process can be done by adding an AND gate at the Fig. 3 4x4 Braun multiplier with 2-dimensional
outputs of the last row of CSAs. The 4X4 Braun multiplier bypassing [4]
with column bypassing is shown in Fig. 2.
2.5 Braun multiplier with row and column
bypassing

Fig. 4 4x4 Braun multiplier with row and column

bypassing [3]
Fig. 2 4x4 Braun multiplier with column bypassing [5]
According to the bypassing features in the previous Braun
array with row or column bypassing multipliers [3], the
addition operations in the (i+1)-th column or the j-th row can
be bypassed for the power reduction if the bit, ai, in the

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 International Journal of Computer Applications (0975 – 8887)
Volume 70– No.9, May 2013

multiplicand is 0 or the bit, bj, in the multiplier is 0.But in row product, aibj, is not equal to the carry bit, ci,j-1. On the other
and column bypassing based multiplier, the addition operation hand, as the product, aibj, is equal to the carry bit, ci,j-1, the
in the (i+1, j) FA can be bypassed if the product, aibj, is 0and addition result in the (i+1, j)-th FA will be obtained by adding
the carry bit, ci,j-1, is 0, that is, as the product, aibj, is 1 or the 2 or 0. Therefore, the resultant carry bit, ci+1, j, in the (i+1, j)-
bit, ci,j-1, is 1, the addition operation in the (i+1, j) FA can be th FA can be bypassed from the previous carry bit, ci, j-1, and
executed. It is known that the (i+1, j) FA only executes the the (i+1, j)-th FA can be replaced with a low-cost incremental
A+1addition as the product, aibj, is 1 and the bit, ci,j-1, is 0, adder, A+1. Besides that, each simplified adder, A+1, in the
or the product, aibj, is 0 and the bit, ci,j-1, is 1. On the other CSA array is only attached by one tri-state buffer and two 2-
hand, the (i+1, j) FA only executes the A+2 addition as the to-1 multiplexers. Similarly, a HA can be also replaced with a
product, aibj, is 1 and the bit, ci, j-1, is 1.The 4X4 Braun low-cost incremental adder, A+1, with the bypassing
multiplier with row and column bypassing [3] shown in Fig. condition as aibj=0. By using the bypassing-based design of a
4. half adder and a full adder, a 4x4 low-power bypassing-based
multiplier can be designed. The 4x4 low power bypassing
3. PROPOSED DESIGN based multiplier, as shown in Fig. 5.
A Low power multiplier based on bypassing technique for For a discrete-time FIR filter, the output is a weighted sum of
digital filter is based on 2-dimensional bypassing feature, the
the current and a finite number of previous values of the input
addition operations in the (i+1)-th column or the j-th row can
be bypassed for the power reduction if the bit, ai, in the [11]. The operation is described by the following equation(1),
multiplicand is 0 or the bit, bj, in the multiplier is 0. On the which defines the output sequence y[n] in terms of its input
other hand, to correct the carry propagation in the sequence x[n]:
multiplication result, the carry bit in the previous row must be
considered in 2-dimensional bypassing condition. In our
proposed low-power bypassing-based multiplier, the addition
operation in the (i+1, j)-th FA can be bypassed if the product,
aibj, is equal to the carry bit, ci,j-1, that is, as the product, aibj,
is not equal to the bit, ci,j-1, the addition operation in the (i+1,
j)-th FA must be executed. Hence, the control signal in the Where,
bypassing condition can be obtained by the XOR result of the x[n] is the input signal, y[n] is the output signal, bi are the
product, aibj, and the carry bit, ci, j-1. filter coefficients, also known as tap weights, that make up the
impulse response, N is the filter order, an Nth-order filter has
(N + 1) terms on the right-hand side. Here, x [n-i] in these
terms are commonly referred to as taps. A 4 tap FIR filter
show in Fig. 6, for low power bypassing based multiplier.

Fig. 5 4x4 low power bypassing-based multiplier Fig. 6 Four tap digital FIR filter based on low power
According to the proposed bypassing condition, it is known bypassing based multiplier.
that the (i+1, j)-th FA only executes the A+1 addition as the

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 International Journal of Computer Applications (0975 – 8887)
Volume 70– No.9, May 2013

4. SIMULATION RESULTS AND 5. CONCLUSION

DISCUSSION The design approach of an optimized FIR filter using different
The simulation results for the bypassing based multipliers are bypassing multipliers is discussed. Compared to other
shown in Table 1. The XILINX ISE 9.2i with Spartan2E as bypassing multipliers a new methodology for designing of
target device is used to synthesis the program and ModelSim high-level optimization technique based on the simplification
DE 6.5e to simulate the results. The building blocks are coded of the addition operations in a low-power bypassing-based
in VHDL. The XILINX ISE 9.2i with Spartan2E as target multiplier for FIR filter is proposed to reduce the switching
device is used to analyze the total estimated power consumed activity. The simulation result shows that the proposed low
by the bypassing techniques. The area analyses of bypassing power FIR filter using bypassing multiplier achieves higher
based multipliers are carried out using XILINX ISE 9.2i. power reduction with lower hardware cost than the other
Performance of the proposed FIR filter using low power conventional FIR filter using different multipliers.
consumption multiplier by comparing with the different
conventional multipliers is given blow.
6. REFERENCES
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Table 1. Comparison of area and power of FIR filter
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