Week 4 Assignment

Week 4 Assignment Questions & Answers
1. The instruction RST 7 is a:

a. Restart instruction that begins the execution of a program.
b. One-byte call to the memory address 0038H.
c. One-byte call to the memory address 0007H.
d. Hardware interrupt.
Answer: b. One-byte call to the memory address 0038H.
Hint: Slide 3 of Week 4 Lecture Slides
2. The opcode of the instruction RST 6 in an 8085 microprocessor is:

a. F7
b. 7F
c. FE
d. EF
Answer: a. F7
Hint: Slide 7 of Week 4 Lecture Slides
3. Which of the following statements is TRUE?

a. Vectored interrupts, whose equivalent vectors are 003CH and 002CH, are level
sensitive and positive edge sensitive, respectively.
b. Vectored interrupts, whose equivalent vectors are 003CH and 0034H, are both level
sensitive.
c. Vectored interrupts, whose equivalent vectors are 0034H and 002CH, are level
d. Vectored interrupts, whose equivalent vectors are 0034H and 003CH, are level
Answer: d. Vectored interrupts, whose equivalent vectors are 0034H and 003CH, are level sensitive
and positive edge sensitive, respectively.
Hint: Slides 16 and 27 of Week 4 Lecture Slides
4. What does the following set of instructions do in an 8085 microprocessor?

EI
MVI A, 08H
SIM
a. Resets the 7.5 interrupt in an 8085 system.
b. Enables all the interrupts in an 8085 system.
c. Enables the 5.5 interrupt and masks all other interrupts in an 8085 system.
d. Enables the 6.5 interrupt and masks all other interrupts in an 8085 system.
Answer: b. Enables all the interrupts in an 8085 system.
Hint: Slides 21 – 26 of Week 4 Lecture Slides

5. After the execution of instruction RIM, the accumulator contained 49H. Which of the
following statement is TRUE in this case?
a. RST 5.5 is enabled and is pending.
b. RST 6.5 is enabled and is pending.
c. RST 7.5 is enabled and is pending.
d. None of the given options.
Answer: c. RST 7.5 is enabled and is pending.
Hint: Slides 28 – 34 of Week 4 Lecture Slides.
6. Which of the following is the correct ordering of the priority of the interrupts in 8085
a. TRAP > RST 7.5 > RST 6.5 > RST 5.5
b. RST 7.5 > RST 6.5 > RST 5.5 > TRAP
c. TRAP > RST 5.5 > RST 6.5 > RST 7.5
d. RST 5.5 > RST 6.5 > RST 7.5 > TRAP
Answer: a. TRAP > RST 7.5 > RST 6.5 > RST 5.5.
Hint: Slides 36 of Week 4 Lecture Slides.
7. Which of the following statements is/are true?
Statement I: RST 7.5 is positive edge sensitive and can’t be triggered with a short pulse
Statement II: RST 6.5 and RST 5.5 are both level sensitive, meaning that the trigger level
should be off until the microprocessor completes the execution of the current instruction.
a. Only I is true
b. Only II is true
c. All are true
d. All are false
Answer: d. All are false

8. Which of the following statements is/are true?
Statement I:
INTR: Maskable Non-Vectored With memory
Statement II:
INTR: Non-Maskable Vectored Without memory
Statement III:
RST7.5: Maskable Vectored Without memory
Statement IV:
RST7.5: Maskable Vectored With memory
a. I and II are true

b. Only II is true
c. Only IV is true
d. II and IV are true
Answer: c. Only IV is true
9. Which of the following statement is true in the context of Simplex, Half-duplex, and Full-
duplex transmission?
Statement I: Both Half-duplex and Full-duplex are bidirectional communication and in both
the cases, data flows in two directions at the same time
Statement II: Both Half-duplex and Full-duplex are bidirectional communication where data
flows in two directions in Full-duplex; however, data flows in one direction in Half-duplex
Statement III: Simplex and Half-duplex requires one wire for data transmission
Statement IV: Both Half-duplex and Full-duplex require two wires for data transmission
a. I and III are true

b. Only II is true
c. Only IV is true
d. II and III are true
Answer: d. II and III are true
10. Which of these are not error checking methods?

a. Parity Check
b. Checksum
c. Cyclic Redundancy Check
d. Huffman Code
Answer: d. Huffman Code

11. Which of the following statement is correct:
Statement I: Asynchronous Serial Data transfer is used for data transfer rates ≤ 20K
bits/second.
Statement II: Synchronous Serial Data transfer is used for data transfer rates ≥ 20K
bits/second.
a. Only Statement I
b. Only Statement II
c. Both Statement I and II
d. None of the above
Answer: c. Both Statement I and II
Hint: Slides 41 and Slide 42 of Week 4 Lecture Slides.
12. To which pin external DMA controller sends a control signal to an 8085 microprocessor.
a. HOLD
b. HLDA
c. INTR
d. INTA
Answer: a. HOLD
13. With respect to an 8085 microprocessor, match Column X with Column Y.

Column X Column Y
1. INTR 1. Non-maskable
2. RST 5.5 2. Maskable
3. TRAP 3. Software
4. RST 1 4. Non-vectored
a. X1-Y2, X2-Y1, X3-Y4, X4-Y3
b. X1-Y4, X2-Y2, X3-Y1, X4-Y3
c. X1-Y3, X2-Y2, X3-Y4, X4-Y1
d. X1-Y1, X2-Y4, X3-Y2, X4-Y3
Answer: b. X1-Y4, X2-Y2, X3-Y1, X4-Y3
14. Interrupt vector table of 8085 ranges over

a. 0010H – 0100H
b. 0000H – FFFFH
c. 0000H – 00FFH
d. 0100H – 01FFH
Answer: c. 0000H – 00FFH

15. With respect to an 8085 match Column X with Column Y.
Column X Column Y
1. RST 5.5 1. Edge-triggered
2. RST 6 2. Level-triggered
3. RST 7.5 3. Edge- and Level-triggered
4. RST 4.5 4. Software
a. X1-Y3, X2-Y1, X3-Y4, X4-Y2
b. X1-Y4, X2-Y2, X3-Y1, X4-Y3
c. X1-Y2, X2-Y4, X3-Y1, X4-Y3
d. X1-Y3, X2-Y4, X3-Y2, X4-Y1
Answer: c. X1-Y2, X2-Y4, X3-Y1, X4-Y3
16. To be surely sensed, in 8085, INTR must be high for number of T-states equal to
a. 1.5
b. 17.5
c. 18.5
d. 19.5
Answer: b. 17.5
17. The READY pin of 8085 is used

a. By the microprocessor to tell the device when it is ready
b. By the devices to tell the microprocessor when it is ready
c. For input/output operations
d. All of the other three options
Answer: b. By the devices to tell the microprocessor when it is ready
18. Suppose that the stack pointer (SP) of 8085 contains 2000H. If the instruction "POP D" is
used, the value of SP will be
a. 2002H
b. 2000H
c. 2006H
d. 2008H
Answer: a. 2002H
19. In a 8085 processor, suppose the accumulator content is FFH and the carry flag is 0. What
will be the content of the accumulator in RAL and RLC instructions?
a. Both FFH
b. Both FEH
c. RAL – FFH, RLC – FEH
d. RAL – FEH, RLC – FFH
Answer: d. RAL – FEH, RLC – FFH
20. In 8085 ALE signal is generated in clock cycle

a. T1
b. T2
c. T1 and T2
d. T3
Answer: a. T1

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Week 4 Assignment Questions & Answers

1. The instruction RST 7 is a:

Answer: b. One-byte call to the memory address 0038H.

Hint: Slide 3 of Week 4 Lecture Slides

2. The opcode of the instruction RST 6 in an 8085 microprocessor is:

Hint: Slide 7 of Week 4 Lecture Slides

3. Which of the following statements is TRUE?

Hint: Slides 16 and 27 of Week 4 Lecture Slides

4. What does the following set of instructions do in an 8085 microprocessor?

Answer: b. Enables all the interrupts in an 8085 system.

Hint: Slides 21 – 26 of Week 4 Lecture Slides

Answer: c. RST 7.5 is enabled and is pending.

Hint: Slides 28 – 34 of Week 4 Lecture Slides.

Hint: Slides 36 of Week 4 Lecture Slides.

7. Which of the following statements is/are true?

Answer: d. All are false

8. Which of the following statements is/are true?

a. I and II are true

Answer: c. Only IV is true

Hint: Slides 37 of Week 4 Lecture Slides.

a. I and III are true

Answer: d. II and III are true

Hint: Slides 44 of Week 4 Lecture Slides.

10. Which of these are not error checking methods?

Answer: d. Huffman Code

Hint: Slides 48 of Week 4 Lecture Slides.

Answer: c. Both Statement I and II

Hint: Slides 41 and Slide 42 of Week 4 Lecture Slides.

Hint: Slides 38 of Week 4 Lecture Slides.

13. With respect to an 8085 microprocessor, match Column X with Column Y.

Answer: b. X1-Y4, X2-Y2, X3-Y1, X4-Y3

14. Interrupt vector table of 8085 ranges over

Answer: c. 0000H – 00FFH

Answer: c. X1-Y2, X2-Y4, X3-Y1, X4-Y3

17. The READY pin of 8085 is used

Answer: b. By the devices to tell the microprocessor when it is ready

Answer: d. RAL – FEH, RLC – FFH

20. In 8085 ALE signal is generated in clock cycle

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