8-Bit Microcontroller With 8K Bytes In-System Programmable Flash AT90PWM1
8-Bit Microcontroller With 8K Bytes In-System Programmable Flash AT90PWM1
8-Bit Microcontroller With 8K Bytes In-System Programmable Flash AT90PWM1
4378A–AVR–06/06
• Operating Voltage: 2.7V - 5.5V
• Extended Operating Temperature:
– -40°C to +105°
1. History
Product Revision
AT90PWM1 First revision of parts
2. Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max val-
ues will be available after the device is characterized.
3. Pin Configurations
Figure 3-1. SOIC 24-pin Package
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AT90PWM1
3.1 Pin Descriptions
:
Table 3-1. Pin out description
S024 Pin Number Mnemonic Type Name, Function & Alternate Function
Analog Power Supply: This is the power supply voltage for analog part
17 AVCC Power
For a normal use this pin must be connected.
Analog Reference : reference for analog converter . This is the reference voltage of the
19 AREF Power
A/D converter. As output, can be used by external analog
PSCOUT01 output
24 PB7 I/O ADC4 (Analog Input Channel 4)
SCK (SPI Clock)
PSCOUT00 output
1 PD0 I/O XCK (UART Transfer Clock)
SS_A (Alternate SPI Slave Select)
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Table 3-1. Pin out description (Continued)
S024 Pin Number Mnemonic Type Name, Function & Alternate Function
4. Overview
The AT90PWM1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90PWM1 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
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AT90PWM1
4.1 Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The AT90PWM1 provides the following features: 8K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose
I/O lines, 32 general purpose working registers, 2 Power Stage Controllers, two flexible
Timer/Counters with compare modes and PWM, an 8-channel 10-bit ADC with two differential
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input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, an On-chip Debug system and four software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt
system to continue functioning. The Power-down mode saves the register contents but freezes
the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The
ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch-
ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90PWM1 is a powerful microcontroller that provides a highly flexible and cost effec-
tive solution to many embedded control applications.
The AT90PWM1 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
4.2.1 VCC
Digital supply voltage.
4.2.2 GND
Ground.
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AT90PWM1
4.2.5 Port E (PE2..0) RESET/ XTAL1/
XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-
acteristics of PE0 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 9-1 on page 42. Shorter pulses are not guaranteed
to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page
70 and “Clock Systems and their Distribution” on page 26.
4.2.6 AVCC
AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
4.2.7 AREF
This is the analog reference pin for the A/D Converter.
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5. AVR CPU Core
5.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Program Status
Flash
Counter and Control
Program
Memory
Interrupt
32 x 8 Unit
Instruction General
Register Purpose SPI
Registrers Unit
Instruction Watchdog
Decoder Timer
Indirect Addressing
Direct Addressing
ALU Analog
Control Lines Comparator
I/O Module1
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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AT90PWM1
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM (Store Program Memory) instruction that writes into the Application Flash
memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher is the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM1
has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
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5.4 Status Register
The Status Register contains information about the result of the most recently executed arith-
metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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AT90PWM1
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
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Figure 5-3. The X-, Y-, and Z-registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
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AT90PWM1
Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
clkCPU
Total Execution Time
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programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Pro-
gramming” on page 202.
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AT90PWM1
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
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6. Memories
This section describes the different memories in the AT90PWM1. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
AT90PWM1 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
Program Memory
0x0000
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AT90PWM1
6.2 SRAM Data Memory
Figure 2 shows how the AT90PWM1 SRAM Memory is organized.
The AT90PWM1 is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-
tions can be used.
The lower 768 data memory locations address both the Register File, the I/O memory, Extended
I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the
next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the
next 512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 512 bytes of internal data SRAM in the AT90PWM1 are all accessible through all these
addressing modes. The Register File is described in “General Purpose Register File” on page
11.
Data Memory
32 Registers 0x0000 - 0x001F
64 I/O Registers 0x0020 - 0x005F
160 Ext I/O Reg. 0x0060 - 0x00FF
0x0100
Internal SRAM
(512 x 8)
0x02FF
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Figure 3. On-chip Data SRAM Access Cycles
T1 T2 T3
clkCPU
Address Compute Address Address valid
Data
Write
WR
Data
Read
RD
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AT90PWM1
6.3.2 The EEPROM Address Registers – EEARH and EEARL
Bit 15 14 13 12 11 10 9 8
– – – – – – – EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 X
X X X X X X X X
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is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
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AT90PWM1
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical pro-
gramming time for EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-
bally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
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Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write (unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
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AT90PWM1
The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
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6.4 I/O Memory
The I/O space definition of the AT90PWM1 is shown in “Register Summary” on page 272.
All AT90PWM1 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using
LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM1 is a complex
microcontroller with more peripheral units than can be supported within the 64 location reserved
in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other
AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be
used on registers containing such status flags. The CBI and SBI instructions work with registers
0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
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AT90PWM1
GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 GPIOR3
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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7. System Clock
PLL
clkI/O AVR Clock clkCPU
Control Unit
clkFLASH
Clock
Multiplexer
Watchdog
Oscillator
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7.1.4 PLL Clock – clkPLL
The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz
clock is also derived for the CPU.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before starting
normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up
time. The number of WDT Oscillator cycles used for each time-out is shown in Table 4. The fre-
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quency of the Watchdog Oscillator is voltage dependent as shown in “Watchdog Oscillator
Frequency vs. VCC” on page 265.
C2
XTAL2
C1
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5.
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AT90PWM1
Table 5. Crystal Oscillator Operating Modes
Recommended Range for Capacitors C1 and
CKSEL3..1 Frequency Range(1) (MHz) C2 for Use with Crystals (pF)
101 0.9 - 3.0 12 - 22
110 3.0 - 8.0 12 - 22
111 8.0 -16.0 12 - 22
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
6.
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Reset Time-out. For more information on the pre-programmed calibration value, see the section
“Calibration Byte” on page 220.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 8 on page 30.
Table 8. Start-up times for the internal calibrated RC Oscillator clock selection
Start-up Time from Power- Additional Delay from
Power Conditions down and Power-save Reset (VCC = 5.0V) SUT1..0
(1)
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms (2) 10
Reserved 11
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.
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7.6 PLL
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency
clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of
PLL must be configurable by software. With a system clock of 8 MHz, the PLL output is 32Mhz
or 64Mhz.
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Figure 7-3. PCK Clocking System
OSCCAL PLLE PLLF
Lock PLOCK
Detector
DIVIDE
BY 4
CK SOURCE
XTAL1
OSCILLATORS
XTAL2
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AT90PWM1
7.8 External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure
7-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
NC XTAL2
External
Clock XTAL1
Signal
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 11.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
34 for details.
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7.10 System Clock Prescaler
The AT90PWM1 system clock can be divided by setting the Clock Prescale Register – CLKPR.
This feature can be used to decrease power consumption when the requirement for processing
power is low. This can be used with all clock source options, and it will affect the clock frequency
of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a
factor as shown in Table 12.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
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the selcted clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
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8. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See Table 13 for a summary. If an enabled interrupt occurs
while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in
addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the register file and SRAM are unaltered when the
device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and exe-
cutes from the Reset Vector.
Figure 7-1 on page 26 presents the different clock systems in the AT90PWM1, and their distribu-
tion. The figure is helpful in selecting an appropriate sleep mode.
36 AT90PWM1
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AT90PWM1
8.1 Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clkCPU
and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
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with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Oscillator
Active Clock Domains s Wake-up Sources
Source Enabled
SPM/EEPROM
Main Clock
OtherI/O
clkFLASH
INT3..0
Ready
clkCPU
clkADC
clkPLL
WDT
ADC
PSC
clkIO
Sleep
Mode
Idle X X X X X X X X X X
ADC
Noise X X X X(2) X X X X
Reduction
Power-
X(2) X X
down
Standby(1) X X(2) X
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. Only level interrupt.
Bit 7 6 5 4 3 2 0
PRPSC2 PRPSC1 PRPSC0 PRTIM1 PRTIM0 PRSPI PRADC PRR
Read/Write R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0
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AT90PWM1
Writing a logic one to this bit reduces the consumption of the PSC1 by stopping the clock to this
module. When waking up the PSC1 again, the PSC1 should be re initialized to ensure proper
operation.
• Bit 5 - PRPSC0: Power Reduction PSC0
Writing a logic one to this bit reduces the consumption of the PSC0 by stopping the clock to this
module. When waking up the PSC0 again, the PSC0 should be re initialized to ensure proper
operation.
• Bit 4 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit reduces the consumption of the Timer/Counter1 module. When the
Timer/Counter1 is enabled, operation will continue like before the setting of this bit.
• Bit 3 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit reduces the consumption of the Timer/Counter0 module. When the
Timer/Counter0 is enabled, operation will continue like before the setting of this bit.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit reduces the consumption of the Serial Peripheral Interface by stop-
ping the clock to this module. When waking up the SPI again, the SPI should be re initialized to
ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this
module. The ADC must be disabled before using this function. The analog comparator cannot
use the ADC input MUX when the clock of ADC is stopped.
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4378A–AVR–06/06
nificantly to the total current consumption. Refer to “Brown-out Detection” on page 44 for details
on how to configure the Brown-out Detector.
40 AT90PWM1
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AT90PWM1
9. System Control and Reset
9.0.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 9-1 shows the reset
logic. Table 9-1 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in “Clock Sources” on page 27.
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4378A–AVR–06/06
Figure 9-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
PORF
BORF
EXTRF
WDRF
Power-on Reset
Circuit
Brown-out
BODLEVEL [2..0] Reset Circuit
Pull-up Resistor
Spike
Filter
Watchdog
Oscillator
CKSEL[3:0]
SUT[1:0]
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AT90PWM1
Figure 9-2. MCU Start-up, RESET Tied to VCC
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
CC
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9.0.5 Brown-out Detection
AT90PWM1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level dur-
ing operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ =
VBOT + VHYST/2 and VBOT- = V BOT - VHYST/2.
Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the case, the device is tested down to VCC = V BOT during the production test. This guar-
antees that a Brown-Out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 010 for Low Operating Voltage and BODLEVEL = 101 for High Operating Volt-
age .
2. Values are guidelines only.
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AT90PWM1
Figure 9-5. Brown-out Reset During Operation
VCC VBOT+
VBOT-
RESET
TIME-OUT tTOUT
INTERNAL
RESET
CC
CK
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This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the reset flags.
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AT90PWM1
9.2 Watchdog Timer
AT90PWM1 has an Enhanced Watchdog Timer (WDT). The main features are:
• Clocked from separate On-chip Oscillator
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
128 KHz
OSCILLATOR
OSC/2K
OSC/8K
OSC/4K
WDP3
MCU RESET
WDIF
INTERRUPT
WDIE
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and
WDE. A logic one must be written to WDE regardless of the previous value of the WDE
bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
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The following code example shows one assembly and one C function for turning off the Watch-
dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note: 1. The example code assumes that the part specific header file is included.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not
set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this
situation, the application software should always clear the Watchdog System Reset Flag
(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
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AT90PWM1
The following code example shows one assembly and one C function for changing the time-out
value of the Watchdog Timer.
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed equence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note: 1. The example code assumes that the part specific header file is included.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change
in the WDP bits can result in a time-out when switching to a shorter time-out period;
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• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Note: 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 9-6 on page 51.
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AT90PWM1
.
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10. Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM1. For a
general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on
page 13.
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AT90PWM1
Table 15. Reset and Interrupt Vectors
Vector Program
No. Address Source Interrupt Definition
29 0x001C INT3 External Interrupt Request 3
30 0x001D
31 0x001E
32 0x001F SPM READY Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 202.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Interrupt Vector will then be the address in this table
added to the start address of the Boot Flash Section.
Table 16 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used, and regular program code can be placed at these locations. This is also
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
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0x010 rjmp TIM0_COMPA ; Timer0 Compare A Handler
0x011 rjmp TIM0_OVF ; Timer0 Overflow Handler
0x012 rjmp ADC ; ADC Conversion Complete Handler
0x013 rjmp EXT_INT1 ; IRQ1 Handler
0x014 rjmp SPI_STC ; SPI Transfer Complete Handler
0x018 rjmp EXT_INT2 ; IRQ2 Handler
0x019 rjmp WDT ; Watchdog Timer Handler
0x01A rjmp EE_RDY ; EEPROM Ready Handler
0x01B rjmp TIM0_COMPB ; Timer0 Compare B Handler
0x01C rjmp EXT_INT3 ; IRQ3 Handler
0x01F rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0x020RESET: ldi r16, high(RAMEND); Main program start
0x021 out SPH,r16 ; Set Stack Pointer to top of RAM
0x022 ldi r16, low(RAMEND)
0x023 out SPL,r16
0x024 sei ; Enable interrupts
0x025 <instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is:
Address Labels Code Comments
0x000 RESET: ldi r16,high(RAMEND); Main program start
0x001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x002 ldi r16,low(RAMEND)
0x003 out SPL,r16
0x004 sei ; Enable interrupts
0x005 <instr> xxx
;
.org 0xC01
0xC01 rjmp PSC2_CAPT ; PSC2 Capture event Handler
0xC02 rjmp PSC2_EC ; PSC2 End Cycle Handler
... ... ... ;
0xC1F rjmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM1
is:
Address Labels Code Comments
.org 0x001
0x001 rjmp PSC2_CAPT ; PSC2 Capture event Handler
0x002 rjmp PSC2_EC ; PSC2 End Cycle Handler
... ... ... ;
0x01F rjmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0xC00
0xC00 RESET: ldi r16,high(RAMEND); Main program start
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AT90PWM1
0xC01 out SPH,r16 ; Set Stack Pointer to top of RAM
0xC02 ldi r16,low(RAMEND)
0xC03 out SPL,r16
0xC04 sei ; Enable interrupts
0xC05 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is:
Address Labels Code Comments
;
.org 0xC00
0xC00 rjmp RESET ; Reset handler
0xC01 rjmp PSC2_CAPT ; PSC2 Capture event Handler
0xC02 rjmp PSC2_EC ; PSC2 End Cycle Handler
... ... ... ;
0xC1F rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0xC20 RESET: ldi r16,high(RAMEND); Main program start
0xC21 out SPH,r16 ; Set Stack Pointer to top of RAM
0xC22 ldi r16,low(RAMEND)
0xC23 out SPL,r16
0xC24 sei ; Enable interrupts
0xC25 <instr> xxx
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IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors
are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis-
abled while executing from the Boot Loader section. Refer to the section “Boot Loader Support –
Read-While-Write Self-Programming” on page 202 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See Code Example below.
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AT90PWM1
11. I/O-Ports
11.1 Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. All port pins have individually selectable pull-up resistors with a supply-voltage invari-
ant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure
11-1. Refer to “Electrical Characteristics(1)” on page 235 for a complete list of parameters.
Rpu
Pxn Logic
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in “Register Description for I/O-Ports”.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O”. Most port
pins are multiplexed with alternate functions for the peripheral features on the device. How each
alternate function interferes with the port pin is described in “Alternate Port Functions” on page
62. Refer to the individual module sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
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11.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
PUD
Q D
DDxn
Q CLR
WDx
RESET
RDx
DATA BUS
1
Pxn Q D
PORTxn 0
Q CLR
WPx
RESET
WRx
SLEEP RRx
SYNCHRONIZER
RPx
D Q D Q
PINxn
L Q Q
clk I/O
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
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AT90PWM1
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
SYNC LATCH
PINxn
t pd, max
t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min , a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 11-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
SYSTEM CLK
r16 0xFF
SYNC LATCH
PINxn
t pd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
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AT90PWM1
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17, (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB, r16
out DDRB, r17
; Insert nop for synchronization
nop
; Read port pins
in r16, PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
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11.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 11-5
shows how the port pin control signals from the simplified Figure 11-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
PUOExn
PUOVxn
1
0
PUD
DDOExn
DDOVxn
1
0 Q D
DDxn
Q CLR
WDx
PVOExn RESET
RDx
PVOVxn
DATA BUS
1 1
Pxn
0 Q D 0
PORTxn
SYNCHRONIZER
RPx
SET
D Q D Q
PINxn
L CLR Q CLR Q
clk I/O
DIxn
AIOxn
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 18 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 11-5 are not shown in the succeeding tables. The overriding signals are generated internally
in the modules having the alternate function.
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The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
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11.3.1 MCU Control Register – MCUCR
Bit 7 6 5 4 3 2 1 0
SPIPS – – PUD – – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• ADC6/INT2 – Bit 5
ADC6, Analog to Digital Converter, input channel 6.
INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU.
• APM0+ – Bit 4
AMP0+, Analog Differential Amplifier 0 Positive Input Channel.
• AMP0- – Bit 3
AMP0-, Analog Differential Amplifier 0 Negative Input Channel.
• ADC5/INT1 – Bit 2
ADC5, Analog to Digital Converter, input channel 5.
INT1, External Interrupt source 1. This pin can serve as an external interrupt source to the MCU.
• MOSI/PSCOUT21 – Bit 1
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1 When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 and PUD bits.
PSCOUT21: Output 1 of PSC 2.
• MISO/PSC20 – Bit 0
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB0 and PUD bits.
PSCOUT20: Output 0 of PSC 2.
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Table 20 and Table 21 relates the alternate functions of Port B to the overriding signals shown in
Figure 11-5 on page 62.
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11.3.3 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 22.
• ACMP0 – Bit 7
ACMP0, Analog Comparator 0 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Ana-
log Comparator.
• ADC3/ACMPM/INT0 – Bit 6
ADC3, Analog to Digital Converter, input channel 3.
ACMPM, Analog Comparators Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Ana-
log Comparator.
INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU.
• ADC2/ACMP2 – Bit 5
ADC2, Analog to Digital Converter, input channel 2.
ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Ana-
log Comparator.
• ADC1/ICP1/SCK_A – Bit 4
ADC1, Analog to Digital Converter, input channel 1.
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ICP1 – Input Capture Pin1: This pin can act as an input capture pin for Timer/Counter1.
SCK_A: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as
a slave, this pin is configured as an input regardless of the setting of DDD4. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDD4. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTD4 bit.
• OC0A/SS/MOSI_A, Bit 3
OC0A, Output Compare Match A output: This pin can serve as an external output for the
Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDD3 set “one”)
to serve this function. The OC0A pin is also the output pin for the PWM mode
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD3. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD3.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD3 bit.
MOSI_A: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as
a slave, this pin is configured as an input regardless of the setting of DDD3 When the SPI is
enabled as a master, the data direction of this pin is controlled by DDD3. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTD3 bit.
• PSCIN2/OC1A/MISO_A, Bit 2
PCSIN2, PSC 2 Digital Input.
OC1A, Output Compare Match A output: This pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set “one”)
to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as
a master, this pin is configured as an input regardless of the setting of DDD2. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTD2 bit.
• PSCIN0/CLKO – Bit 1
PCSIN0, PSC 0 Digital Input.
CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided
system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTD1 and
DDD1 settings. It will also be output during reset.
• PSCOUT00/SS_A – Bit 0
PSCOUT00: Output 0 of PSC 0.
SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit.
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Table 23 and Table 24 relates the alternate functions of Port D to the overriding signals shown in
Figure 11-5 on page 62.
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Table 24. Overriding Signals for Alternate Functions in PD3..PD0
PD3/OC0A/ PD2/PSCIN2/ PD1/PSCIN0/ PD0/PSCOUT00/
Signal Name SS/MOSI_A OC1A/MISO_A CLKO SS_A
SPE • SPE •
PUOE – 0
MSTR • SPIPS MSTR • SPIPS
SPE • MSTR •
PUOV – 0 PD0 • PUD
SPIPS • PD3 • PUD
SPE • PSCen00 + SPE •
DDOE – 0
MSTR • SPIPS MSTR • SPIPS
DDOV 0 0 PSCen00
OC0en + SPE •
PVOE – 0 PSCen00 + UMSEL
MSTR • SPIPS
TXD + TXEN •
(OC0en • OC0 +
PVOV – 0 –
OC0en • SPIPS •
MOSI)
DIEOE 0 0 0 0
DIEOV 0 0 0 0
SS
DI SS_A
MOSI_Ain
AIO
• XTAL1/OC0B – Bit 1
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XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC
Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
OC0B, Output Compare Match B output: This pin can serve as an external output for the
Timer/Counter0 Output Compare B. The pin has to be configured as an output (DDE1 set “one”)
to serve this function. This pin is also the output pin for the PWM mode timer function.
• RESET/OCD – Bit 0
RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O
pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.
When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the
pin can not be used as an I/O pin.
If PE0 is used as a reset pin, DDE0, PORTE0 and PINE0 will all read 0.
Table 26 relates the alternate functions of Port E to the overriding signals shown in Figure 11-5
on page 62.
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Initial Value 0 0 0 0 0 0 0 0
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12. External Interrupts
The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts
will trigger even if the INT3:0 pins are configured as outputs. This feature provides a way of gen-
erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or
a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-
isters – EICRA (INT3:0). When the external interrupt is enabled and is configured as level
triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or
rising edge interrupts on INT3:0 requires the presence of an I/O clock, described in “Clock Sys-
tems and their Distribution” on page 26. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in the “Electrical Characteristics(1)” on page 235. The MCU
will wake up if the input has the required level during this sampling or if it is held until the end of
the start-up time. The start-up time is defined by the SUT fuses as described in “System Clock”
on page 26. If the level is sampled twice by the Watchdog Oscillator clock but disappears before
the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
required level must be held long enough for the MCU to complete the wake up to trigger the level
interrupt.
Bit 7 6 5 4 3 2 1 0
ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits 7..0 – ISC31, ISC30 – ISC01, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 27. Edges on INT3..INT0 are registered asynchro-
nously.The value on the INT3:0 pins are sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency
can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as
long as the pin is held low.
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Note: 1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Bit 7 6 5 4 3 2 1 0
- - - - INT3 INT2 INT1 IINT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - - INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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13. Timer/Counter0 and Timer/Counter1 Prescalers
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE
clk I/O
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
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Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
PSRSYNC
T0
Synchronization
T1
Synchronization
clkT1 clkT0
Note: 1. The synchronization logic on the input pins (Tn/T0) is shown in Figure 13-1.
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Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PB6). The selection
is made thanks to ICPSEL1 bit as described in Table .
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14. 8-bit Timer/Counter0 with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation. The main features are:
14.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual
placement of I/O pins, refer to “Pin Descriptions” on page 6. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the “8-bit Timer/Counter Register Description” on page 88.
The PRTIM0 bit in “Power Reduction Register” on page 38 must be written to zero to enable
Timer/Counter0 module.
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
DATA BUS
Timer/Counter
TCNTn
= =0 OCnA
(Int.Req.)
Waveform
= Generation
OCnA
OCRnx OCnB
Fixed (Int.Req.)
TOP
Values
= Waveform
OCnB
Generation
OCRnx
TCCRnA TCCRnB
14.1.1 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
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The definitions in Table 29 are also used extensively throughout the document.
Table 29. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
14.1.2 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Using the Output Compare Unit” on page 105. for details. The compare match
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Out-
put Compare interrupt request.
Clock Select
count Edge
Tn
clear clkTn Detector
TCNTn Control Logic
direction
( From Prescaler )
bottom top
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count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk T0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see “Modes of
Operation” on page 83.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
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Figure 14-3. Output Compare Unit, Block Diagram
DATA BUS
OCRnx TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator OCnx
FOCn
WGMn1:0 COMnx1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR0x directly.
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The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-
pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
COMnx1
COMnx0 Waveform
D Q
FOCn Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter Register Description” on page 88.
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non-PWM modes refer to Table 30 on page 89. For fast PWM mode, refer to Table 31 on page
89, and for phase correct PWM refer to Table 32 on page 89.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
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Figure 14-5. CTC Mode, Timing Diagram
TCNTn
OCn
(COMnx1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
fclk_I/O
fOCnx = -------------------------------------------------
-
2 ⋅ N ⋅ ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
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inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare
matches between OCR0x and TCNT0.
TCNTn
OCn (COMnx1:0 = 2)
OCn (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available
for the OC0B pin (see Table 34 on page 90). The actual OC0x value will only be visible on the
port pin if the data direction for the port pin is set as output. The PWM waveform is generated by
setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and
clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes
from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = -----------------
-
N ⋅ 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform
generated will have a maximum frequency of fOC0 = fclk_I/O /2 when OCR0A is set to zero. This
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-
put Compare unit is enabled in the fast PWM mode.
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14.6.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-
inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match
between TCNT0 and OCR0x while upcounting, and set on the compare match while downcount-
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmet-
ric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x
and TCNT0.
OCRnx Update
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see Table 35 on page 90). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and
TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare
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match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
fclk_I/O
fOCnxPCPWM = -----------------
-
N ⋅ 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 14-7 OCnx has a transition from high to low even though
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCRnx changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-
counting Compare Match.
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
clkI/O
clkTn
(clkI/O /1)
TOVn
Figure 14-9 shows the same timing data, but with the prescaler enabled.
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O /8)
clkI/O
clkTn
(clkI/O /8)
TOVn
Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCFnx
Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC)
OCRnx TOP
OCFnx
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• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 30 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 31 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 32. Compare Output Mode, Phase Correct PWM Mode (1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
0 1
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match when up-counting. Set OC0A on
1 0
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
1 1
Compare Match when down-counting.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 110 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
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These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 33 shows the COM0B1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 34 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Table 35. Compare Output Mode, Phase Correct PWM Mode (1)
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
1 0
Compare Match when down-counting.
Set OC0B on Compare Match when up-counting. Clear OC0B on
1 1
Compare Match when down-counting.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 86 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM1 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
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Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 36. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 83).
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strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM1 and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “Timer/Counter Control Register A – TCCR0A” on page 88.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
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14.8.5 Output Compare Register B – OCR0B
Bit 7 6 5 4 3 2 1 0
OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
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The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 36, “Waveform
Generation Mode Bit Description” on page 91.
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15. 16-bit Timer/Counter1 with PWM
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
15.1 Overview
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1. For the actual
placement of I/O pins, refer to “Pin Descriptions” on page 3. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the “16-bit Timer/Counter Register Description” on page 115.
The PRTIM1 bit in “Power Reduction Register” on page 38 must be written to zero to enable
Timer/Counter1 module.
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Figure 15-1. 16-bit Timer/Counter Block Diagram(1)
Count TOVn
Clear (Int.Req.)
Control Logic
Direction clkTn Clock Select
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)
Waveform
= Generation
OCnA
OCRnA
Fixed OCnB
TOP (Int.Req.)
DATA BUS
Values
Waveform
= Generation
OCnB
OCRnB
TCCRnA TCCRnB
Note: 1. Refer toTable on page 3 for Timer/Counter1 pin placement and description.
15.1.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit
registers. These procedures are described in the section “Accessing 16-bit Registers” on page
97. The Timer/Counter Control Registers (TCCRnx) are 8-bit registers and have no CPU access
restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter
value at all time. The result of the compare can be used by the Waveform Generator to generate
a PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare
Units” on page 103. The compare match event will also set the Compare Match Flag (OCFnx)
which can be used to generate an Output Compare interrupt request.
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital
filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using
OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used
as an alternative, freeing the OCRnA to be used as PWM output.
15.1.2 Definitions
The following definitions are used extensively throughout the section:
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,
TOP
or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is
dependent of the mode of operation.
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Assembly Code Examples(1)
...
; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNTnH,r17
out TCNTnL,r16
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
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The following code examples show how to do an atomic read of the TCNTn Register contents.
Reading any of the OCRnx or ICRn Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_ReadTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNTn( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNTn into i */
i = TCNTn;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNTn Register contents.
Writing any of the OCRnx or ICRn Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNTn( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNTn to i */
TCNTn = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example requires that the r17:r16 register pair contains the value to be writ-
ten to TCNTn.
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15.4 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2 shows a block diagram of the counter and its surroundings.
TEMP (8-bit)
Clock Select
Count Edge
Tn
TCNTnH (8-bit) TCNTnL (8-bit) Clear clkTn Detector
Control Logic
Direction
TCNTn (16-bit Counter)
( From Prescaler )
TOP BOTTOM
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15.5 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-
nal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
TEMP (8-bit)
ICPnA
Noise Edge
ICFn (Int.Req.)
Canceler Detector
ICPnB
When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at
the same system clock as the TCNTn value is copied into ICRn Register. If enabled (ICIEn = 1),
the Input Capture Flag generates an Input Capture interrupt. The ICFn Flag is automatically
cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software
by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low
byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will
access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location
before the low byte is written to ICRnL.
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For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 97.
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ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See “16-bit Timer/Counter1 with PWM” on page 95.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 15-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (x). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
TEMP (8-bit)
OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
Waveform Generator OCnx
BOTTOM
WGMn3:0 COMnx1:0
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-
put glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-
abled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg-
ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
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updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 97.
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Figure 15-5. Compare Match Output Unit, Schematic
COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 38, Table 39 and Table 40 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the out-
put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter Register Description” on page 115.
The COMnx1:0 bits have no effect on the Input Capture unit.
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put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare
match (See “Compare Match Output Unit” on page 105.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 114.
TCNTn
OCnA
(COMnA1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the
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interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-
ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buff-
ering feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its max-
imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-
quency of fOCnA = f clk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is
defined by the following equation:
f
clk_I/O
f
OCnA = --------------------------------------------------
2 ⋅ N ⋅ ( 1 + OCRnA )
-
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =
14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn
slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will
be set when a compare match occurs.
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AT90PWM1
Figure 15-7. Fast PWM Mode, Timing Diagram
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7 8
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition
the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA
or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-
dler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP
value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICRn value written is lower than the current value of TCNTn. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location
to be written anytime. When the OCRnA I/O location is written the value written will be put into
the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done
at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COMnx1:0 to three (see Table on page 116). The actual OCnx
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at
the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
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The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
fOCnxPWM = ----------------------------------
-
N ⋅ ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOCnA = fclk_I/O /2 when OCRnA is set to zero (0x0000). This feature is
similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.
log ( TOP + 1 )
R PCPWM = ----------------------------------
-
log ( 2 )
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-8. The figure
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter-
rupt Flag will be set when a compare match occurs.
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Figure 15-8. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in Figure 15-8 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg-
ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx1:0 to three (See Table on page 116). The
actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis-
ter at the compare match between OCRnx and TCNTn when the counter increments, and
clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when
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the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
fclk_I/O
fOCnxPCPWM = ---------------------------
-
2 ⋅ N ⋅ TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
log ( TOP + 1 )
R PFCPW M = ----------------------------------
-
log ( 2 )
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNTn value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 15-9. The figure shows phase and frequency correct
PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing dia-
gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-
inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-
sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
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Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx
Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn
is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP.
The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri-
cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on
page 116). The actual OCnx value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)
the OCnx Register at the compare match between OCRnx and TCNTn when the counter incre-
ments, and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
fclk_I/O
fOCnxPFCPWM = ---------------------------
-
2 ⋅ N ⋅ TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
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The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
clkI/O
clkTn
(clkI/O /1)
OCFnx
Figure 15-11 shows the same timing data, but with the prescaler enabled.
Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCFnx
Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
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Figure 15-12. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)
TCNTn
TOP - 1 TOP TOP - 1 TOP - 2
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
Figure 15-13 shows the same timing data, but with the prescaler enabled.
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)
TOVn (FPWM)
and ICF n (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
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I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting. Table 38 shows the COMnx1:0 bit functionality when the
WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 39 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM
mode.
Table 40. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM (1)
COMnA1/COMnB1 COMnA0/COMnB0 Description
0 0 Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
0 1
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OCnA/OCnB on Compare Match when up-
1 0 counting. Set OCnA/OCnB on Compare Match when
downcounting.
Set OCnA/OCnB on Compare Match when up-
1 1 counting. Clear OCnA/OCnB on Compare Match
when downcounting.
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Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See
“Phase Correct PWM Mode” on page 110. for more details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 41. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “16-bit Timer/Counter1 with PWM” on page 95.).
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This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
15-10 and Figure 15-11.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
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FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the
COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 97.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 97.
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15.10.7 Input Capture Register 1 – ICR1H and ICR1L
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 97.
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15.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1
Bit 7 6 5 4 3 2 1 0
– – ICF1 – – OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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16. Power Stage Controller – (PSC0, PSC2)
The Power Stage Controller is a high performance waveform controller.
16.1 Features
• PWM waveform generation function (2 complementary programmable outputs)
• Dead time control
• Standard mode up to 12 bit resolution
• Frequency Resolution Enhancement Mode (12 + 4 bits)
• Frequency up to 64 Mhz
• Conditional Waveform on External Events (Zero Crossing, Current Sensing ...)
• All on chip PSC synchronization
• ADC synchronization
• Overload protection function
• Abnormality protection function, emergency input to force all outputs to high impedance or in
inactive state (fuse configurable)
• Center aligned and edge aligned modes synchronization
• Fast emergency stop by hardware
16.2 Overview
Many register and bit references in this section are written in general form.
• A lower case “n” replaces the PSC number, in this case 0, 1 or 2. However, when using the
register or bit defines in a program, the precise form must be used, i.e., PSOC1 for
accessing PSC 0 Synchro and Output Configuration register and so on.
• A lower case “x” replaces the PSC part , in this case A or B. However, when using the
register or bit defines in a program, the precise form must be used, i.e., PFRCnA for
accessing PSC n Fault/Retrigger n A Control register and so on.
The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has
two outputs on PSC0 and PSC1 and four outputs on PSC2.
These outputs can be used in various ways:
• “Two Ouputs” to drive a half bridge (lighting, DC motor ...)
• “One Output” to drive single power transistor (DC/DC converter, PFC, DC motor ...)
• “Four Outputs” in the case of PSC2 to drive a full bridge (lighting, DC motor ...)
Each PSC has two inputs the purpose of which is to provide means to act directly on the gener-
ated waveforms:
• Current sensing regulation
• Zero crossing retriggering
• Demagnetization retriggering
• Fault input
The PSC can be chained and synchronized to provide a configuration to drive three half bridges.
Thanks to this feature it is possible to generate a three phase waveforms for applications such
as Asynchronous or BLDC motor drive.
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16.3 PSC Description
PSC Counter
Waveform
= Generator B
PSCOUTn1
OCRnSB PISELnB
Part B
PSCn Input A
= PSC Input
Module A PSCINn
OCRnRA PISELnA
Waveform PSCOUTn0
= Generator A
OCRnSA
Part A
PICRn
Note: n = 0, 1
The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to
count up and count down from and to values stored in registers according to the selected run-
ning mode.
The PSC is seen as two symetrical entities. One part named part A which generates the output
PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output.
Each part A or B has its own PSC Input Module to manage selected input.
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16.3.1 PSC2 Distinctive Feature
PSC Counter
PSCOUTn3
POS23
Waveform
= Generator B
PSCOUTn1
PSCn Input A
= PSC Input
Module A PSCINn
OCRnRA PISELnA
PSCOUTn2
POS22
Waveform PSCOUTn0
= Generator A
OCRnSA
Part B
PICRn
Note: n=2
PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector
PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23
can duplicate PSCOUT20 or PSCOUT21.
The Output Matrix is a kind of 2*2 look up table which gives the possibility to program the output
values according to a PSC sequence (See “Output Matrix” on page 150.)
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16.3.2 Output Polarity
The polarity “active high” or “active low” of the PSC outputs is programmable. All the timing dia-
grams in the following examples are given in the “active high” polarity.
CLK I/O
SYnIn
StopOut
12
OCRnRB[11:0] PSCOUTn0
12
OCRnSB[11:0] PSCOUTn1
12 (1)
OCRnRA[11:0] PSCOUTn2
12 (1)
OCRnSA[11:0] PSCOUTn3
4
OCRnRB[15:12]
(Flank Width
Modulation)
12
PICRn[11:0] PSCINn
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16.4.1 Input Description
Table 43. Internal Inputs
Type
Name Description
Width
OCRnRB[1 Register
Compare Value which Reset Signal on Part B (PSCOUTn1)
1:0] 12 bits
OCRnSB[1 Register
Compare Value which Set Signal on Part B (PSCOUTn1)
1:0] 12 bits
OCRnRA[1 Register
Compare Value which Reset Signal on Part A (PSCOUTn0)
1:0] 12 bits
OCRnSA[1 Register
Compare Value which Set Signal on Part A (PSCOUTn0)
1:0] 12 bits
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Table 46. Internal Outputs
Type
Name Description
Width
SYnOut Synchronization Output(1) Signal
PICRn PSC n Input Capture Register Register
[11:0] Counter value at retriggering event 12 bits
PSC Interrupt Request : three souces, overflow, fault, and input
IRQPSCn Signal
capture
PSCnASY ADC Synchronization (+ Amplifier Syncho. )(2) Signal
StopOut Stop Output (for synchronized mode)
Sub-Cycle A Sub-Cycle B
4 Ramp Mode
2 Ramp Mode
Ramp A Ramp B
1 Ramp Mode
UPDATE
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Figure 16-5. Cycle Presentation in Centered Mode
PSC Cycle
Centered Mode
UPDATE
Ramps illustrate the output of the PSC counter included in the waveform generators. Centered
Mode is like a one ramp mode which count down up and down.
Notice that the update of a new set of values is done regardless of ramp Mode at the top of the
last ramp.
Figure 16-6. PSCn0 & PSCn1 Basic Waveforms in Four Ramp mode
OCRnRA
PSC Counter OCRnRB
OCRnSA OCRnSB
0 0
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 Dead-Time 1
PSC Cycle
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PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and
Dead-Time 1 values with :
On-Time 0 = OCRnRAH/L * 1/Fclkpsc
On-Time 1 = OCRnRBH/L * 1/Fclkpsc
Dead-Time 0 = (OCRnSAH/L + 2) * 1/Fclkpsc
Dead-Time 1 = (OCRnSBH/L + 2) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 2 * 1/Fclkpsc
Figure 16-7. PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode
OCRnRA
OCRnRB
PSC Counter
OCRnSA OCRnSB
0 0
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 Dead-Time 1
PSC Cycle
PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and
Dead-Time 1 values with :
On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc
On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc
Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc
Dead-Time 1 = (OCRnSBH/L + 1) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc
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Figure 16-8. PSCn0 & PSCn1 Basic Waveforms in One Ramp mode
OCRnRB
OCRnSB
OCRnRA
PSC Counter
OCRnSA
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 Dead-Time 1
PSC Cycle
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Figure 16-9. PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode
OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful
to adjust ADC synchronization (See “Analog Synchronization” on page 151.).
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16.5.3 Fifty Percent Waveform Configuration
When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the
PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the
OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not
necessary to program OCRnSAH/L and OCRnRAH/L registers.
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
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fractional divider number. The resulting output frequency is the average of the frequencies in the
frame. The fractional divider (d) is given by OCRnRB[15:12].
The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0)
and PSCOUTn1 On Time + DeadTime (OT1+DT1) values. These values are 12 bits numbers.
The frequency adjustment can only be done in steps like the dedicated counters. The step width
is defined as the frequency difference between two neighboring PSC frequencies:
f
PLL f PLL 1
Δf = f 1 – f 2 = ---------- – ------------ = f PSC × --------------------
k k+1 k(k + 1)
with k is the number of CLKPSC period in a PSC cycle and is given by the following formula:
f PSC
n = ----------
f OP
Exemple, in normal mode, with maximum operating frequency 160 kHz and fPLL = 64 Mhz, k
equals 400. The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.
In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu-
tive cycles.
16 – d d
f AVERAGE = --------------- × f b 1 + ------ × f b 2
16 16
16 – d f PLL d f PLL
fAVERAGE = --------------- × ---------
- + ------ × -----------
-
16 n 16 n + 1
Then the frequency resolution is divided by 16. In the example above, the resolution equals 25
Hz.
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16.7.1 Frequency distribution
The frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame.
These two frequencies are fb1 and fb2 where fb1 is the nearest base frequency above the wanted
frequency and fb2 is the nearest base frequency below the wanted frequency. The number of fb1
in the frame is (d-16) and the number of fb2 is d. The f b1 and fb2 frequencies are evenly distrib-
uted in the frame according to a predefined pattern. This pattern can be as given in the following
table or by any other implementation which give an equivallent evenly distribution.
fb1 fb2
fOP
d: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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16.7.2 Modes of Operation
1 f
CLK_PSCn
f - = ----------------------------------------------------------------------
PSCn = -----------------------------
PSCnCycle ( OT 0 + OT 1 + DT 0 + DT 1 )
= = 1
PSCOUTn0
PSCOUTn1
Period T1 T2
The supplementary step in counting to generate fb2 is added on the PSCn0 signal while needed
in the frame according to the fractional divider. SeeTable 47, “Distribution of fb2 in the modu-
lated frame,” on page 134.
The waveform frequency is defined by the following equations:
1 f
f 1 PSCn CLK_PSCn
= ------ = ----------------------------------------------------------------------
T 1 ( OT 0 + OT 1 + DT 0 + DT 1 )
1 f
f 2 PSCn CLK_PSCn
= ------ = --------------------------------------------------------------------------------
T 2 ( OT 0 + OT 1 + DT 0 + DT 1 + 1 )
d 16 – d
f
AVERAGE = -----
16
- × f 1 PSCn + --------------- × f 2 PSCn
16
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16.8 PSC Inputs
Each part A or B of PSC has its own system to take into account one PSC input. According to
PSC n Input A/B Control Register (see description 16.25.13page 160), PSCnIN0/1 input can act
has a Retrigger or Fault input.
This system A or B is also configured by this PSC n Input A/B Control Register (PFRCnA/B).
PSCINn 0
Digital
Filter 1
Analog
Comparator 1
n Output
PFLTEnA
CLK PSC (PFLTEnB)
PISELnA
(PISELnB)
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Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A
(falling edge)
PSCn Input A
(rising edge)
Dead-Time 0 Dead-Time 1
Note: This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
Dead-Time 0 Dead-Time 1
Note: This exemple is given in “Input Mode 1” in “2 or 4 ramp mode” See Figure 16-20. for details.
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Figure 16-17. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input B
(falling edge)
PSCn Input B
(rising edge)
Note: This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details.
PSCOUTn0
PSCOUTn1
PSCn Input B
(high level)
PSCn Input B
(low level)
Note: This exemple is given in “Input Mode 1” in “2 or 4 ramp mode” See Figure 16-20. for details.
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Figure 16-19. Burst Generation
OFF BURST
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
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If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active
level is high (level modes) and vice versa for unset/falling/low
- In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-
Time0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B).
- In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp.
Notice: All following examples are given with rising edge or high level active inputs.
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16.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and
OT1.
When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state
and then jumps and executes DT1 plus OT1.
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state
and then jumps and executes DT0 plus OT0.
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16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus
OT1 and then waits for PSC Input A inactive state.
Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-
pletely executed.
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0
and then waits for PSC Input B inactive state.
Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-
pletely executed.
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16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT1 OT1 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and
OT1.
When PSC Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1
plus DT0 while PSC Input A is in active state.
Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-
pletely executed.
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and
OT0.
When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0
plus DT1 while PSC Input B is in active state.
Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-
pletely executed.
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Figure 16-26. PSC behaviour versus PSCn Input A or Input B in Mode 4
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Figure 16-27. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
DT0
DT1
DT1
OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0
or on On-Time1/Dead-Time1.
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16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0
or on On-Time1/Dead-Time1.
16.15 PSC Input Mode 7: Halt PSC and Wait for Software Action
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Note: 1. Software action is the setting of the PRUNn bit in PCTLn register.
Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0
or on On-Time1/Dead-Time1.
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16.16 PSC Input Mode 8: Edge Retrigger PSC
PSCOUTn0
PSCOUTn1
PSCn Input A
The output frequency is modulated by the occurence of significative edge of retriggering input.
PSCOUTn0
PSCOUTn1
PSCn Input B
or
PSCn Input B
The output frequency is modulated by the occurence of significative edge of retriggering input.
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
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16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
PSCOUTn0
PSCOUTn1
PSCn Input A
The output frequency is not modified by the occurence of significative edge of retriggering input.
Only the output is disactivated when significative edge on retriggering input occurs.
Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrig-
ger/Fault input is actve. Only the significative edge of Retrigger/Fault input is taken into account.
PSCOUTn0
PSCOUTn1
PSCn Input B
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
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16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output
PSCOUTn0
PSCOUTn1
PSCn Input A
The output frequency is not modified by the occurence of significative edge of retriggering input.
PSCOUTn0
PSCOUTn1
PSCn Input B
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16.18.1 Available Input Mode according to Running Mode
Some Input Modes are not consistent with some Running Modes. So the table below gives the
input modes which are valid according to running modes..
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16.19 PSC2 Outputs
PSCOUT2m takes the value given in Table 50. during all corresponding ramp. Thanks to the
Output Matrix it is possible to generate all kind of PSCOUT20/PSCOUT21 combination.
When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.
Waveform PSCOUT20
Generator A
0
PSCOUT22
1
POS22
Output
Matrix POS23
1
PSCOUT23
0
Waveform PSCOUT21
Generator B
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16.20 Analog Synchronization
PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for
measurements.
This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-
tion of the ADC. It this case, it’s minimum value is 1.
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If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1.
PRUNn and PARUNn bits are located in PCTLn register. See “PSC 0 Control Register – PCTL0”
on page 157. See “PSC 1 Control Register – PCTL1” on page 159. See “PSC 2 Control Register
– PCTL2” on page 159.
Note : Do not set the PARUNn bits on the three PSC at the same time.
Thanks to this feature, we can for example configure two PSC in slave mode (PARUNn = 1 /
PRUNn = 0) and one PSC in master mode (PARUNm = 0 / PRUNm = 0). This PSC master can
start all PSC at the same moment ( PRUNm = 1).
PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source.
PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the
clock.
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16.24 Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM1.
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16.25.1 PSC 0 Synchro and Output Configuration – PSOC0
Bit 7 6 5 4 3 2 1 0
- - PSYNC01 PSYNC00 - POEN0B - POEN0A PSOC0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 2 – POENnB: PSC n OUT Part B Output Enable
When this bit is clear, I/O pin affected to PSCOUTn1 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUTn1 is connected to the PSC waveform generator
B output and is set and clear according to the PSC operation.
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16.25.5 Output Compare SB Register – OCRnSBH and OCRnSBL
Bit 7 6 5 4 3 2 1 0
– – – – OCRnSB[11:8] OCRnSBH
OCRnSB[7:0] OCRnSBL
Read/Write W W W W W W W W
Initial Value 0 0 0 0 0 0 0 0
The PSC n Configuration Register is used to configure the running mode of the PSC.
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• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and
the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The
update of the PSC internal registers will be done at the end of the PSC cycle if the Output Com-
pare Register RB has been the last written.
When set, this bit prevails over LOCK (bit 5)
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• Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified
by this factor.
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16.25.11 PSC 1 Control Register – PCTL1
Bit 2
PARUN1
Read/Write R/W
Initial Value 0
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• Bit 1 – PCCYC2 : PSC 2 Complete Cycle
When this bit is set, the PSC 2 completes the entire waveform cycle before halt operation
requested by clearing PRUN2. This bit is not relevant in slave mode (PARUN2 = 1).
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
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• Bit 3:0 – PRFMnx3:0: PSC n Fault Mode
These four bits define the mode of operation of the Fault or Retrigger functions.
(see PSC Functional Specification for more explanations)
PRFMnx3:0 Description
0000b No action, PSC Input is ignored
0001b PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
0010b PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
0011b PSC Input Mode 3: Stop signal, Execute Opposite while Fault active
0100b PSC Input Mode 4: Deactivate outputs without changing timing.
0101b PSC Input Mode 5: Stop signal and Insert Dead-Time
0110b PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
0111b PSC Input Mode 7: Halt PSC and Wait for Software Action
1000b PSC Input Mode 8: Edge Retrigger PSC
1001b PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
1010b Reserved (do not use)
1011b
1100b
1101b
PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate
1110b
Output
1111b Reserved (do not use)
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• Bit 7 – PCSTn : PSC Capture Software Trig bit
Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means
that the capture operation was triggered by PCSTn setting otherwise it means that the capture
operation was triggered by a PSC input.
The Input Capture is updated with the PSC counter value each time an event occurs on the
enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is
enabled (bit PCAEnx in PFRCnx register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or
12-bit registers.
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16.26.2 PSC0 Interrupt Mask Register – PIM0
Bit 7 6 5 4 3 2 1 0
- - PSEIE0 PEVE0B PEVE0A - - PEOPE0 PIM0
Read/Write R R R/W R/W R/W R R R/W
Initial Value 0 0 0 0 0 0 0 0
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This feature is useful to detect that a PSC output doesn’t change due to a freezen external input
signal.
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17. Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
AT90PWM1 and peripheral devices or between several AVR devices.
The AT90PWM1 SPI includes the following features:
17.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
MISO
MISO
_A
clk IO
MOSI
MOSI
_A
DIVIDER
/2/4/8/16/32/64/128
SCK
SCK
_A
SS
SPI2X
SS_A
SPI2X
Note: 1. Refer to Figure 3-1 on page 2, and Table 19 on page 64 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The sys-
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective shift Registers, and the Master generates
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the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of transmission
flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested. The Slave may continue to place new data to be sent into SPDR before reading the
incoming data. The last incoming byte will be kept in the Buffer Register for later use.
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fclkio/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 60. For more details on automatic port overrides, refer to “Alternate Port
Functions” on page 62.
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Table 60. SPI Pin Overrides(1)
Pin Direction, Master SPI Direction, Slave SPI
MISO Input User Defined
SCK User Defined Input
SS User Defined Input
Note: 1. See “Alternate Functions of Port B” on page 64 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the
SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits
for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI
with DDRB.
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Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
Note: 1. The example code assumes that the part specific header file is included.
The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
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SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return data register */
return SPDR;
}
Note: 1. The example code assumes that the part specific header file is included.
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17.2 SS Pin Functionality
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– When the SPIPS bit is written to one,the SPI signals are directed on pins
MISO,MOSI, SCK and SS.
Note that programming port are always located on alternate SPI port.
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These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clkIO frequency fclkio is shown in
the following table:
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17.2.6 SPI Data Register – SPDR
Bit 7 6 5 4 3 2 1 0
SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X Undefined
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
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Figure 17-4. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
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18. Analog Comparator
The Analog Comparator compares the input values on the positive pin ACMPx and negative pin
ACMPM.
18.1 Overview
The AT90PWM1 features three fast analog comparators.
Each comparator has a dedicated input on the positive input, and the negative input can be con-
figured as:
• a steady value among the 4 internal reference levels defined by the Vref selected thanks to
the REFS1:0 bits in ADMUX register.
• a value generated from the internal DAC
• an external analog input ACMPM.
When the voltage on the positive ACMPn pin is higher than the voltage selected by the ACnM
multiplexer on the negative input, the Analog Comparator output, ACnO, is set.
The comparator is a clocked comparator. A new comparison is done on the falling edge of
CLKI/O or CLKI/O/2 ( Depending on ACCKDIV fit of ACSR register, See “Analog Comparator Sta-
tus Register – ACSR” on page 178.).
Each comparator can trigger a separate interrupt, exclusive to the Analog Comparator. In addi-
tion, the user can select Interrupt triggering on comparator output rise, fall or toggle.
The interrupt flags can also be used to synchronize ADC or DAC conversions.
Moreover, the comparator’s output of the comparator 1 can be set to trigger the Timer/Counter1
Input Capture function.
A block diagram of the three comparators and their surrounding logic is shown in Figure 18-1.
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Figure 18-1. Analog Comparator Block Diagram(1)(2)
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These 2 bits determine the sensitivity of the interrupt trigger.
The different setting are shown in Table 65.
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These 2 bits determine the sensitivity of the interrupt trigger.
The different setting are shown in Table 65.
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This bit is cleared by hardware when the corresponding interrupt vector is executed in case the
AC0IE in AC0CON register is set. Anyway, this bit is cleared by writing a logical one on it.
This bit can also be used to synchronize ADC or DAC conversions.
• Bit 2– AC2O: Analog Comparator 2 Output Bit
AC2O bit is directly the output of the Analog comparator 2.
Set when the output of the comparator is high.
Cleared when the output comparator is low.
• Bit 0– AC0O: Analog Comparator 0 Output Bit
AC0O bit is directly the output of the Analog comparator 0.
Set when the output of the comparator is high.
Cleared when the output comparator is low.
• Bit 3:2 – ACMPM and ACMP2D: ACMPM and ACMP2 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Analog pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to one of these pins and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
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19. Analog to Digital Converter - ADC
19.1 Features
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ± 2 LSB Absolute Accuracy
• 8- 250 µs Conversion Time
• Up to 120 kSPS at Maximum Resolution
• 11 Multiplexed Single Ended Input Channels
• Two Differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40
• Optional Left Adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 2.56 V ADC Reference Voltage
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The AT90PWM1 features a 10-bit successive approximation ADC. The ADC is connected to an
15-channel Analog Multiplexer which allows eleven single-ended input. The single-ended volt-
age inputs refer to 0V (GND).
The device also supports 2 differential voltage input combinations which are equipped with a
programmable gain stage, providing amplification steps of 14dB (5x), 20 dB (10x), 26 dB (20x),
or 32dB (40x) on the differential input voltage before the A/D conversion. On the amplified chan-
nels, 8-bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 19-1.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±
0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 187 on how to connect this
pin.
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage refer-
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.
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Figure 19-1. Analog to Digital Converter Block Schematic
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19.2 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be con-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel are selected by writing to the MUX bits in ADMUX. Any of the ADC
input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single
ended inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference is set
by the REFS1 and REFS0 bits in ADMUX register, whatever the ADC is enabled or not. The
ADC does not consume power when ADEN is cleared, so it is recommended to switch off the
ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completed before ADCH
is read, neither register is updated and the result from the conversion is lost. When ADCH is
read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. The ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
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Figure 19-2. ADC Auto Trigger Logic
ADTS[2:0]
PRESCALER
START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. The free
running mode is not allowed on the amplified channels.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
ADEN
START Reset
7-BIT ADC PRESCALER
CK
CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 2 MHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input
clock frequency to the ADC can be higher than 2 MHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference
Selection” on page 185 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 69.
Figure 19-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion
Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3
ADC Clock
ADEN
ADSC
ADIF
MUX
MUX and REFS Conversion and REFS
Update Sample & Hold Complete Update
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
ADC Clock
ADSC
ADIF
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Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion Next Conversion
Cycle Number 1 2 3 4 5 6 7 8 13 14 15 16 1 2
ADC Clock
Trigger
Source
ADATE
ADIF
14 15 16 1 2 3 4
Cycle Number
ADC Clock
ADSC
ADIF
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If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
1. When ADATE or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
In order to start a conversion on an amplified channel, there is a dedicated ADASCR bit in ADC-
SRB register which wait for the next amplifier trigger event before really starting the conversion
by an hardware setting of the ADSC bit in ADCSRA register.
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If differential channels are used, the selected reference should not be closer to AVCC than indi-
cated in Table 136 on page 315.
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Figure 19-8. Analog Input Circuitry
IIH
ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2
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19.6.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected.
(See “Amplifier 0 Control and Status register – AMP0CSR” on page 200. and See “Amplifier
1Control and Status register – AMP1CSR” on page 254.). This offset residue can be then sub-
tracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
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Figure 19-11. Gain Error
Output Code Gain
Error
Ideal ADC
Actual ADC
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Ideal ADC
Actual ADC
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the
interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0
LSB.
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Figure 19-13. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,
a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared
to an ideal transition for any code. This is the compound effect of offset, gain error,
differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.
V IN ⋅ 1023
ADC
V REF
= --------------------------
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 71 on page 193 and Table 72 on page 194). 0x000 represents analog ground, and 0x3FF
represents the selected reference voltage.
If differential channels are used, the result is:
( V POS – V NEG ) ⋅ GAIN ⋅ 512
ADC
V REF
= ------------------------------------------------------------------------
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
GAIN the selected gain factor and VREF the selected voltage reference. The result is presented
in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user
wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result
(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi-
tive. Figure 19-14 shows the decoding of the differential input range.
Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is
selected with a reference voltage of VREF .
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Figure 19-14. Differential Measurement Range
Output Code
0x1FF
0x000
0x200
Example 1:
– ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
– ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270
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– ADCL will thus read 0x00, and ADCH will read 0x9C.
Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.
Example 2:
– ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
– ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 .
– ADCL will thus read 0x40, and ADCH will read 0x0A.
Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
If these bits are changed during a conversion, the change will not take effect until this conversion
is complete (it means while the ADIF bit in ADCSRA register is set).
In case the internal Vref is selected, it is turned ON as soon as an analog feature needed it is
set.
• Bit 5 – ADLAR: ADC Left Adjust Result
Set this bit to left adjust the ADC result.
Clear it to right adjust the ADC result.
The ADLAR bit affects the configuration of the ADC result data registers. Changing this bit
affects the ADC data registers immediately regardless of any on going conversion. For a com-
plete description of this bit, see Section “ADC Result Data Registers – ADCH and ADCL”,
page 196.
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• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits
These 4 bits determine which analog inputs are connected to the ADC input. The different set-
ting are shown in Table 72.
If these bits are changed during a conversion, the change will not take effect until this conversion
is complete (it means while the ADIF bit in ADCSRA register is set).
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• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register.
See Table 74 on page 196.
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the
conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of
the ADC.
The different setting are shown in Table 73.
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event, there is no flag. So in this case a conversion will start each time the trig event appears
and the previous conversion is completed..
19.8.4.1 ADLAR = 0
Bit 7 6 5 4 3 2 1 0
- - - - - - ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
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19.8.4.2 ADLAR = 1
Bit 7 6 5 4 3 2 1 0
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 - - - - - - ADCL
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
• Bit 5:0 – ACMP0D, AMP0+D, AMP0-D, ADC10D..ADC8D: ACMP0, AMP1:0 and ADC10:8
Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
19.9 Amplifier
The AT90PWM1 features two differential amplified channels with programmable 5, 10, 20, and
40 gain stage.
Because the amplifier is a switching capacitor amplifier, it needs to be clocked by a synchroniza-
tion signal called in this document the amplifier synchronization clock. To ensure an accurate
result, the amplifier input needs to have a quite stable input value during at least 4 Amplifier syn-
chronization clock periods.
Amplified conversions can be synchronized to PSC events (See “Synchronization Source
Description in One/Two/Four Ramp Modes” on page 154 and “Synchronization Source Descrip-
tion in Centered Mode” on page 154) or to the internal clock CKADC equal to eighth the ADC
clock frequency. In case the synchronization is done by the ADC clock divided by 8, this syn-
chronization is done automatically by the ADC interface in such a way that the sample-and-hold
occurs at a specific phase of CKADC2. A conversion initiated by the user (i.e., all single conver-
sions, and the first free running conversion) when CKADC2 is low will take the same amount of
time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A
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conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits
in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is done
on each synchronization event. The amplification is done independently of the ADC.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX
must be configured as specified on Table 72 on page 194.
Depending on AT90PWM1 revision the ADC starting is done by setting the ADSC (ADC Start
conversion) bit in the ADCSRB register on AT90PWM1.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown Figure 19-15.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
The conversion takes advantage of the amplifier characteristics to ensure a conversion in less
time.
As soon as a conversion is requested thanks to the ADSC bit, the Digital to Analog Conversion
is started. In case the amplifier output is modified during the sample phase of the ADC, the on-
going conversion is aborted and restarted as soon as the output of the amplifier is stable. This
ensure a fast response time. The only precaution to take is to be sure that the trig signal (PSC)
frequency is lower that ADCclk/4.
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Delta V
4th stable sample
Signal to be
measured
PSC PSCn_ASY
Block
AMPLI_clk
(Sync Clock)
CK ADC
Amplifier
Block
Amplifier Sample
Enable
Amplifier Hold
Value
Valid sample
ADSC
ADC
ADC
Sampling
ADC ADC Aborted ADC
Activity Conv Conv
ADC ADC
Sampling Sampling
ADC Result ADC Result
Ready Ready
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19.10 Amplifier Control Registers
The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and
AMP1CSR. Then the start of conversion is done via the ADC control and status registers.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the less significant bits.
To ensure an accurate result, after the gain value has been changed, the amplifier input needs
to have a quite stable input value during at least 4 Amplifier synchronization clock periods.
• Bit 1, 0– AMP0TS1, AMP0TS0: Amplifier 0 Trigger Source Selection Bits
In accordance with the Table 76, these 2 bits select the event which will generate the trigger for
the amplifier 0. This trigger source is necessary to start the conversion on the amplified channel.
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20. debugWIRE On-chip Debug System
20.1 Features
• Complete Program Flow Control
• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
• Real-time Operation
• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
• Unlimited Number of Program Break Points (Using Software Break Points)
• Non-intrusive Operation
• Electrical Characteristics Identical to Real Device
• Automatic Configuration System
• High-Speed Operation
• Programming of Non-volatile Memories
20.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR instructions in the CPU and to program the different non-volatile
memories.
VCC
dW dW(RESET)
GND
Figure 20-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator
connector. The system clock is not affected by debugWIRE and will always be the clock source
selected by the CKSEL Fuses.
When designing a system where debugWIRE will be used, the following observations must be
made for correct operation:
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• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up
resistor is not required for debugWIRE functionality.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors connected to the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.
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program memory. The program code within the Boot Loader section has the capability to write
into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify
itself, and it can also erase itself from the code if the feature is not needed anymore. The size of
the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets
of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select
different levels of protection.
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section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
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Figure 21-1. Read-While-Write vs. No Read-While-Write
Read-While-Write
(RWW) Section
Z-pointer
Addresses NRWW
Z-pointer Section
Addresses RWW No Read-While-Write
Section (NRWW) Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Figure 21-2. Memory Sections
Program Memory Program Memory
BOOTSZ = '11' BOOTSZ = '10'
0x0000 0x0000
Read-While-Write Section
Read-While-Write Section
No Read-While-Write Section Application Flash Section Application Flash Section
No Read-While-Write Section
End RWW End RWW
Start NRWW Start NRWW
End Application
End Application Start Boot Loader
Start Boot Loader Boot Loader Flash Section
Boot Loader Flash Section
Flashend Flashend
Read-While-Write Section
No Read-While-Write Section
End RWW
Start NRWW Start NRWW, Start Boot Loader
Application Flash Section
End Application
Boot Loader Flash Section
Start Boot Loader
Boot Loader Flash Section
Flashend Flashend
Note: 1. The parameters in the figure above are given in Table 82 on page 215.
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Table 79. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode BLB12 BLB11 Protection
No restrictions for SPM or LPM accessing the Boot Loader
1 1 1
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
3 0 0 from the Boot Loader section. If Interrupt Vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
LPM executing from the Application section is not allowed to
read from the Boot Loader section. If Interrupt Vectors are
4 0 1
placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
Note: 1. “1” means unprogrammed, “0” means programmed
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21.5.1 Store Program Memory Control and Status Register – SPMCSR
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
Since the Flash is organized in pages (see Table 95 on page 222), the Program Counter can be
treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is1 shown in Figure 21-3. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Page Write operation. Once a program-
ming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.
The content of the Z-pointer is ignored and will have no effect on the operation. The LPM
instruction does also use the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
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Figure 21-3. Addressing the Flash During SPM(1)
BIT 15 ZPCMSB ZPAGEMSB 1 0
Z - REGISTER 0
PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER
01
02
PAGEEND
Note: 1. The different variables used in Figure 21-3 are listed in Table 84 on page 216.
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21.7.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
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21.7.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-
ware update by the MCU.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1
See Table 78 and Table 79 for how the different settings of the Boot Loader bits affect the Flash
access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future compatibility it
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-
gramming the Lock bits the entire Flash can be read during the operation.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to Table 88 on page 218 for a detailed
description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to Table 89 on page 219 for detailed description and mapping of the Fuse High byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
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value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.
Refer to Table 88 on page 218 for detailed description and mapping of the Extended Fuse byte.
Bit 7 6 5 4 3 2 1 0
Rd – – – – EFB3 EFB2 EFB1 EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
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; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SPMEN)
call Do_spm
Do_spm:
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; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret
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For details about these two section, see “NRWW – No Read-While-Write Section” on page 204
and “RWW – Read-While-Write Section” on page 204
Table 84. Explanation of Different Variables used in Figure 21-3 and the Mapping to the Z-
pointer
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The
PCMSB 11
Program Counter is 12 bits PC[11:0])
Most significant bit which is used to address the
PAGEMSB 4 words within one page (32 words in a page requires
5 bits PC [4:0]).
Bit in Z-register that is mapped to PCMSB. Because
ZPCMSB Z12
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB.
ZPAGEMSB Z5 Because Z0 is not used, the ZPAGEMSB equals
PAGEMSB + 1.
Program counter page address: Page select, for
PCPAGE PC[11:5] Z12:Z6
page erase and page write
Program counter word address: Word select, for
PCWORD PC[4:0] Z5:Z1 filling temporary buffer (must be zero during page
write operation)
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Notes: 1. “1” means unprogrammed, “0” means programmed.
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22.2 Fuse Bits
The AT90PWM1 has three Fuse bytes. Table 88 - Table 90 describe briefly the functionality of
all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi-
cal zero, “0”, if they are programmed.
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Table 89. Fuse High Byte
High Fuse Byte Bit No Description Default Value
RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)
DWEN 6 debugWIRE Enable 1 (unprogrammed)
Enable Serial Program and 0 (programmed, SPI
SPIEN(2) 5
Data Downloading programming enabled)
WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)
EEPROM memory is
1 (unprogrammed), EEPROM
EESAVE 3 preserved through the Chip
not reserved
Erase
Brown-out Detector trigger
BODLEVEL2(4) 2 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL1(4) 1 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL0(4) 0 1 (unprogrammed)
level
Notes: 1. See “Alternate Functions of Port C” on page 71 for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See “Watchdog Timer Configuration” on page 50 for details.
4. See Table 9-2 on page 44 for BODLEVEL Fuse decoding.
Table 90. Fuse Low Byte
Low Fuse Byte Bit No Description Default Value
(4)
CKDIV8 7 Divide clock by 8 0 (programmed)
CKOUT(3) 6 Clock output 1 (unprogrammed)
SUT1 5 Select start-up time 1 (unprogrammed)(1)
SUT0 4 Select start-up time 0 (programmed) (1)
CKSEL3 3 Select Clock source 0 (programmed) (2)
CKSEL2 2 Select Clock source 0 (programmed) (2)
CKSEL1 1 Select Clock source 1 (unprogrammed)(2)
CKSEL0 0 Select Clock source 0 (programmed) (2)
Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 11 on page 33 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 11 on
page 33 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock Output
Buffer” on page 33 for details.
4. See “System Clock Prescaler” on page 34 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
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22.4 Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space.
BS1 AVCC
PD4
XA0 PD5
PB[7:0] DATA
XA1 PD6
PAGEL PD7
+ 12 V RESET
BS2 PE2
XTAL1
GND
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Table 94. Command Byte Bit Coding
Command Byte Command Executed
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes and Calibration byte
0000 0100 Read Fuse and Lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM
Table 95. No. of Words in a Page and No. of Pages in the Flash
No. of
Device Flash Size Page Size PCWORD Pages PCPAGE PCMSB
4K words
AT90PWM1 32 words PC[4:0] 128 PC[11:5] 11
(8K bytes)
Table 96. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Page No. of
Device Size Size PCWORD Pages PCPAGE EEAMSB
AT90PWM1 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
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1. Set Prog_enable pins listed in Table 92. to “0000”, RESET pin to “0” and Vcc to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor Vcc, and as soon as Vcc reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been
applied to ensure the Prog_enable Signature has been latched.
5. Wait until Vcc actually reaches 4.5 -5.5V before giving any parallel programming
commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
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1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 22-3 for signal
waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address
the pages within the FLASH. This is illustrated in Figure 22-2 on page 225. Note that if less than
eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)
in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY
goes low.
2. Wait until RDY/BSY goes high (See Figure 22-3 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are
reset.
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Figure 22-2. Addressing the Flash Which is Organized in Pages(1)
PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER
01
02
PAGEEND
A B C D E B C D E G H
0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH XX
DATA
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note: 1. “XX” is don’t care. The letters refer to the programming description above.
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5. E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 22-4 for
signal waveforms).
A G B C E B C E L
0x11 ADDR. HIGH ADDR. LOW DATA XX ADDR. LOW DATA XX
DATA
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
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22.8.8 Programming the Fuse Low Bits
The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”
on page 223 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
A C A C A C
0x40 DATA XX 0x40 DATA XX 0x40 DATA XX
DATA
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
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1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
Figure 22-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
0
Extended Fuse Byte 1
DATA
BS2
Lock Bits 0
1
BS1
Fuse High Byte 1
BS2
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1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 22-7. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH tPLBX t BVWL
tWLBX
PAGEL tPHPL
tWLWH
WR tPLWL
WLRL
RDY/BSY
tWLRH
Figure 22-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)
t XLXH tXLPH
tPLXH
XTAL1
BS1
PAGEL
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 22-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
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Figure 22-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 22-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
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Table 98. Parallel Programming Characteristics, V CC = 5V ± 10% (Continued)
Symbol Parameter Min Typ Max Units
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
VCC
+1.8 - 5.5V(2)
MOSI_A
AVCC
MISO_A
SCK_A
XTAL1
RESET
GND
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
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When reading data from the AT90PWM1, data is clocked on the falling edge of SCK. See Figure
22-11 for timing details.
To program and verify the AT90PWM1 in the serial programming mode, the following sequence
is recommended (See four byte instruction formats in Table 100):
1. Power-up sequence:
Apply power between V CC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of
the address. If polling is not used, the user must wait at least t WD_FLASH before issuing the
next page. (See Table 99.) Accessing the serial programming interface before the Flash
write operation completes can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least t WD_EEPROM before issuing the next byte. (See Table 99.) In a chip erased device,
no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn V CC power off.
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a new byte, the programmed value will read correctly. This is used to determine when the next
byte can be written. This will not work for the value 0xFF, but the user should have the following
in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that
are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-pro-
grammed without chip erasing the device. In this case, data polling cannot be used for the value
0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See
Table 99 for tWD_EEPROM value.
Table 99. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 3.6 ms
tWD_ERASE 9.0 ms
SAMPLE
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Table 100. Serial Programming Instruction Set (Continued)
Instruction Format
Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation
1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page
Load EEPROM Memory
buffer. After data is loaded, program
Page (page access)
EEPROM page.
Write EEPROM Memory 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx
Write EEPROM page at address a:b.
Page (page access)
0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”
Read Lock bits = unprogrammed. See Table 85 on
page 216 for details.
1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to
Write Lock bits program Lock bits. See Table 85 on
page 216 for details.
Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
Write Fuse bits unprogram. See Table XXX on page
XXX for details.
1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
Write Fuse High bits unprogram. See Table 89 on page 219
for details.
1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = “0” to program, “1” to
Write Extended Fuse Bits unprogram. See Table 88 on page
218 for details.
0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”
Read Fuse bits = unprogrammed. See Table XXX on
page XXX for details.
0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro-
Read Fuse High bits grammed, “1” = unprogrammed. See
Table 89 on page 219 for details.
0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-
Read Extended Fuse Bits grammed, “1” = unprogrammed. See
Table 88 on page 218 for details.
Read Calibration Byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte
1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is
Poll RDY/BSY still busy. Wait until this bit returns to
“0” before applying another command.
Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
234 AT90PWM1
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AT90PWM1
23. Electrical Characteristics(1)
Operating Temperature.................................. -40°C to +105°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or
Voltage on any Pin except RESET other conditions beyond those indicated in the
with respect to Ground ................................-1.0V to VCC +0.5V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Voltage on RESET with respect to Ground......-1.0V to +13.0V conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V
Note: 1. Electrical Characteristics for this product have not yet been finalized. Please consider all val-
ues listed herein as preliminary and non-contractual.
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23.2 DC Characteristics
TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min. Typ. Max. Units
Port B, C & D and XTAL1,
VIL Input Low Voltage -0.5 0.2VCC(1) V
XTAL2 pins as I/O
Port B, C & D and XTAL1,
VIH Input High Voltage 0.6VCC(2) VCC+0.5 V
XTAL2 pins as I/O
XTAL1 pin , External
VIL1 Input Low Voltage -0.5 0.1VCC(1) V
Clock Selected
XTAL1 pin , External
VIH1 Input High Voltage 0.7VCC(2) VCC+0.5 V
Clock Selected
VIL2 Input Low Voltage RESET pin -0.5 0.2VCC(1) V
(2)
VIH2 Input High Voltage RESET pin 0.9VCC VCC+0.5 V
VIL3 Input Low Voltage RESET pin as I/O -0.5 0.2VCC(1) V
VIH3 Input High Voltage RESET pin as I/O 0.8VCC(2) VCC+0.5 V
(3)
Output Low Voltage
(Port B, C & D and IOL = 20 mA, V CC = 5V 0.7 V
VOL
XTAL1, XTAL2 pins as IOL = 10 mA, V CC = 3V 0.5 V
I/O)
Output High Voltage (4)
(Port B, C & D and IOH = -20 mA, VCC = 5V 4.2 V
VOH
XTAL1, XTAL2 pins as IOH = -10 mA, VCC = 3V 2.4 V
I/O)
236 AT90PWM1
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AT90PWM1
TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
Active 8 MHz, VCC = 3V,
3.8 mA
RC osc, PRR = 0xFF
Active 16 MHz, VCC = 5V,
14 mA
Ext Clock, PRR = 0xFF
Power Supply Current
Idle 8 MHz, VCC = 3V, RC
1.5 mA
Osc
Idle 16 MHz, VCC = 5V,
5.5 mA
Ext Clock
ICC WDT enabled, VCC = 3V
5 µA
t0 < 90°C
WDT enabled, VCC = 3V
9 µA
t0 < 105°C
(5)
Power-down mode
WDT disabled, VCC = 3V
1.5 µA
t0 < 90°C
WDT disabled, VCC = 3V
5 µA
t0 < 105°C
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23.3 External Clock Drive Characteristics
V IH1
V IL1
238 AT90PWM1
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AT90PWM1
At 19 MHz this gives:
16Mhz
8Mhz
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23.5 SPI Timing Characteristics
See Figure 23-3 and Figure 23-4 for details.
Note: In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK >12 MHz
SS
6 1
SCK
(CPOL = 0)
2 2
SCK
(CPOL = 1)
4 5 3
MISO
MSB ... LSB
(Data Input)
7 8
MOSI
MSB ... LSB
(Data Output)
240 AT90PWM1
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AT90PWM1
Figure 23-4. SPI Interface Timing Requirements (Slave Mode)
SS
10 16
9
SCK
(CPOL = 0)
11 11
SCK
(CPOL = 1)
13 14 12
MOSI
MSB ... LSB
(Data Input)
15 17
MISO
MSB ... LSB X
(Data Output)
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23.6 ADC Characteristics
Table 103. ADC Characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min Typ Max Units
Single Ended Conversion 10 Bits
Resolution Differential Conversion
10 Bits
Gain = 10x
Single Ended Conversion
VREF = 2.56V 2.5 LSB
ADC clock = 500 kHz
Single Ended Conversion
VREF = 2.56V 7 (*) LSB
ADC clock = 1MHz
Single Ended Conversion
VREF = 2.56V 30 (*) LSB
ADC clock = 2 MHz
Differential Conversion
Absolute accuracy Gain = 10
5.5 LSB
VREF = 2.56V
ADC clock = 500 kHz
Differential Conversion
Gain = 10
12 (*) LSB
VREF = 2.56V
ADC clock = 1MHz
Differential Conversion
Gain = 10
38 (*) LSB
VREF = 2.56V
ADC clock = 2 MHz
Single Ended Conversion
VCC = 4.5V, VREF = 2.56V 0.7 LSB
ADC clock = 500 kHz
Integral Non-linearity Differential Conversion
Gain = 10
4.5 LSB
VCC = 4.5V, VREF = 2.56V
ADC clock = 500 kHz
Single Ended Conversion
VCC = 4.5V, VREF = 4V 0.35 LSB
ADC clock = 500 kHz
Differential Non-linearity Differential Conversion
Gain = 10
1.08 LSB
VCC = 4.5V, VREF = 4V
ADC clock = 500 kHz
242 AT90PWM1
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AT90PWM1
Table 103. ADC Characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min Typ Max Units
Single Ended Conversion
VCC = 4.5V, VREF = 4V 1.85 LSB
ADC clock = 500 kHz
Zero Error (Offset) Differential Conversion
Gain = 10
-3.2 LSB
VCC = 4.5V, VREF = 4V
ADC clock = 500 kHz
Conversion Time Single Conversion 8 260 µs
Clock Frequency 50 2000 kHz
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
Single Ended Conversion 2.0 AVCC V
VREF Reference Voltage
Differential Conversion 2.0 AVCC - 0.2 V
VIN Single Ended Conversion GND VREF
Input voltage
Differential Conversion -VREF/Gain +VREF/Gain
Single Ended Conversion 38.5 kHz
Input bandwidth
Differential Conversion 4 kHz
VINT Internal Voltage Reference 2.4 2.56 2.8 V
RREF Reference Input Resistance 30 kΩ
RAIN Analog Input Resistance 100 MΩ
Figure 23-5. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH tPLBX t BVWL
tWLBX
PAGEL tPHPL
tWLWH
WR tPLWL
WLRL
RDY/BSY
tWLRH
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Figure 23-6. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)
t XLXH tXLPH
tPLXH
XTAL1
BS1
PAGEL
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 23-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
Figure 23-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1
Note: 1. ggThe timing requirements shown in Figure 23-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to
reading operation.
244 AT90PWM1
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Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
245
4378A–AVR–06/06
additional current consumption compared to ICC Active and I CC Idle for every I/O module con-
trolled by the Power Reduction Register. See “Power Reduction Register” on page 37 for details.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-
ture. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-
rent drawn by the Watchdog Timer.
Figure 24-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
1,6
1,4 5.5 V
1,2 5.0 V
1 4.5 V
ICC (mA)
4.0 V
0,8
3.3 V
0,6 3.0 V
2.7 V
0,4
0,2
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
246 AT90PWM1
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AT90PWM1
Figure 24-2. Active Supply Current vs. Frequency (1 - 24 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
30
25
5.5 V
20
5.0 V
4.5 V
ICC (mA)
15
10 4.0 V
3.3 V
5 3.0 V
2.7 V
0
0 5 10 15 20 25
Frequency (MHz)
Figure 24-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. V CC
INTERNAL RC OSCILLATOR, 8 MHz
9 105 °C
85 °C
25 °C
8 -40 °C
7
5
ICC (mA)
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
247
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Figure 24-4. Active Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz)
ACTIVE SUPPLY CURRENT vs. V CC
INTERNAL PLL OSCILLATOR, 16 MHz
20
105 °C
18 85 °C
25 °C
16
-40 °C
14
12
ICC (mA)
10
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
0,45
0,4
5.5 V
0,35
5.0 V
0,3 4.5 V
0,25 4.0 V
ICC (mA)
0,2
3.3 V
3.0 V
0,15 2.7 V
0,1
0,05
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
248 AT90PWM1
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AT90PWM1
Figure 24-6. Idle Supply Current vs. Frequency (1 - 24 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
12
10
5.5 V
5.0 V
8
4.5 V
ICC (mA)
4 4.0 V
3.3 V
2 3.0 V
2.7 V
0
-1 1 3 5 7 9 11 13 15 17 19 21 23 25
Frequency (MHz)
Figure 24-7. IIdle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
IDLE SUPPLY CURRENT vs. V CC
INTERNAL RC OSCILLATOR, 8 MHz
3,5 105 °C
85 °C
25 °C
3 -40 °C
2,5
ICC (mA)
1,5
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
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Figure 24-8. Idle Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL PLL OSCILLATOR, 16 MHz
8 105 °C
85 °C
25 °C
7 -40 °C
5
ICC (mA)
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Table 105.
Additional Current Consumption for the different I/O modules (absolute values)
PRR bit Typical numbers
VCC = 3V, F = 8MHz VCC = 5V, F = 16MHz
PRPSC2 350 uA 1.3 mA
PRPSC1 350 uA 1.3 mA
PRPSC0 350 uA 1.3 mA
PRTIM1 300 uA 1.15 mA
PRTIM0 200 uA 0.75 mA
PRSPI 250 uA 0.9 mA
PRUSART 550 uA 2 mA
PRADC 350 uA 1.3 mA
250 AT90PWM1
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AT90PWM1
Table 106.
Additional Current Consumption (percentage) in Active and Idle mode
Additional Current consumption
compared to Active with external Additional Current consumption
clock compared to Idle with external clock
PRR bit (see Figure 24-1 and Figure 24-2) (see Figure 24-5 and Figure 24-6)
PRPSC2 10% 25%
PRPSC1 10% 25%
PRPSC0 10% 25%
PRTIM1 8.5% 22%
PRTIM0 4.3% 11%
PRSPI 5.3% 14%
PRUSART 15.6 36
PRADC 10.5% 25%
It is possible to calculate the typical current consumption based on the numbers from Table 2 for
other VCC and frequency settings than listed in Table 1.
24.2.1.1 Example 1
Calculate the expected current consumption in idle mode with USART0, TIMER1, and TWI
enabled at VCC = 3.0V and F = 1MHz. From Table 2, third column, we see that we need to add
18% for the USART0, 26% for the TWI, and 11% for the TIMER1 module. Reading from Figure
3, we find that the idle current consumption is ~0,075mA at VCC = 3.0V and F = 1MHz. The total
current consumption in idle mode with USART0, TIMER1, and TWI enabled, gives:
I CC total ≈ 0,075 mA • ( 1 + 0,18 + 0,26 + 0,11 ) ≈ 0,116 mA
24.2.1.2 Example 2
Same conditions as in example 1, but in active mode instead. From Table 2, second column we
see that we need to add 3.3% for the USART0, 4.8% for the TWI, and 2.0% for the TIMER1
module. Reading from Figure 1, we find that the active current consumption is ~0,42mA at VCC =
3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and
TWI enabled, gives:
I CC total ≈ 0,42 mA • ( 1 + 0,033 + 0,048 + 0,02 ) ≈ 0,46 mA
24.2.1.3 Example 3
All I/O modules should be enabled. Calculate the expected current consumption in active mode
at VCC = 3.6V and F = 10MHz. We find the active current consumption without the I/O modules
to be ~ 4.0mA (from Figure 2). Then, by using the numbers from Table 2 - second column, we
find the total current consumption:
I CC total ≈ 4,0 mA • ( 1 + 0,033 + 0,048 + 0,047 + 0,02 + 0,016 + 0,061 + 0,049 ) ≈ 5,1 mA
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24.3 Power-Down Supply Current
Figure 24-9. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. V CC
WATCHDOG TIMER DISABLED
6 105 °C
4
ICC (uA)
3
85 °C
-40 °C
1 25 °C
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-10. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
14
105 °C
12
10
85 °C
-40 °C
8 25 °C
ICC (uA)
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
252 AT90PWM1
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AT90PWM1
24.4 Power-Save Supply Current
Figure 24-11. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled)
10
T E I Z ED 25 °C
PLA T ER
M AC
8
TE R
HA
ICC (uA)
6
C
BE
TO
4
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
450
E E D 16 MHz Xtal
T Z
400
LA ERI 12 MHz Xtal
350
M P CT
300 TE AR
A
H
ICC (uA)
C
BE
250
6 MHz Xtal
(ckopt)
TO
200
4 MHz Xtal
150 (ckopt)
2 MHz Xtal
100
(ckopt)
50
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
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24.6 Pin Pull-up
Figure 24-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN (including PE1 & PE2) PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5.0 V
-40 °C
160
25 °C
85 °C 140
105 °C
120
100
80
IOP (uA)
60
40
20
0
0 1 2 3 4 5 6
-20
V OP (V)
Figure 24-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN (including PE1 & PE2) PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7 V
-40 °C 90
25 °C 80
85 °C
105 °C 70
60
50
IOP (uA)
40
30
20
10
0
0 0,5 1 1,5 2 2,5 3
-10
V OP (V)
254 AT90PWM1
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AT90PWM1
Figure 24-15. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5.0 V
25 °C 120
-40 °C
85 °C
105 °C 100
80
IOP (uA)
60
40
20
0
0 1 2 3 4 5 6
V OP (V)
Figure 24-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7 V
70
25 °C
-40 °C 60
85 °C
105 °C 50
40
IOP (uA)
30
20
10
0
0 0,5 1 1,5 2 2,5 3
V OP (V)
255
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24.7 Pin Driver Strength
Figure 24-17. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5.0 V
25
85 °C 25 °C -40 °C
20
105 °C
15
IOH (mA)
10
0
4 4,2 4,4 4,6 4,8 5 5,2
V OH (V)
Figure 24-18. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7 V
25
105 °C 85 °C 25 °C -40 °C
20
15
IOH (mA)
10
0
0 0,5 1 1,5 2 2,5 3
V OH (V)
256 AT90PWM1
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AT90PWM1
Figure 24-19. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5.0 V
25
-40 °C25 °C 85 °C105 °C
20
15
IOL (mA)
10
0
0 0,2 0,4 0,6 0,8 1
-5
V OL (V)
Figure 24-20. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7 V
25
-40 °C 25 °C 85 °C 105 °C
20
15
IOL (mA)
10
0
0 0,5 1 1,5 2 2,5 3
-5
V OL (V)
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24.8 Pin Thresholds and Hysteresis
Figure 24-21. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1')
I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2,5
-40 °C
25 °C
2 85 °C
105 °C
1,5
Threshold (V)
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-22. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0')
I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs. V CC
VIL, IO PIN READ AS '0'
2,5
-40 °C
25 °C
1,5
Threshold (V)
85 °C
105 °C
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
258 AT90PWM1
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AT90PWM1
Figure 24-23. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1')
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1'
2,5
1,5 -40 °C
Threshold (V)
25 °C
85 °C
105 °C
1
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-24. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0')
RESET INPUT THRESHOLD VOLTAGE vs. V CC
VIL, RESET PIN READ AS '0'
2,5 105 °C
85 °C
25 °C
-40 °C
2
1,5
Threshold (V)
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
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Figure 24-25. Reset Input Pin Hysteresis vs. VCC
RESET PIN INPUT HYSTERESIS vs. VCC
0,6
-40 °C
Input Hysteresis (V) 0,5
0,4
25 °C
0,3
0,2
85 °C
105 °C
0,1
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-26. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '1')
XTAL1 INPUT THRESHOLD VOLTAGE vs. VCC
XTAL1 PIN READ AS "1"
3,5 -40 °C
25 °C
3 85 °C
105 °C
2,5
Threshold (V)
1,5
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
260 AT90PWM1
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AT90PWM1
Figure 24-27. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '0')
XTAL1 INPUT THRESHOLD VOLTAGE vs. V CC
XTAL1 PIN READ AS "0"
3,5
2,5
Threshold (V)
-40 °C
2 25 °C
85 °C
105 °C
1,5
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Figure 24-28. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '1')
PE0 INPUT THRESHOLD VOLTAGE vs. VCC
VIH, PE0 PIN READ AS '1'
4 -40 °C
25 °C
3,5 85 °C
105 °C
3
2,5
Threshold (V)
1,5
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
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Figure 24-29. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '0')
PE0 INPUT THRESHOLD VOLTAGE vs. VCC
VIL, PE0 PIN READ AS '0'
2,5
105 °C
85 °C
2 25 °C
-40 °C
1,5
Threshold (V)
0,5
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
4,42
Rising Vcc
4,4
4,38
Threshold (V)
4,36
4,34
Falling Vcc
4,32
4,3
4,28
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (C)
262 AT90PWM1
4378A–AVR–06/06
AT90PWM1
Figure 24-31. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLV IS 2.7 V
2,82
2,78
Threshold (V)
2,76
2,74
Falling Vcc
2,72
2,7
2,68
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (C)
2,6
105 °C
85 °C
25 °C
2,55
-40 °C
2,5
Aref (V)
2,45
2,4
2,35
2,3
2 2,5 3 3,5 4 4,5 5 5,5
Vcc (V)
263
4378A–AVR–06/06
Figure 24-33. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC=5V)
ANALOG COMPARATOR TYPICAL OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
Vcc = 5.0 V
0,14
0,12
Analog comparator offset voltage (V)
0,1
0,08
0,06
0,04
0,02
0
0 1 2 3 4 5 6
Common Mode Voltage (V)
Figure 24-34. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC=3V)
ANALOG COMPARATOR TYPICAL OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
Vcc = 3.0 V
0,045
0,04
Analog comparator offset voltage (V)
0,035
0,03
0,025
0,02
0,015
0,01
0,005
0
0 0,5 1 1,5 2 2,5 3 3,5
Common Mode Voltage (V)
264 AT90PWM1
4378A–AVR–06/06
AT90PWM1
24.10 Internal Oscillator Speed
110
108
106
-40 °C
104
FRC (kHz)
25 °C
102
100
85 °C
98
105 °C
96
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
8.4
8.3
D 5.0 V
8.2
TE IZE 2.7 V
8.1
PLA T ER 1.8 V
M AC
8
TE R
FRC (MHz)
7.9
C HA
7.8
BE
7.7 TO
7.6
7.5
7.4
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
265
4378A–AVR–06/06
Figure 24-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
8.6
8.4
D
AT
E I ZE
ER
85 ˚C
L
MP CT
8.2
TE A
FRC (MHz)
R
HA
8 25 ˚C
C
7.8 BE -40 ˚C
TO
7.6
7.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
16
105 °C
85 °C
14 25 °C
-40 °C
12
10
FRC (MHz)
0
-1 15 31 47 63 79 95 111 127 143 159 175 191 207 223 239 255
OSCCAL (X1)
266 AT90PWM1
4378A–AVR–06/06
AT90PWM1
24.11 Current Consumption of Peripheral Units
45
40
35
30
105 °C
25 85 °C
ICC (uA)
25 °C
20 -40 °C
15
10
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
450
-40 °C
400
E Z ED 25 °C
L AT ER
I 85 °C
MP CT
350
ICC (uA)
TE R A
HA
300
C
250
BE
200
TO
150
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
267
4378A–AVR–06/06
Figure 24-41. Aref Current vs. VCC (ADC at 1 MHz)
120
ICC (uA)
100
80
60
40
20
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
80
-40 °C
105 °C
70 85 °C
25 °C
60
50
ICC (uA)
40
30
20
10
0
2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
268 AT90PWM1
4378A–AVR–06/06
AT90PWM1
Figure 24-43. Programming Current vs. VCC
14
12 -40 ˚C
10
25 ˚C
8
ICC (mA)
85 ˚C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 24-44. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the
Reset Pull-up)
0,18
0,16 5.5 V
0,14 5.0 V
0,12 4.5 V
0,1 4.0 V
ICC (mA)
0,08 3.3 V
3.0 V
0,06 2.7 V
0,04
0,02
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
269
4378A–AVR–06/06
Figure 24-45. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the Reset
Pull-up)
RESET SUPPLY CURRENT vs. V CC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
4
5.5 V
3,5
5.0 V
3
4.5 V
2,5
ICC (mA)
1,5 4.0 V
1 3.3 V
3.0 V
0,5 2.7 V
0
0 5 10 15 20 25
Frequency (MHz)
Figure 24-46. Reset Supply Current vs. VCC (Clock Stopped, Excluding Current through the
Reset Pull-up)
RESET CURRENT vs. VCC (CLOCK STOPPED)
EXCLUDING CURRENT THROUGH THE RESET PULLUP
0,05
0,04
0,03
ICC (mA)
0,02
105 °C
0,01 -40 °C
85 °C
25 °C
0
2 2,5 3 3,5 4 4,5 5 5,5
-0,01
V CC (V)
270 AT90PWM1
4378A–AVR–06/06
AT90PWM1
Figure 24-47. Reset Pulse Width vs. VCC
RESET PULSE WIDTH vs. VCC
Ext Clock 1 MHz
1600
1400
1200
1000
Pulsewidth (ns)
800
600 105 °C
85 °C
400 25 °C
-40 °C
200
0
0 1 2 3 4 5 6
VCC (V)
271
4378A–AVR–06/06
25. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) PICR2H page 161
(0xFE) PICR2L page 161
(0xFD) PFRC2B PCAE2B PISEL2B PELEV2B PFLTE2B PRFM2B3 PRFM2B2 PRFM2B1 PRFM2B0 page 160
(0xFC) PFRC2A PCAE2A PISEL2A PELEV2A PFLTE2A PRFM2A3 PRFM2A2 PRFM2A1 PRFM2A0 page 160
(0xFB) PCTL2 PPRE21 PPRE20 PBFM2 PAOC2B PAOC2A PARUN2 PCCYC2 PRUN2 page 159
(0xFA) PCNF2 PFIFTY2 PALOCK2 PLOCK2 PMODE21 PMODE20 POP2 PCLKSEL2 POME2 page 156
(0xF9) OCR2RBH page 156
(0xF8) OCR2RBL page 156
(0xF7) OCR2SBH page 156
(0xF6) OCR2SBL page 156
(0xF5) OCR2RAH page 155
(0xF4) OCR2RAL page 155
(0xF3) OCR2SAH page 155
(0xF2) OCR2SAL page 155
(0xF1) POM2 POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 page 162
(0xF0) PSOC2 POS23 POS22 PSYNC21 PSYNC20 POEN2D POEN2B POEN2C POEN2A page 154
(0xEF) PICR1H page 169
(0xEE) PICR1L page 169
(0xED) PFRC1B PCAE1B PISEL1B PELEV1B PFLTE1B PRFM1B3 PRFM1B2 PRFM1B1 PRFM1B0 page 160
(0xEC) PFRC1A PCAE1A PISEL1A PELEV1A PFLTE1A PRFM1A3 PRFM1A2 PRFM1A1 PRFM1A0 page 160
(0xEB) PCTL1 PRUN1 page 159
(0xEA) Reserved – – – – – – – –
(0xE9) Reserved – – – – – – – –
(0xE8) Reserved – – – – – – – –
(0xE7) Reserved – – – – – – – –
(0xE6) Reserved – – – – – – – –
(0xE5) Reserved – – – – – – – –
(0xE4) Reserved – – – – – – – –
(0xE3) Reserved – – – – – – – –
(0xE2) Reserved – – – – – – – –
(0xE1) Reserved – – – – – – – –
(0xE0) PSOC1 – – PSYNC11 PSYNC10 – POEN1B – POEN1A page 161
(0xDF) PICR0H page 161
(0xDE) PICR0L page 161
(0xDD) PFRC0B PCAE0B PISEL0B PELEV0B PFLTE0B PRFM0B3 PRFM0B2 PRFM0B1 PRFM0B0 page 160
(0xDC) PFRC0A PCAE0A PISEL0A PELEV0A PFLTE0A PRFM0A3 PRFM0A2 PRFM0A1 PRFM0A0 page 160
(0xDB) PCTL0 PPRE01 PPRE00 PBFM0 PAOC0B PAOC0A PARUN0 PCCYC0 PRUN0 page 157
(0xDA) PCNF0 PFIFTY0 PALOCK0 PLOCK0 PMODE01 PMODE00 POP0 PCLKSEL0 - page 156
(0xD9) OCR0RBH page 156
(0xD8) OCR0RBL page 156
(0xD7) OCR0SBH page 156
(0xD6) OCR0SBL page 156
(0xD5) OCR0RAH page 155
(0xD4) OCR0RAL page 155
(0xD3) OCR0SAH page 155
(0xD2) OCR0SAL page 155
(0xD1) Reserved – – – – – – – –
(0xD0) PSOC0 – – PSYNC01 PSYNC00 – POEN0B – POEN0A page 154
(0xCF) Reserved – – – – – – – –
(0xCE) Reserved – – – – – – – –
(0xCD) Reserved – – – – – – – –
(0xCC) Reserved – – – – – – – –
(0xCB) Reserved – – – – – – – –
(0xCA) Reserved – – – – – – – –
(0xC9) Reserved – – – – – – – –
(0xC8) Reserved – – – – – – – –
(0xC7) Reserved – – – – – – – –
(0xC6) Reserved – – – – – – – –
(0xC5) Reserved – – – – – – – –
(0xC4) Reserved – – – – – – – –
(0xC3) Reserved – – – – – – – –
(0xC2) Reserved – – – – – – – –
(0xC1) Reserved – – – – – – – –
(0xC0) Reserved – – – – – – – –
(0xBF) Reserved – – – – – – – –
272 AT90PWM1
4378A–AVR–06/06
AT90PWM1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xBE) Reserved – – – – – – – –
(0xBD) Reserved – – – – – – – –
(0xBC) Reserved – – – – – – – –
(0xBB) Reserved – – – – – – – –
(0xBA) Reserved – – – – – – – –
(0xB9) Reserved – – – – – – – –
(0xB8) Reserved – – – – – – – –
(0xB7) Reserved – – – – – – – –
(0xB6) Reserved – – – – – – – –
(0xB5) Reserved – – – – – – – –
(0xB4) Reserved – – – – – – – –
(0xB3) Reserved – – – – – – – –
(0xB2) Reserved – – – – – – – –
(0xB1) Reserved – – – – – – – –
(0xB0) Reserved – – – – – – – –
(0xAF) AC2CON AC2EN AC2IE AC2IS1 AC2IS0 AC2SADE- AC2M2 AC2M1 AC2M0 page 177
(0xAD) AC0CON AC0EN AC0IE AC0IS1 AC0IS0 - AC0M2 AC0M1 AC0M0 page 176
(0xAC) Reserved – – – – – – – – page 258
(0xAB) Reserved – – – – – – – – page 258
(0xAA) Reserved – – – – – – – – page 257
(0xA9) Reserved – – – – – – – –
(0xA8) Reserved – – – – – – – –
(0xA7) Reserved – – – – – – – –
(0xA6) Reserved – – – – – – – –
(0xA5) PIM2 - - PSEIE2 PEVE2B PEVE2A - - PEOPE2 page 163
(0xA4) PIFR2 - - PSEI2 PEV2B PEV2A PRN21 PRN20 PEOP2 page 163
(0xA3) Reserved – – – – – – – –
(0xA2) Reserved – – – – – – – –
(0xA1) PIM0 - - PSEIE0 PEVE0B PEVE0A - - PEOPE0 page 163
(0xA0) PIFR0 - - PSEI0 PEV0B PEV0A PRN01 PRN00 PEOP0 page 163
(0x9F) Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved – – – – – – – –
(0x92) Reserved – – – – – – – –
(0x91) Reserved – – – – – – – –
(0x90) Reserved – – – – – – – –
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) OCR1BH OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11 OCR1B10 OCR1B9 OCR1B8 page 119
(0x8A) OCR1BL OCR1B7 OCR1B6 OCR1B5 OCR1B4 OCR1B3 OCR1B2 OCR1B1 OCR1B0 page 119
(0x89) OCR1AH OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11 OCR1A10 OCR1A9 OCR1A8 page 119
(0x88) OCR1AL OCR1A7 OCR1A6 OCR1A5 OCR1A4 OCR1A3 OCR1A2 OCR1A1 OCR1A0 page 119
(0x87) ICR1H ICR115 ICR114 ICR113 ICR112 ICR111 ICR110 ICR19 ICR18 page 120
(0x86) ICR1L ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 page 120
(0x85) TCNT1H TCNT115 TCNT114 TCNT113 TCNT112 TCNT111 TCNT110 TCNT19 TCNT18 page 119
(0x84) TCNT1L TCNT17 TCNT16 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 page 119
(0x83) Reserved – – – – – – – –
(0x82) TCCR1C FOC1A FOC1B – – – – – – page 118
(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 page 117
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 page 115
(0x7F) DIDR1 – – ACMP0D AMP0PD AMP0ND ADC10D/ACMP1D ADC9D/AMP1PD ADC8D/AMP1ND page 197
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D/ACMPMD ADC2D/ACMP2D ADC1D ADC0D page 197
(0x7D) Reserved – – – – – – – –
273
4378A–AVR–06/06
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 193
(0x7B) ADCSRB ADHSM – – ADASCR ADTS3 ADTS2 ADTS1 ADTS0 page 195
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 194
(0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 196
(0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 / - ADC0 / page 196
(0x77)
(0x76) AMP0CSR AMP0EN - AMP0G1 AMP0G0 - AMP0TS2 AMP0TS1 AMP0TS0 page 200
(0x75) Reserved – – – – – – – –
(0x74) Reserved – – – – – – – –
(0x73) Reserved – – – – – – – –
(0x72) Reserved – – – – – – – –
(0x71) Reserved – – – – – – – –
(0x70) Reserved – – – – – – – –
(0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 page 120
(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 page 93
(0x6D) Reserved – – – – – – – –
(0x6C) Reserved – – – – – – – –
(0x6B) Reserved – – – – – – – –
(0x6A) Reserved – – – – – – – –
(0x69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 page 73
(0x68) Reserved – – – – – – – –
(0x67) Reserved – – – – – – – –
(0x66) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 page 30
(0x65) Reserved – – – – – – – –
(0x64) PRR PRPSC2 PRPSC1 PRPSC0 PRTIM1 PRTIM0 PRSPI – PRADC page 38
(0x63) Reserved – – – – – – – –
(0x62) Reserved – – – – – – – –
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 34
(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 49
0x3F (0x5F) SREG I T H S V N Z C page 10
0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 12
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 12
0x3C (0x5C) Reserved – – – – – – – –
0x3B (0x5B) Reserved – – – – – – – –
0x3A (0x5A) Reserved – – – – – – – –
0x39 (0x59) Reserved – – – – – – – –
0x38 (0x58) Reserved – – – – – – – –
0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN page 208
0x36 (0x56) Reserved – – – – – – – –
0x35 (0x55) MCUCR SPIPS – – PUD – – IVSEL IVCE page 55 & page 64
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF page 45
0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE page 36
0x32 (0x52) MSMCR Monitor Stop Mode Control Register reserved
0x31 (0x51) MONDR Monitor Data Register reserved
0x30 (0x50) ACSR ACCKDIV AC2IF – AC0IF – AC2O – AC0O page 178
0x2F (0x4F) Reserved – – – – – – – –
0x2E (0x4E) SPDR SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 page 173
0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X page 172
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 page 171
0x2B (0x4B) Reserved – – – – – – – –
0x2A (0x4A) Reserved – – – – – – – –
0x29 (0x49) PLLCSR - - - - - PLLF PLLE PLOCK page 32
0x28 (0x48) OCR0B OCR0B7 OCR0B6 OCR0B5 OCR0B4 OCR0B3 OCR0B2 OCR0B1 OCR0B0 page 93
0x27 (0x47) OCR0A OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0 page 92
0x26 (0x46) TCNT0 TCNT07 TCNT06 TCNT05 TCNT04 TCNT03 TCNT02 TCNT01 TCNT00 page 92
0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 91
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 page 88
0x23 (0x43) GTCCR TSM ICPSEL1 – – – – – PSRSYNC page 76
0x22 (0x42) EEARH – – – – EEAR11 EEAR10 EEAR9 EEAR8 page 19
0x21 (0x41) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 19
0x20 (0x40) EEDR EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 page 19
0x1F (0x3F) EECR – – – – EERIE EEMWE EEWE EERE page 19
0x1E (0x3E) GPIOR0 GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 page 24
0x1D (0x3D) EIMSK – – – – INT3 INT2 INT1 INT0 page 74
0x1C (0x3C) EIFR – – – – INTF3 INTF2 INTF1 INTF0 page 74
0x1B (0x3B) GPIOR3 GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 page 24
274 AT90PWM1
4378A–AVR–06/06
AT90PWM1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1A (0x3A) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 24
0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 24
0x18 (0x38) Reserved – – – – – – – –
0x17 (0x37) Reserved – – – – – – – –
0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 121
0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 page 93
0x14 (0x34) Reserved – – – – – – – –
0x13 (0x33) Reserved – – – – – – – –
0x12 (0x32) Reserved – – – – – – – –
0x11 (0x31) Reserved – – – – – – – –
0x10 (0x30) Reserved – – – – – – – –
0x0F (0x2F) Reserved – – – – – – – –
0x0E (0x2E) PORTE – – – – – PORTE2 PORTE1 PORTE0 page 72
0x0D (0x2D) DDRE – – – – – DDE2 DDE1 DDE0 page 72
0x0C (0x2C) PINE – – – – – PINE2 PINE1 PINE0 page 72
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 72
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 72
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 72
0x08 (0x28) – – – – – – – – – –
0x07 (0x27) – – – – – – – – – –
0x06 (0x26) – – – – – – – – – –
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 71
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 71
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 72
0x02 (0x22) Reserved – – – – – – – –
0x01 (0x21) Reserved – – – – – – – –
0x00 (0x20) Reserved – – – – – – – –
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM1 is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
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26. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
276 AT90PWM1
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AT90PWM1
Mnemonics Operands Description Operation Flags #Clocks
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
SEV Set Twos Complement Overflow. V←1 V 1
CLV Clear Twos Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1
CLH Clear Half Carry Flag in SREG H←0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
277
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Mnemonics Operands Description Operation Flags #Clocks
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
278 AT90PWM1
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AT90PWM1
27. Ordering Information
279
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28. Package Information
Package Type
280 AT90PWM1
4378A–AVR–06/06
AT90PWM1
28.1 SO24
281
4378A–AVR–06/06
Table of Contents
1 History ....................................................................................................... 2
2 Disclaimer ................................................................................................. 2
4 Overview ................................................................................................... 4
4.1 Block Diagram ......................................................................................................5
4.2 Pin Descriptions ...................................................................................................6
4.3 About Code Examples .........................................................................................7
6 Memories ................................................................................................ 16
6.1 In-System Reprogrammable Flash Program Memory .......................................16
6.2 SRAM Data Memory ..........................................................................................17
6.3 EEPROM Data Memory .....................................................................................18
6.4 I/O Memory ........................................................................................................24
6.5 General Purpose I/O Registers ..........................................................................24
282 AT90PWM1
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AT90PWM1
7.9 Clock Output Buffer ............................................................................................33
7.10 System Clock Prescaler .....................................................................................34
10 Interrupts ................................................................................................ 52
10.1 Interrupt Vectors in AT90PWM1 ........................................................................52
11 I/O-Ports .................................................................................................. 57
11.1 Introduction ........................................................................................................57
11.2 Ports as General Digital I/O ...............................................................................58
11.3 Alternate Port Functions ....................................................................................62
11.4 Register Description for I/O-Ports ...................................................................... 71
283
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15.3 Timer/Counter Clock Sources ..........................................................................100
15.4 Counter Unit .....................................................................................................101
15.5 Input Capture Unit ............................................................................................ 102
15.6 Output Compare Units ..................................................................................... 103
15.7 Compare Match Output Unit ............................................................................105
15.8 Modes of Operation .........................................................................................106
15.9 Timer/Counter Timing Diagrams ......................................................................114
15.10 16-bit Timer/Counter Register Description .......................................................115
284 AT90PWM1
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AT90PWM1
17 Serial Peripheral Interface – SPI ......................................................... 165
17.1 Features ...........................................................................................................165
17.2 SS Pin Functionality .........................................................................................170
17.3 Data Modes ......................................................................................................173
285
4378A–AVR–06/06
22.1 Program And Data Memory Lock Bits ..............................................................216
22.2 Fuse Bits .......................................................................................................... 218
22.3 PSC Output Behaviour During Reset ...............................................................218
22.4 Signature Bytes ................................................................................................220
22.5 Calibration Byte ................................................................................................220
22.6 Parallel Programming Parameters, Pin Mapping, and Commands .................220
22.7 Serial Programming Pin Mapping .................................................................... 222
22.8 Parallel Programming ......................................................................................222
22.9 Serial Downloading ..........................................................................................231
286 AT90PWM1
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AT90PWM1
28.1 SO24 ................................................................................................................281
287
4378A–AVR–06/06
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4378A–AVR–06/06