ANALOG and DIGITAL ELECTRONICS
ANALOG and DIGITAL ELECTRONICS
ANALOG and DIGITAL ELECTRONICS
MCQ 8.1 In the sum of products function f (X, Y, Z) = /(2, 3, 4, 5), the prime
implicants are
(A) XY, XY (B) XY, X Y Z , XYZ
MCQ 8.2 The i -v characteristics of the diode in the circuit given below are
v − 0.7 A, v $ 0.7 V
i = * 500
0A v < 0.7 V
MCQ 8.3 The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is
greater than the 2-bit input B . The number of combinations for which the
output is logic 1, is
(A) 4 (B) 6
(C) 8 (D) 10
1
(A) low pass filter with f3dB = (R )C
rad/s
1 + R2
1
(B) high pass filter with f3dB = rad/s
R1C
1
(C) low pass filter with f3dB = rad/s
R1C
1
(D) high pass filter with f3dB = (R )C
rad/s
1 + R2
MCQ 8.8 A low-pass filter with a cut-off frequency of 30 Hz is cascaded with a high
pass filter with a cut-off frequency of 20 Hz. The resultant system of filters
will function as
(A) an all – pass filter
(B) an all – stop filter
(C) an band stop (band-reject) filter
(D) a band – pass filter
MCQ 8.9
(A) 1 (B) 0
(C) X (D) X
MCQ 8.11 A portion of the main program to call a subroutine SUB in an 8085
environment is given below.
h
LXI D, DISP
LP : CALL SUB
LP+3
h
It is desired that control be returned to LP+DISP+3 when the RET
instruction is executed in the subroutine. The set of instructions that
precede the RET instruction in the subroutine are
POP H
DAD D
POP D
INX H
(A) DAD H (B)
INX H
PUSH D
INX H
PUSH H
XTHL
POP H INX D
(C) DAD D (D) INX D
PUSH H INX D
XTHL
MCQ 8.12 The transistor used in the circuit shown below has a β of 30 and ICBO is
negligible
If the forward voltage drop of diode is 0.7 V, then the current through
collector will be
(A) 168 mA (B) 108 mA
(C) 20.54 mA (D) 5.36 mA
It the state QAQB of the counter at the clock time tn is ‘10’ then the state
Q A QB of the counter at tn + 3 (after three clock cycles) will be
(A) 00 (B) 01
(C) 10 (D) 11
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MCQ 8.15 Given that the op-amp is ideal, the output voltage vo is
(A) 4 V (B) 6 V
(C) 7.5 V (D) 12.12 V
MCQ 8.16 Assuming that the diodes in the given circuit are ideal, the voltage V0 is
(A) 4 V (B) 5 V
(C) 7.5 V (D) 12.12 V
MCQ 8.17 The transistor circuit shown uses a silicon transistor with VBE = 0.7, IC . IE
and a dc current gain of 100. The value of V0 is
MCQ 8.18 The TTL circuit shown in the figure is fed with the waveform X (also
shown). All gates have equal propagation delay of 10 ns. The output Y of
the circuit is
MCQ 8.19 When a “CALL Addr” instruction is executed, the CPU carries out the
following sequential operations internally :
Note: (R) means content of register R
((R)) means content of memory location pointed to by R.
PC means Program Counter
SP means Stack Pointer
(A) (SP) incremented (B) (PC)!Addr
(PC)!Addr ((SP))!(PC)
((SP))!(PC) (SP) incremented
(C) (PC)!Addr (D) ((SP))!(PC)
(SP) incremented (SP) incremented
((SP))!(PC) (PC)!Addr
MCQ 8.21 Which of the following circuits is a realization of the above function F ?
MCQ 8.22 The following circuit has a source voltage VS as shown in the graph. The
current through the circuit is also shown.
MCQ 8.23 The increasing order of speed of data access for the following device is
(I) Cache Memory
(II) CD-ROM
(III) Dynamic RAM
(IV) Processor Registers
(V) Magnetic Tape
(A) (V), (II), (III), (IV), (I) (B) (V), (II), (III), (I), (IV)
(C) (II), (I), (III), (IV), (V) (D) (V), (II), (I), (III), (IV)
MCQ 8.26 The following circuit has R = 10 kΩ, C = 10 μF. The input voltage is a
sinusoidal at 50 Hz with an rms value of 10 V. Under ideal conditions, the
current Is from the source is
MCQ 8.28 In an 8085 microprocessor, the contents of the Accumulator, after the
following instructions are executed will become
XRA A
MVI B, F0 H
SUB B
(A) 01 H (B) 0F H
(C) F0 H (D) 10 H
MCQ 8.29 An ideal op-amp circuit and its input wave form as shown in the figures. The
output waveform of this circuit will be
MCQ 8.30 The equivalent circuits of a diode, during forward biased and reverse biased
conditions, are shown in the figure.
(I)
(II)
If such a diode is used in clipper circuit of figure given above, the output
voltage V0 of the circuit will be
MCQ 8.31 Two perfectly matched silicon transistor are connected as shown in the
figure assuming the β of the transistors to be very high and the forward
voltage drop in diodes to be 0.7 V, the value of current I is
MCQ 8.32 In the voltage doubler circuit shown in the figure, the switch ‘S ’ is closed at
t = 0. Assuming diodes D1 and D2 to be ideal, load resistance to be infinite
and initial capacitor voltages to be zero. The steady state voltage across
capacitor C1 and C2 will be
MCQ 8.33 The block diagrams of two of half wave rectifiers are shown in the figure.
The transfer characteristics of the rectifiers are also shown within the block.
It is desired to make full wave rectifier using above two half-wave rectifiers.
The resultants circuit will be
MCQ 8.34 A waveform generator circuit using OPAMPs is shown in the figure. It
produces a triangular wave at point ‘P’ with a peak to peak voltage of 5 V
for Vi = 0 V.
If the voltage Vi is made +2.5 V, the voltage waveform at point ‘P’ will
become
MCQ 8.36 The output of the filter in Q.21 is given to the circuit in figure :
The gain v/s frequency characteristic of the output (vo) will be
MCQ 8.37 A 3-line to 8-line decoder, with active low outputs, is used to implement a
3-variable Boolean function as shown in the figure
MCQ 8.38 The content of some of the memory location in an 8085 accumulator based
system are given below
Address Content
g g
26FE 00
26FF 01
2700 02
2701 03
2702 04
g g
The content of stack (SP), program counter (PC) and (H,L) are 2700 H,
2100 H and 0000 H respectively. When the following sequence of instruction
are executed.
2100 H: DAD SP
2101 H: PCHL
the content of (SP) and (PC) at the end of execution will be
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MCQ 8.39 The common emitter forward current gain of the transistor shown is βF = 100
MCQ 8.43 The input signal Vin shown in the figure is a 1 kHz square wave voltage that
alternates between +7 V and −7 V with a 50% duty cycle. Both transistor
have the same current gain which is large. The circuit delivers power to the
load resistor RL . What is the efficiency of this circuit for the given input ?
choose the closest answer.
MCQ 8.44 The switch S in the circuit of the figure is initially closed, it is opened at
time t = 0. You may neglect the zener diode forward voltage drops. What is
the behavior of vout for t > 0 ?
MCQ 8.47 What are the states of the three ideal diodes of the circuit shown in figure ?
MCQ 8.48 For a given sinusoidal input voltage, the voltage waveform at point P of the
clamper circuit shown in figure will be
MCQ 8.49 Assuming the diodes D1 and D2 of the circuit shown in figure to be ideal
ones, the transfer characteristics of the circuit will be
MCQ 8.50 Consider the circuit shown in figure. If the β of the transistor is 30 and ICBO
is 20 mA and the input voltage is +5 V, the transistor would be operating in
MCQ 8.51 A relaxation oscillator is made using OPAMP as shown in figure. The supply
voltages of the OPAMP are !12 V. The voltage waveform at point P will be
MCQ 8.52 A TTL NOT gate circuit is shown in figure. Assuming VBE = 0.7 V of both
the transistors, if Vi = 3.0 V, then the states of the two transistors will be
MCQ 8.53 A student has made a 3-bit binary down counter and connected to the R-2R
ladder type DAC, [Gain = (− 1 kΩ/2R)] as shown in figure to generate a
staircase waveform. The output achieved is different as shown in figure.
What could be the possible cause of this error ?
MCQ 8.57 Assume that D1 and D2 in figure are ideal diodes. The value of current is
MCQ 8.58 The 8085 assembly language instruction that stores the content of H and L
register into the memory locations 2050H and 2051H, respectively is
(A) SPHL 2050H (B) SPHL 2051H
(C) SHLD 2050H (D) STAX 2050H
MCQ 8.59 Assume that the N-channel MOSFET shown in the figure is ideal, and that
its threshold voltage is +1.0 V the voltage Vab between nodes a and b is
(A) 5 V (B) 2 V
(C) 1 V (D) 0 V
MCQ 8.61 The common emitter amplifier shown in the figure is biased using a 1 mA
ideal current source. The approximate base current value is
(A) 0 μA (B) 10 μA
(C) 100 μA (D) 1000 μA
MCQ 8.62 Consider the inverting amplifier, using an ideal operational amplifier shown
in the figure. The designer wishes to realize the input resistance seen by the
small-signal source to be as large as possible, while keeping the voltage gain
between −10 and −25. The upper limit on RF is 1 MΩ. The value of R1
should be
MCQ 8.63 The typical frequency response of a two-stage direct coupled voltage amplifier
is as shown in figure
MCQ 8.64 In the given figure, if the input is a sinusoidal signal, the output will appear
as shown
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MCQ 8.65 Select the circuit which will produce the given output Q for the input signals
X1 and X2 given in the figure
MCQ 8.66 If X1 and X2 are the inputs to the circuit shown in the figure, the output Q
is
(A) X1 + X2 (B) X1 : X2
(C) X1 : X2
(D) X1 : X2
MCQ 8.67 In the figure, as long as X1 = 1 and X2 = 1, the output Q remains
(A) at 1 (B) at 0
(C) at its initial value (D) unstable
Data for Q. 68 and Q. 69 are given below. Solve the problems and
choose the correct option.
Assume that the threshold voltage of the N-channel MOSFET shown in
figure is + 0.75 V. The output characteristics of the MOSFET are also
shown
MCQ 8.71 Two perfectly matched silicon transistor are connected as shown in figure.
The value of the current I is
MCQ 8.72 The feedback used in the circuit shown in figure can be classified as
MCQ 8.73 The digital circuit using two inverters shown in figure will act as
MCQ 8.74 The voltage comparator shown in figure can be used in the analog-to-digital
conversion as
MCQ 8.75 Assuming that the diodes are ideal in figure, the current in diode D1 is
(A) 9 mA (B) 5 mA
(C) 0 mA (D) − 3 mA
MCQ 8.76 The trans-conductance gm of the transistor shown in figure is 10 mS. The
value of the input resistance Rin is
MCQ 8.77 The value of R for which the PMOS transistor in figure will be biased in
linear region is
MCQ 8.78 In the active filter circuit shown in figure, if Q = 1, a pair of poles will be
realized with ω0 equal to
MCQ 8.79 The input resistance Rin = vx /ix of the circuit in figure is
MCQ 8.82 The digital circuit shown in figure generates a modified clock pulse at the
output. Choose the correct output waveform from the options given below.
MCQ 8.84 In the Schmitt trigger circuit shown in figure, if VCE(sat) = 0.1 V, the output
logic low level (VOL) is
MCQ 8.85 The variation of drain current with gate-to-source voltage (ID − VGS
characteristic) of a MOSFET is shown in figure. The MOSFET is
MCQ 8.86 In the circuit of figure, assume that the transistor has hfe = 99 and VBE = 0.7
V. The value of collector current IC of the transistor is approximately
MCQ 8.87 For the circuit of figure with an ideal operational amplifier, the maximum
phase shift of the output vout with reference to the input vin is
MCQ 8.89 When a program is being executed in an 8085 microprocessor, its Program
Counter contains
(A) the number of instructions in the current program that have already
been executed
(B) the total number of instructions in the program being executed.
(C) the memory address of the instruction that is being currently executed
(D) the memory address of the instruction that is to be executed next
MCQ 8.90 For the n-channel enhancement MOSFET shown in figure, the threshold
voltage Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the
drain resistance RD is 1 kΩ.If the value of RD is increased to 4 kΩ, drain
current ID will become
MCQ 8.91 Assuming the operational amplifier to be ideal, the gain vout /vin for the
circuit shown in figure is
MCQ 8.92 A voltage signal 10 sin ωt is applied to the circuit with ideal diodes, as shown
in figure, The maximum, and minimum values of the output waveform Vout
of the circuit are respectively
MCQ 8.93 The circuit of figure shows a 555 Timer IC connected as an astable multi-
vibrator. The value of the capacitor C is 10 nF. The values of the resistors
RA and RB for a frequency of 10 kHz and a duty cycle of 0.75 for the output
voltage waveform are
MCQ 8.94 The boolean expression X Y Z + XYZ + XYZ + XYZ + XYZ can be
simplified to
(A) XZ + XZ + YZ (B) XY + YZ + YZ
(C) XY + YZ + XZ (D) XY + YZ + XZ
MCQ 8.95 The shift register shown in figure is initially loaded with the bit pattern
1010. Subsequently the shift register is clocked, and with each clock pulse
the pattern gets shifted by one bit position to the right. With each shift, the
bit at the serial input is pushed to the left most position (msb). After how
many clock pulses will the content of the shift register become 1010 again ?
(A) 3 (B) 7
(C) 11 (D) 15
(A) J = X, K = Y (B) J = X, K = Y
(C) J = Y, K = X (D) J = Y , K = X
MCQ 8.97 A memory system has a total of 8 memory chips each with 12 address lines
and 4 data lines, The total size of the memory system is
(A) 16 kbytes (B) 32 kbytes
(C) 48 kbytes (D) 64 kbytes
MCQ 8.98 The following program is written for an 8085 microprocessor to add two
bytes located at memory addresses 1FFE and 1FFF
LXI H, 1FFE
MOV B, M
INR L
MOV A, M
ADD B
INR L
MOV M, A
XOR A
On completion of the execution of the program, the result of addition is
found
(A) in the register A (B) at the memory address 1000
(C) at the memory address 1F00 (D) at the memory address 2000
MCQ 8.99 The frequency of the clock signal applied to the rising edge triggered D-flip-
flop shown in Figure is 10 kHz. The frequency of the signal available at Q is.
MCQ 8.100 The forward resistance of the diode shown in Figure is 5 Ω and the remaining
parameters are same at those of an ideal diode. The dc component of the
source current is
(A) Vm (B) Vm
50π 50π 2
V
(C) m
(D) 2Vm
100π 2 50π
MCQ 8.101 The cut-in voltage of both zener diode DZ and diode D shown in Figure
is 0.7 V, while break-down voltage of DZ is 3.3 V and reverse break-down
voltage of D is 50 V. The other parameters can be assumed to be the same
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as those of an ideal diode. The values of the peak output voltage (Vo) are
(A) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.
(B) 4 V in the positive half cycle and 5 V in the negative half cycle.
(C) 3.3 V in both positive and negative half cycles.
(D) 4 V in both positive and negative half cycle
MCQ 8.102 The logic circuit used to generate the active low chip select (CS ) by an 8085
microprocessor to address a peripheral is shown in Figure. The peripheral
will respond to addresses in the range.
MCQ 8.103 A first order, low pass filter is given with R = 50 Ω and C = 5 μF. What is
the frequency at which the gain of the voltage transfer function of the filter
is 0.25 ?
(A) 4.92 kHz (B) 0.49 kHz
(C) 2.46 kHz (D) 24.6 kHz
MCQ 8.104 The output voltage (vo) of the Schmitt trigger shown in Figure swings
between + 15 V and −15 V. Assume that the operational amplifier is ideal.
The output will change from +15 V to − 15 V when the instantaneous value
of the input sine wave is
MCQ 8.105 For the circuit shown in Figure, the boolean expression for the output Y in
terms of inputs P, Q, R and S is
(A) P + Q + R + S (B) P + Q + R + S
(C) (P + Q)(R + S ) (D) (P + Q)(R + S)
Vy
MCQ 8.109 The transfer function of the first network is
Vx
jωCR jωCR
(A) (B)
(1 − ω R2 C 2) + j3ωCR
2
(1 − ω R2 C 2) + j2ωCR
2
jωCR jωCR
(C) (D)
1 + j3ωCR 1 + j2ωCR
MCQ 8.110 The frequency of oscillation will be
1 (B) 1
(A)
RC 2RC
1 (D) None of these
(C)
4RC
MCQ 8.111 Value of RF is
(A) 1 kΩ (B) 4 kΩ
(C) 2 kΩ (D) 8 kΩ
MCQ 8.112 *The ripple counter shown in figure is made up of negative edge triggered J-
K flip-flops. The signal levels at J and K inputs of all the flip flops are
maintained at logic 1. Assume all the outputs are cleared just prior to
applying the clock signal.
module no. of the counter is:
(A) 7 (B) 5
(C) 4 (D) 8
MCQ 8.113 *In Figure , the ideal switch S is switched on and off with a switching
frequency f = 10 kHz. The switching time period is T = tON + tOFF μs.
The circuit is operated in steady state at the boundary of continuous and
discontinuous conduction, so that the inductor current i is as shown in
Figure. Values of the on-time tON of the switch and peak current ip . are
that the capacitance C has a finite value which is large enough so that the
voltage. VC has negligible ripple, calculate the following under steady state
conditions, in terms of D , I and R
MCQ 8.114 The voltage Vc, with the polarity shown in Figure,
(A) I (B) I (1 − DT)
C C
(C) I (1 − D) T (D) − I T
C C
MCQ 8.115 The average output voltage V0, with the polarity shown in figure
(A) − I T (B) − I D2 T
C 2C
(C) I (1 − DT) (D) I (1 − D) T
2C 2C
MCQ 8.116 In the single-stage transistor amplifier circuit shown in Figure, the capacitor
CE is removed. Then, the ac small-signal mid-band voltage gain of the
amplifier
MCQ 8.117 Among the following four, the slowest ADC (analog-to-digital converter) is
(A) parallel-comparator (i.e. flash) type
(B) successive approximation type
(C) integrating type
(D) counting type
MCQ 8.118 The output of a logic gate is “1” when all its inputs are at logic “0”. The
gate is either
(A) a NAND or an EX-OR gate
(B) a NOR or an EX-OR gate
(C) an AND or an EX-NOR gate
(D) a NOR or an EX-NOR gate
(A) xy + x (B) x + y
(C) x + y (D) xy + x
MCQ 8.120 An op-amp has an open-loop gain of 105 and an open-loop upper cut-off
frequency of 10 Hz. If this op-amp is connected as an amplifier with a closed-
loop gain of 100, then the new upper cut-off frequency is
(A) 10 Hz (B) 100 Hz
(C) 10 kHz (D) 100 kHz
MCQ 8.121 For the oscillator circuit shown in Figure, the expression for the time period
of oscillation can be given by (where τ = RC )
(A) τ ln 3 (B) 2τ ln 3
(C) τ ln 2 (D) 2τ ln 2
MCQ 8.122 An Intel 8085 processor is executing the program given below.
MVI A, 10 H
MVI B, 10 H
BACK: NOP
ADD B
RLC
INC BACK
HLT
The number of times that the operation NOP will be executed is equal to
(A) 1 (B) 2
(C) 3 (D) 4
MCQ 8.123 A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is
used at the input of an ADC (analog-to-digital converter). The conversion
time of the ADC is 1 μ sec, and during this time, the capacitor should not
loose more than 0.5% of the charge put across it during the sampling time.
The maximum value of the input signal to the S/H circuit is 5 V. The
leakage current of the S/H circuit should be less than
(A) 2.5 mA (B) 0.25 mA
(C) 25.0 μA (D) 2.5 μA
MCQ 8.124 An op-amp, having a slew rate of 62.8 V/μ sec, is connected in a voltage
follower configuration. If the maximum amplitude of the input sinusoidal is
10 V, then the minimum frequency at which the slew rate limited distortion
would set in at the output is
(A) 1.0 MHz (B) 6.28 MHz
(C) 10.0 MHz (D) 62.8 MHz
MCQ 8.125 An n-channel JFET, having a pinch off voltage (Vp ) of −5 V, shows a
transconductance (gm) of 1 mA/V when the applied gate -to-source voltage
(VGS ) is −3 V. Its maximum transconductance (in mA/V) is
(A) 1.5 (B) 2.0
(C) 2.5 (D) 3.0
MCQ 8.126 *The circuit shown in the figure is a MOD-N ring counter. Value of N is
(A) 4 (B) 15
(C) 7 (D) 6
MCQ 8.127 *For the op-amp circuit shown in Figure, determine the output voltage vo .
Assume that the op-amps are ideal.
(A) − 8 V (B) − 20 V
7 7
(C) −10 V (D) None of these
MCQ 8.129 What is the required value of CE for the circuit to have a lower cut-off
frequency of 10 Hz
(A) 0.15 mF (B) 1.59 mF
(C) 5 μF (D) 10 μF
MCQ 8.131 If the above filter has a 3 dB frequency of 1 kHz, a high frequency input
resistance of 100 kΩ and a high frequency gain of magnitude 10. Then
values of R1, R2 and C respectively are :-
(A) 100 kΩ, 1000 kΩ, 15.9 nF
(B) 10 kΩ, 100 kΩ, 0.11 μF
(C) 100 kΩ, 1000 kΩ, 15.9 nF
(D) none of these
************
SOLUTION
F = XY + XY
1pr44 2 44 3
ime implicants
Y = 1, when A > B
A = a1a0, B = b1b0
a1 a0 b1 b0 Y
0 1 0 0 1
1 0 0 0 1
1 0 0 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
Total combination = 6
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VC − 100IB − 0.7 = 0
VC = 100IB + 0.7 ...(i)
IC - IE = 13.7 − VC = (β + 1) IB
12k
13.7 − VC = 100I ...(ii)
B
12 # 103
Solving equation (i) and (ii),
IB = 0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current source.
vi −5.1 # 10−4 − v0
=
Rs 428.72 v0 RF
vi =− 1.16 # 10−6 v0 − 1 # 10−5 v0 Rs = 10 kΩ (source resistance)
3
10 # 10
vi =− 1.116 # 10−5
3
10 # 10
Av = v 0 = 1
−5 - 8.96
vi 10 # 103 # 1.116 #
10
SOL 8.6 Option (D) is correct.
Let Qn + 1 is next state and Qn is the present state. From the given below
figure.
D = Y = AX0 + AX1
Qn + 1 = D = AX0 + AX1
Qn + 1 = A Qn + AQn X0 = Q, X1 = Q
If A = 0, Qn + 1 = Qn (toggle of previous state)
If A = 1, Qn + 1 = Qn
So state diagram is
0 − Vi (jω) 0 − Vo (jω)
1 + =0
+ R1 R2
jωC
Vo (jω) − Vi (jω)
R2 = 1
+ R1
jωC
Vi (jω) R2
Vo(jω) =−
R1 − j 1
ωC
1
At ω " 0 (Low frequencies), ωC" 3, so Vo = 0
1 " 0, so V (jω) =− R2 V (jω)
o i
At ω " 3 (higher frequencies),
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ωC R1
−R 2 R2
H (3) = R1 = R1
At 3 dB frequency, gain will be 2 times of maximum gain 6H (3)@
1
H^jω0h = H (3)
2
So, R2 = 1 b R2 l
R 12 + ω021C 2 2 R1
2R 2 = R 2 + 1 & R 2 = 1
1 1 1
ω02 C 2 ω 2C 2
ω0 = 1
R1C
Y = X 5X
= X X + XX
= XX + X X
= X+X = 1
= LP + 3 + DE
PUSH H & The last two value of the stack will be HL value i.e,
LP + DISP + 3
We can see that both BE and BC Junction are forwarded biased. So the
BJT is operating in saturation.
12 − 0.2 = 5.36 mA
Collector current IC =
2.2k
Y βIB
Note:- In saturation mode IC -
vo = 5 + 0.7 = 5.7 V
2 + (2 − vo) = 0
R 2R
4 + 2 − vo = 0
vo = 6 volt
10 − (10 # V0
3 − 0.7 − V0 = 0
103) 10 # 10
9.3 − 2V0 = 0
& V0 = 9.3 = 4.65 A
2
Output Y is written as
Y = X 5B
Since each gate has a propagation delay of 10 ns.
F = X Y + YZ
Feedback samples output voltage and adds a negative feedback voltage (vfb)
to input.
So, it is a voltage-voltage feedback.
SUB B & A = A − B
A =00000000
B = 1111 0 0 0 0
2’s complement of (− B) = 0 0 0 1 0 0 0 0
A + (− B) = A − B = 0 0 0 1 0 0 0 0
= 10 H
Now capacitor VC2 will charge upto −10 volt in opposite direction.
To get output V0
V0 = K(− VP + VQ) K − gain of op-amp
So, P should connected at inverting terminal of op-amp and Q with non-
inverting terminal.
Output, vo = vi
So it will pass high frequency signal.
This is a high pass filter.
F = XZ + YZ + XYZ
In POS form F = (Y + Z)(X + Z)(X + Y + Z )
Since all outputs are active low so each input in above expression is
complemented
F = (Y + Z )(X + Z )(X + Y + Z)
IC (sat) 5
IB(sat) = = .050 mA
β = 100
IB 1 IB(sat), so transistor is in forward active region.
v1 c R1 + R2 m = V
R1R2 R1
v1 = V c R2
R+ R m
1 2
c c c c
-t
vc (t) = 20 (1 − e ) RC
v+ − vout + v+ − 0 = 0
10 100
v+ = 10 vout
11
Due to zener diodes, −5 # vout #+ 5
So, v+ = 10 (5) V
11
Transistor form − 5 V to +5 V occurs when capacitor charges upto v+.
So 20 (1 − e-t/RC) = 10 # 5
11
1−e = 5
- t/RC
22
17 = e- t/RC
22
t = RC ln ` 22 j = 1 # 103 # .01 # 10-6 # = 2.57 μsec
17
0.257
Voltage waveforms in the circuit is shown below
Since there is no feed back to the op-amp and op-amp has a high open loop
gain so it goes in saturation. Input is applied at inverting terminal so.
VP =− VCC =− 12 V
In negative half cycle of input, diode D1 is in forward bias and equivalent
circuit is shown below.
Output VP = Vγ + V-
Op-amp is at virtual ground so V+ = V- = 0 and VP = Vγ = 0.7 V
Voltage wave form at point P is
Output, Vo = 10 volt
When Vi > 10 V (D1 is in forward bias and D2 is off
So the equivalent circuit is,
Output, Vo = Vi
Transfer characteristic of the circuit is
node equation
Vth + 12 + Vth − 0 = 0
2 10
5 Vth + 60 + Vth = 0
Vth =− 10 volt (negative threshold)
So the capacitor will discharge upto −10 volt.
At terminal P voltage waveform is.
Voltage Vn is given by
Vn = 1 # 2 = 2 Volt
Vp = 0
Vn > Vp (so diode is in reverse bias, assumption is true)
Current through D2 is ID2 = 0
Due to 10 V source VDS > VDS(sat) so the NMOS goes in saturation, channel
conductivity is high and a high current flows through drain to source and it
acts as a short circuit.
So, Vab = 0
(2 − 1) mA
= = 1 mS
(2 − 1) V
vo =− gm vgs RD
vgs = vin
So, vo =− gm RD vin
Voltage gain Av = vo =− gm RD =− (1 mS) (10 kΩ) =− 10
vi
In the circuit
V1 = 3.5 V (given)
Current in zener is.
IZ = V1 − VZ = 3.5 − 3.3 = 2 mA
RZ 0.1 # 103
SOL 8.71 Option (C) is correct.
This is a current mirror circuit. Since VBE is the same in both devices, and
transistors are perfectly matched, then
IB1 = IB2 and IC1 = IC2
From the circuit we have,
Here the feedback circuit samples the output voltage and produces a feed
back current Ifb which is in shunt with input signal. So this is a shunt-shunt
feedback configuration.
V
n
Vp < Vn (so the assumption is true and D1 is in reverse bias) and current in
D1
ID1 = 0 mA
gm = 10 ms
50 = 5 kΩ
a gm rπ = β & rπ =
Input resistance 10 # 10-3
Rin = RB < rπ = 5 kΩ < 5 kΩ = 2.5 kΩ
11vx = vy ...(2)
For equation (1) & (2)
ix = vx − 11vx =− 10vx
1 # 106 106
Input impedance of the circuit.
6
Rin = vx =−10 =− 100 kΩ
ix 10
times.
HALT " 1-instruction cycle.
IC = hfe IB
= 99 # 3.3 mA = 3.3 mA
[0.33 + 3.3] # 100 0.33 + 3.3
Similarly,
v+ − vin + v+ − 0 = 0
R 1
c jωC m
v+ − vin + v+(jωCR) = 0
v+(1 + jωCR) = Vin ..(2)
By equation (1) & (2)
2vin
= vin + vout "a v+ = v- (ideal op-amp)
1 + jωCR
vin ; 2 − 1E = vout
1 + jωCR
(1 − jωCR)
vout = vin
1 + jωCR
Phase shift in output is given by
θ = tan-1(− ωCR) − tan-1(ωCR)
= π − tan-1(ωCR) − tan-1(ωCR)
= π − 2 tan-1(ωCR)
Maximum phase shift θ =π
Vout = + 4 Volt
In the negative half cycle diode D1 conducts and D2 will be off so the circuit
is,
Applying KVL
Vin − 10I + 4 − 10I = 0
Vin + 4 = I
20
Vin =− 10 V (Maximum value in negative half cycle)
So, I = −10 + 4 =− 3 mA
20 10
Vin − Vout = I
10
−10 − Vout
=− 3
10 10
Vout =− (10 − 3)
Vout =− 7 volt
= YZ + Y(X + X )(X + Z )
= YZ + Y (X + Z )
= YZ + YX + YZ
X = X1 5 X0 , Y = X 2
Serial Input Z = X 5 Y = [X1 5 X0] 5 X2
Truth table for the circuit can be obtain as.
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 0 0
Output Vo = VD + Vz
= 0.7 + 3.3
= 4 Volt
In the negative halt cycle, zener diode (Dz) is in forward bias and diode (D)
Transfer function
V (jω)
H (jω) = 0 = 1 # 1 = 1
V1(jω) R+ 1 jωC jωcR +1
jωC
Given that H (jω1) = 0.25
1 =1
ω2C 2 R2 + 1
1
4
16 = ω12R2C2 + 1
ω12R2C2 = 15
4π2f1 2(50)2(5 # 10-6)2 = 15
In the circuit
VBE = 0.7 V
VE = IE # 1 kΩ = 1V
VB − VE = 0.7
VB = 0.7 + 1 = 1.7 volt
Current throughR1
IR = VB = 1.7 = 100 μA
1
17 kΩ 17 kΩ
I
IB = = 1 mA
E
= 10 μA
β+1 (99 + 1)
Current through RF , by writing KCL at Base
IRF = IB + IR1
= 10 + 100 = 110 μA
Current through RC
I1 = IC + IRF = 0.99 mA + 110 μA = 1.1 mA
Va − Vx + V Cs + (V − V ) Cs = 0
a a y
R
or Va (1 + 2RCs) − Vx − sCRVy = 0 ...(1)
Vy
or (Vy − Va) Cs +
=0
R
or Vy (1 + sCR) − Va sCR = 0 ...(2)
From equation (1) & (2)
1 + sCR
c sCR m (1 + 2sCR) Vy − Vx − sCRVy = 0
(1 + sCR)(1 + 2sCR)
Vy ; − sCR E = Vx
sCR
(1 + 3sCR + 2s2C2R2 − s2C2R2)
Vy = Vx
sCR
Transfer function
Vy
T (s) = = sCR
Vx 1 + 3sCR + s2C2R2
jωCR jωCR
T (jω) = =
1 + j3ωCR − C2R2ω2 (1 − C2R2ω2) + 3jωCR
ω0 = 1
RC
ω= 1
RC
Vy
So, = j =1
V0 3j 3
R =1
RF + R 3
RF = 2R = 2 # 1 = 2 kΩ
GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
Published by: NODIA and COMPANY ISBN: 9788192276243
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I = C dVdt
c
& I t + V (0)
Vc = C c
Initially Vc (0) = 0
Vc = I t
C
At t = Toff
Vc = I Toff
C
Duty cycle D = T TON = TON
ON + TOFF T
TON = DT
TOFF = T − TON = T − DT
So, Vc = I (T − DT)
C
= I (1 − D) T
C
During TOFF , output voltage V0 = 0 volt.
I2 = C I a dVc = I
C dt C
V0 =− Vc = −I C t
Average output voltage
V0 = 1 ; # I
DT = T TOFF
b−C t l dt + #0 0 dtE
ON
T 0
2 DT 2
=− 1 . I :t D =− 1 .I . D T =− I D .T
2 2
TC 2 0 TC 2 C 2
o
In the circuit
i = vs
hie
b = hfe ib .RC = hfe . vs .RC
hie
v
GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
Published by: NODIA and COMPANY ISBN: 9788192276243
Visit us at: www.nodia.co.in
www.gatehelp.com
.
.
.
(
1
)
In the circuit
vs = ib hie + (ib + hfe ib) RE
vs = ib [hie + (1 + hfe) RE] ...(2)
v0 = hfe ib .RC ...(3)
from equation (2) and (3)
vs
v0 = hfe .RC
hie + (1 + hfe) RE
v hfe RC
Voltage gain, Av = =
2
0
vs hie + (1 + hfe) RE
So Av1 = hie + (1 + hfe) RE = 1 + (1 + hfe) RE
Av2 hie hie
Av < Av
2 1
β = v+ = 1
vo 2
J1 + 1 N
K 2O
So, T = 2τ ln K1 − 1 O = 2τ ln 3
L 2P
BACK : NOP
ADDB & Adds contents of register B to accumulator and result stores in
accumulator
A = A + B = (10)H + (10)H
000 10000
ADD 0 0 0 1 0 0 0 0
A= 0 0100 0 0 0
= (20)H
RLC & Rotate accumulator left without carry
A = (A0)H
JNC BACK
NOP
ADDB & A = A + B
= (A0)H + (10)H
1 0 1 0 0 0 00
ADD 0 0 0 1 0 0 0 0
A= 10110 0 0 0
A = (B0)H
CY = 1 So it goes to HLT.
therefore NOP will be executed 3 times.
CLK Q3 Q2 Q1 Q0
Initial state 1 1 1 0
1 0 1 1 1
2 0 0 1 1
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 0
From the truth table we can see that counter states at N = 4 and N = 8 are
same. So mod number is 4.
4v1 − vo = 0 ...(2)
At the negative terminals of op-amp-2
−1 − v2 + − 1 − vo = 0
c 4 m c8 m
−2 − 2v2 − 1 − vo = 0
vo + 2v2 =− 3 ...(3)
From equation (1) and (2)
3 vo − 2v2 = 1
4
From equation (3)
3 vo − 2 (− 3 − vo) = 1
4
3 vo + vo
=− 5
4
7 vo =− 5
4
vo =− 20 volt
7
− 200 # (1 kΩ)
So gain Av = =− 6.62
(25 kΩ + 5.2 kΩ)
f0 = 1
2πReq CE
Req " Equivalent resistance seen through capacitor CE
RE (RB + rπ)
Req = RE < RB + rπ =
RE + RB + rπ
1(RE + RB + rπ)
So f0 = = 10 Hz (given)
2πRE (RB + rπ) CE
(0.1 + 25 + 5.2) # 103
So, CE = = 1.59 mF
2π # 0.1(25 + 5.2) # 106
vo =− R2 vi
R1
SOL 8.131 At high frequency ω " 3 & 1 " 0, capacitor behaves as short circuit
ωc
and gain of the filter is given as
Av = − R2 = 10
R
1
R2 = 10 R1
Input resistance of the circuit Rin = R1 = 100 kΩ
So, R2 = 10 # 100 kΩ = 1 MΩ
Transfer function of the circuit
= −jωR2C
Vo(jω)
Vi(jω) 1 + jω R1C
High frequency gain Av3 = 10
At cutoff frequency gain is
− jωc R2 C
Av = 10 =
2 1 + jωc R1 C
10 = ωc R22C 2 2
2 1 + ωc R1 C
100 + 100ω2 R 2 C2 = 2ω2 R 2 C2
c 1 c 2
100 + 100 # ω2 # 1010 # C2 = 2 # ω2 # 1012 # C2
c c
100 = ω C # 1012
c
2 2
C2 = 2 100 12
ω 10
C = c #1 4 =
1
2πf 10 2 3.14 103 104
c# # # #
= 15.92 nF
***********