Gfk2222y Rx3i Rx7i Cpu Ref Manual

GE
Automation & Controls

Programmable Control Products
RX7i & RX3i CPU Reference Manual

GFK-2222Y
PACSystems*
RX7i & RX3i
CPU Reference Manual
GFK-2222Y
December 2016
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Table of Contents
RX7i & RX3i CPU Reference Manual GFK-2222Y
Table of Contents................................................................................................................................................ i
Table of Figures.................................................................................................................................................vi
Chapter 1 Introduction............................................................................................................................ 1
1.1 Revisions in this Manual ............................................................................................................. 2
1.2 PACSystems Control System Overview .................................................................................... 4

1.2.1 Programming and Configuration ................................................................................................................................... 4
1.2.2 Process Systems ...................................................................................................................................................................... 4
1.2.3 PACSystems CPU Model ...................................................................................................................................................... 5
1.3 RX3i Overview ............................................................................................................................... 6
1.4 RX7i Overview ............................................................................................................................... 9
1.5 Migrating Series 90 Applications to PACSystems ................................................................ 10
1.6 Documentation........................................................................................................................... 11
Chapter 2 CPU Features & Specifications .......................................................................................... 13
2.1 Common CPU Features ............................................................................................................. 14

2.1.1 Features Shared by All PACSystems CPU Models ................................................................................................14
2.1.2 Features Shared by Certain PACSystems CPU Models .....................................................................................14
2.1.3 Firmware Storage in Flash Memory ............................................................................................................................15
2.1.4 Operation, Protection, and Module Status ..............................................................................................................15
2.1.5 Ethernet Global Data...........................................................................................................................................................15
2.1.6 Embedded PROFINET Controller ...................................................................................................................................16
2.1.7 OPC UA........................................................................................................................................................................................17
2.1.8 Removable Data Storage Devices (RDSDs) .............................................................................................................17
2.2 RX3i CPU Features and Specifications ................................................................................... 23

2.2.1 CPE400........................................................................................................................................................................................29
2.2.2 CPE330........................................................................................................................................................................................47
2.2.3 CPE305 and CPE310 ............................................................................................................................................................55
2.2.4 CPU315 and CPU320/CRU320 .......................................................................................................................................64
2.2.5 CPU310 .......................................................................................................................................................................................67
2.3 RX7i CPU Features and Specifications ................................................................................... 69

2.3.1 CPE030/CRE030 and CPE040/CRE040 .......................................................................................................................73
GFK-2222Y December 2016 i

Contents
2.3.2 CPE010, CPE020 and CRE020 .........................................................................................................................................75

2.3.3 RX7i Embedded Ethernet Interface .............................................................................................................................77
Chapter 3 CPU Configuration............................................................................................................... 83
3.1 Configuring the CPU .................................................................................................................. 84
3.2 Configuration Parameters........................................................................................................ 85

3.2.1 Settings Parameters ............................................................................................................................................................85
3.2.2 Modbus TCP Address Map................................................................................................................................................87
3.2.3 Scan Parameters ...................................................................................................................................................................88
3.2.4 Memory Parameters ...........................................................................................................................................................91
3.2.5 Fault Parameters...................................................................................................................................................................93
3.2.6 Redundancy Parameters (Redundancy CPUs Only) ...........................................................................................96
3.2.7 Transfer List .............................................................................................................................................................................96
3.2.8 COM1 and COM2 Parameters ........................................................................................................................................96
3.2.9 Scan Sets Parameters ..................................................................................................................................................... 100
3.2.10 Power Consumption Parameters .............................................................................................................................. 100
3.2.11 Access Control ..................................................................................................................................................................... 101
3.3 Storing (Downloading) Hardware Configuration ............................................................... 102
3.4 Configuring the Embedded Ethernet Interface .................................................................. 103

3.4.1 Establishing Initial Ethernet Communications.................................................................................................... 104
3.4.2 Setting a Temporary IP Address ................................................................................................................................. 105
Chapter 4 CPU Operation ................................................................................................................... 107
4.1 CPU Sweep ................................................................................................................................. 108

4.1.1 Parts of the CPU Sweep .................................................................................................................................................. 109
4.1.2 CPU Sweep Modes............................................................................................................................................................. 112
4.2 Program Scheduling Modes ................................................................................................... 115
4.3 Window Modes ......................................................................................................................... 115
4.4 Data Coherency in Communications Windows.................................................................. 115
4.5 Run/Stop Operations ............................................................................................................... 116

4.5.1 CPU STOP Modes ................................................................................................................................................................ 117
4.5.2 STOP-to-RUN Mode Transition .................................................................................................................................... 119
4.5.3 RUN/STOP Switch Operation ....................................................................................................................................... 119
4.6 Flash Memory Operation ........................................................................................................ 120
4.7 Logic/Configuration Source and CPU Operating Mode at Power-Up ............................ 121
4.7.1 CPU Mode when Memory Not Preserved/Power-up Source is Flash ..................................................... 122
4.7.2 CPU Mode when Memory Preserved ....................................................................................................................... 122
ii PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

Contents
4.8 Clocks and Timers .................................................................................................................... 123

4.8.1 Elapsed Time Clock ........................................................................................................................................................... 123
4.8.2 Time-of-Day Clock ............................................................................................................................................................. 123
4.8.3 Watchdog Timer ................................................................................................................................................................. 124
4.9 System Security ........................................................................................................................ 126

4.9.1 Passwords and Privilege Levels - Legacy Mode ................................................................................................ 126
4.9.2 OEM Protection – Legacy Mode ................................................................................................................................. 128
4.9.3 Enhanced Security for Passwords and OEM Protection ................................................................................ 129
4.9.4 Legacy/Enhanced Security Comparison ............................................................................................................... 130
4.10 PACSystems I/O System .......................................................................................................... 131

4.10.1 I/O Configuration................................................................................................................................................................ 132
4.10.2 Genius I/O .............................................................................................................................................................................. 134
4.10.3 I/O System Diagnostic Data Collection .................................................................................................................. 136
4.11 Power-Up and Power-Down Sequences .............................................................................. 138

4.11.1 Power-Up Sequence......................................................................................................................................................... 138
4.11.2 Power-Down Sequence .................................................................................................................................................. 140
4.11.3 Power Cycle Operation with an Energy Pack ...................................................................................................... 140
4.11.4 Retention of Data Memory Across Power Failure ............................................................................................. 143
Chapter 5 Communications ............................................................................................................... 145
5.1 Ethernet Communications ..................................................................................................... 146

5.1.1 Embedded Ethernet Interface ..................................................................................................................................... 146
5.1.2 Ethernet Interface Modules .......................................................................................................................................... 150
5.2 Serial Communications ........................................................................................................... 151

5.2.1 Serial Port Communications Capabilities .............................................................................................................. 151
5.2.2 Configurable STOP Mode Protocols ......................................................................................................................... 152
5.2.3 Serial Port Pin Assignments .......................................................................................................................................... 152
5.2.4 Serial Port Electrical Isolation ...................................................................................................................................... 157
5.2.5 Serial Cable Lengths and Shielding .......................................................................................................................... 158
5.2.6 Serial Port Baud Rates ..................................................................................................................................................... 159
5.3 Series 90-70 Communications and Intelligent Option Modules ...................................... 160
5.3.1 Communications Coprocessor Module (CMM) ................................................................................................... 160
5.3.2 Programmable Coprocessor Module (PCM) ......................................................................................................... 161
5.3.3 DLAN/DLAN+ (Drives Local Area Network) Interface ...................................................................................... 162
Chapter 6 Serial I/O, SNP & RTU Protocols ...................................................................................... 163
6.1 Configuring Serial Ports Using COMMREQ Function 65520 ............................................. 164
6.1.1 COMMREQ Function Example ..................................................................................................................................... 164
6.1.2 Timing....................................................................................................................................................................................... 164
6.1.3 Sending Another COMMREQ to the Same Port .................................................................................................. 164
GFK-2222Y December 2016 iii

Contents
6.1.4 Invalid Port Configuration Combinations .............................................................................................................. 165

6.1.5 COMMREQ Command Block Parameter Values ................................................................................................ 165
6.1.6 Example COMMREQ Command Blocks for Serial Port Setup function .................................................. 166
6.2 Serial I/O Protocol .................................................................................................................... 169

6.2.1 Calling Serial I/O COMMREQs from the CPU Sweep ........................................................................................ 169
6.2.2 Compatibility ........................................................................................................................................................................ 169
6.2.3 Status Word for Serial I/O COMMREQs ................................................................................................................... 169
6.2.4 Serial I/O COMMREQ Commands .............................................................................................................................. 171
6.2.5 Overlapping COMMREQs ................................................................................................................................................ 172
6.2.6 Initialize Port Function (4300) ...................................................................................................................................... 173
6.2.7 Set Up Input Buffer Function (4301) ......................................................................................................................... 174
6.2.8 Flush Input Buffer Function (4302) ............................................................................................................................ 175
6.2.9 Read Port Status Function (4303) .............................................................................................................................. 176
6.2.10 Write Port Control Function (4304) ........................................................................................................................... 178
6.2.11 Cancel COMMREQ Function (4399) ........................................................................................................................... 179
6.2.12 Autodial Function (4400) ................................................................................................................................................ 180
6.2.13 Write Bytes Function (4401) ......................................................................................................................................... 182
6.2.14 Read Bytes Function (4402) .......................................................................................................................................... 183
6.2.15 Read String Function (4403) ......................................................................................................................................... 185
6.3 RTU Slave Protocol ................................................................................................................... 187

6.3.1 Message Format................................................................................................................................................................. 188
6.3.2 Cyclic Redundancy Check (CRC) ................................................................................................................................. 193
6.3.3 RTU Message Descriptions ........................................................................................................................................... 197
6.3.4 RTU Scratch Pad ................................................................................................................................................................. 213
6.3.5 Communication Errors .................................................................................................................................................... 214
6.3.6 RTU Slave/SNP Slave Operation with Programmer Attached .................................................................... 217
6.4 SNP Slave Protocol ................................................................................................................... 218

6.4.1 Permanent Datagrams ................................................................................................................................................... 218
6.4.2 Communication Requests (COMMREQs) for SNP .............................................................................................. 218
Appendix A Performance Data ................................................................................................................... 219
A-1 Boolean Execution Times ..................................................................................................................... 220

A-1.1 Boolean Execution Measurements (ms per 1000 Boolean executions) ................................................ 220
A-2 Instruction Timing ................................................................................................................................. 221

A-2.1 Overview ................................................................................................................................................................................. 221
A-2.2 PLC Version Information................................................................................................................................................. 222
A-2.3 RX3i Instruction Times ..................................................................................................................................................... 223
A-2.4 RX7i Instruction Times ..................................................................................................................................................... 236
A-3 Overhead Sweep Impact Times .......................................................................................................... 247

A-3.1 Base Sweep Times ............................................................................................................................................................. 248
A-3.2 What the Sweep Impact Tables Contain ............................................................................................................... 250
iv PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

Contents
A-3.3 Programmer Sweep Impact Times ........................................................................................................................... 251

A-3.4 I/O Scan and I/O Fault Sweep Impact..................................................................................................................... 252
A-3.5 Ethernet Global Data Sweep Impact ....................................................................................................................... 259
A-3.6 EGD Sweep Impact for Embedded Ethernet Interface on RX3i CPE Models ...................................... 263
A-3.7 Sweep Impact of Intelligent Option Modules ...................................................................................................... 266
A-3.8 I/O Interrupt Performance and Sweep Impact .................................................................................................. 268
A-3.9 Timed Interrupt Performance ...................................................................................................................................... 271
A-3.10 Example of Predicted Sweep Time Calculation ................................................................................................ 272
Appendix B User Memory Allocation ......................................................................................................... 273
B-1 Items that Count Against User Memory ........................................................................................... 274
B-2 User Program Memory Usage ............................................................................................................. 275

B-2.1 %L and %P Program Memory ..................................................................................................................................... 275
B-2.2 Program Logic and Overhead ..................................................................................................................................... 275
GFK-2222Y December 2016 v

Contents
Table of Figures
Figure 1: Configuring an Embedded PROFINET Controller ___________________________________________ 16
Figure 2: CPE400 Front View and Features _______________________________________________________ 29
Figure 3: CPE400 Underside Ports & Connectors___________________________________________________ 32
Figure 4: CPE400 Micro-SD & USB Pinouts _______________________________________________________ 35
Figure 5: Typical Field Agent Application _________________________________________________________ 39
Figure 6: Display Port Connector _______________________________________________________________ 42
Figure 7: Location of RTC battery on CPE400 _____________________________________________________ 44
Figure 8: DIN-Rail Mount Bracket Assembly CPE400 ________________________________________________ 46
Figure 9: Panel-Mount Bracket Assembly CPE400__________________________________________________ 46
Figure 10: CPE330 Front View & Features ________________________________________________________ 47
Figure 11: CPE330 RUN/STOP Switch and RDSD Switches ___________________________________________ 49
Figure 12: Location and Orientation of Real-Time Clock Battery in CPE330 ______________________________ 52
Figure 13: IC695CPE305 Front View ____________________________________________________________ 55
Figure 14: IC695CPE310 Front View ____________________________________________________________ 55
Figure 15: External Features of CPE305 __________________________________________________________ 57
Figure 16: External Features of CPE310 __________________________________________________________ 57
Figure 17: Accessing Real-Time Clock Battery (CPE305 and CPE310) ___________________________________ 60
Figure 18: Sample Tool for Coin Battery Extraction _________________________________________________ 61
Figure 19: IC695CPU320 Front View ____________________________________________________________ 64
Figure 20: IC695CPU310 Front View ____________________________________________________________ 67
Figure 21: CPE040 Front View _________________________________________________________________ 73
Figure 22: CPE010 Front View _________________________________________________________________ 75
Figure 23: PME Expansion of PACSystems Target __________________________________________________ 84
Figure 24: Downloading Hardware Config to CPU ________________________________________________ 102
Figure 25: Selecting Embedded Ethernet for Configuration _________________________________________ 103
Figure 26: Set Temporary IP Address ___________________________________________________________ 105
Figure 27: Major Phases of a Typical CPU Sweep _________________________________________________ 109
Figure 28: Typical Sweeps in Normal Sweep Mode ________________________________________________ 112
Figure 29: Typical Sweeps in Constant Sweep Mode ______________________________________________ 113
Figure 30: Typical Sweeps in Constant Window Mode _____________________________________________ 114
Figure 31: CPU Sweep in Stop-I/O Disabled and Stop-I/O Enabled Modes ______________________________ 117
Figure 32: CPE330 Overlapping Local IP Subnet Example __________________________________________ 147
Figure 33: Expected Response Path ____________________________________________________________ 148
Figure 34: Actual Response Path ______________________________________________________________ 148
Figure 35: COM1 Port CPE400 ________________________________________________________________ 153
Figure 36: RTU Message Transactions __________________________________________________________ 188
Figure 37: RTU Read Output Table Example _____________________________________________________ 191
Figure 38: CRC Register Operation _____________________________________________________________ 193
Figure 39: RTU Read Output Table Message Format _______________________________________________ 197
Figure 40: RTU Read Input Table Message Format ________________________________________________ 198
Figure 41: RTU Read Registers Message Format __________________________________________________ 199
Figure 42: RTU Read Analog Inputs Message Format ______________________________________________ 200
Figure 43: RTU Force Single Output Message Format ______________________________________________ 201
Figure 44: RTU Preset Single Register Message Format ____________________________________________ 202
Figure 45: RTU Read Exception Status Message Format ____________________________________________ 203
Figure 46: RTU Loopback/Maintenance Message Format___________________________________________ 204
Figure 47: RTU Force Multiple Outputs Message Format ___________________________________________ 206
Figure 48: RTU Preset Multiple Registers Message Format __________________________________________ 207
Figure 49: RTU Report Device Type Message Format ______________________________________________ 208
Figure 50: RTU Read Scratch Pad Memory Message Format ________________________________________ 212
vi PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

Contents
Figure 51: RTU Error Response Format _________________________________________________________ 214

Figure 52: Interrupt Execution Considerations ___________________________________________________ 269
GFK-2222Y December 2016 vii

Chapter 1 Introduction
This manual contains general information about PACSystems CPU operation and product features.
Chapter 1 provides a general introduction to the PACSystems family of products, including new
features, product overviews, and a list of related documentation.
CPU Features & Specifications are provided in Chapter 2.
Installation procedures are described in the PACSystems RX7i Installation Manual, GFK-2223 and the
PACSystems RX3i System Manual, GFK-2314.
CPU Programming is covered in PACSystems RX7i and RX3i CPU Programmer’s Reference Manual,
GFK-2950. It provides an overview of program structure and describes the various languages which
may be used, their syntax and operation, and provides examples.
CPU Configuration is described in Chapter 3. Configuration using the proprietary Proficy Machine
Edition (PME) programming and configuration software package determines characteristics of CPU,
System and module operation. It also establishes the program references used by each module in
the system. For details on configuration of the embedded RX7i Ethernet interface as well as the rack-
based RX7i and RX3i Ethernet Interface modules, refer to PACSystems RX7i & RX3i TCP/IP Ethernet
Communications User Manual, GFK-2224.
CPU Operation is described in Chapter 4.
Ethernet Communications and Serial Communications are described in Chapter 5.
Serial I/O, SNP & RTU Protocols are described in Chapter 6.
Performance Data, including Instruction Timing is provided in Appendix A.
User Memory Allocation is described in Appendix B.
GFK-2222Y December 2016 1

Chapter 1. Introduction
1.1 Revisions in this Manual

Note: A given feature may not be implemented on all PACSystems CPUs. To determine whether a
feature is available on a given CPU model and firmware version, please refer to the Important
Product Information (IPI) document provided for the CPU version that you are using.
Rev Date Description
Y Dec-  Added section on CPE400 and incorporated into CPU comparison table (section 2.2). This
2016 section also introduces Field Agent and documents how to set up Embedded Field Agent
for the CPE400 (section 2.2.1.8).
 Added section 2.1.6, Embedded PROFINET Controller.
 Update of Energy Pack Section 4.11.3 to include ACC403 and compatibility matrix.
 Added compatibility mode information for CPE330 with CPU320 & CRU320
X Feb-  Corrected Ethernet Indicators CPE305 & CPE310 table
2016
W Aug-  Addition of support for Ethernet Global Data (Class 1) on CPE330
2015
V Jun-  Addition of RX3i CPE330 (new product) and related Ethernet considerations.
2015  Update of Energy Pack Section 4.11.3 to include ACC402 and compatibility matrix.
 Addition of HART® Pass Through feature (see page 7).
 Addition of CPU Comparison Charts (Section 2.2 and Section 2.3).
 Update of Communications Section (Chapter 5). Added Serial Port Electrical Isolation.
 Removed original Chapters 5-11 (chapters dealing with CPU programming) and Chapter
14 (Diagnostics). These are now in PACSystems RX7i and RX3i CPU Programmer’s
Reference Manual, GFK-2950 (Chapters 2-8 and Chapter 9 respectively).
U Nov-  New Appendix (A-3.6) EGD Sweep Impact for Embedded Ethernet Interface on RX3i
2014 CPE305 and CPE310.
T Oct-  Support for OPC UA using embedded Ethernet port in CPE305/CPE310 with CPU firmware
2014 8.20.
 Support for Ethernet Global Data (EGD Class 1) using embedded Ethernet port in
CPE305/CPE310 with CPU firmware 8.30 Sweep impact of EGD on Embedded Ethernet
interface. Direct replacement for S90-30 IC693CPU374.
 New communications capabilities provided by:
o IC695PNS001 – PROFINET Scanner Module
o IC695GCG001 – Genius Communications Gateway via PROFINET
o IC695EDS001 – Ethernet based DNP3 Outstation
2 PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

Rev Date Description

S July-  Support for Modbus/TCP Server, SRTP channels and Modbus/TCP client channels on RX3i
2013 CPE305/CPE310 embedded Ethernet interface – Chapter 2 & Chapter 5
 Support for Access Control List – Chapter 3
 Modbus TCP/IP mapping for CPE305/CPE310 – Chapter 3
 Enhanced Security Passwords and OEM Protection – Chapter 4
 Serial I/O protocol enhancements (Data Set Ready, Ring Indicator, and Data Carrier
Detect) – Chapter 6
 Diagnostics for PROFINET alarms and PROFINET network faults, including #PNIO_ALARM,
SA0030 – refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual,
GFK-2950 Chapter 3 & Chapter 9.
 Instruction executions times measured for RX3i CPU320/CRU320 – Appendix A
 Sweep impact times for new modules: IC694MDL758, IC694APU300-CA and later,
IC695PNS001, IC694ALG442, IC694ALG220, IC694MDL645 and IC694MDL740 – Appendix
A
earlier  Added instructions for replacing the RX3i CPE305/CPE310 real-time clock battery:
Chapter 2
 Corrected definitions of reverse acting and direct acting modes for PID functions: refer to
PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 7.
 Expanded data for Boolean execution measurements – Appendix A
 Re-instated instruction times for RX7i CPE030/CRE030/CPE040 release 6.0 as published in
version Q of the manual (unintentionally omitted from version R) – Appendix A
 Compatibility information for volatile memory backup batteries has been consolidated in
the PACSystems Battery and Energy Pack Manual, GFK-2741 – throughout

1.2 PACSystems Control System Overview

The PACSystems controller environment combines performance, productivity, openness and
flexibility. The PACSystems control system integrates advanced technology with existing systems. The
result is seamless migration that protects your investment in I/O and application development.
1.2.1 Programming and Configuration

Proficy* Machine Edition programming software provides a universal engineering development
environment for all programming, configuration and diagnostics of PACSystems. A PACSystems CPU
is programmed and configured using the programming software to perform process and discrete
automation for various applications. The CPU communicates with I/O and smart option modules
through a rack-mounted backplane. It communicates with the programmer and/or HMI devices via
the Ethernet ports or via the serial ports COM1 and COM2 using Serial I/O, or Modbus RTU slave
protocols.
1.2.2 Process Systems
PACSystems CPUs with firmware version 5.0 and later support Proficy Process Systems (PPS). PPS is a
complete, tightly integrated, seamless process control system using PACSystems, Proficy HMI/SCADA,
and Proficy Production Management Software to provide control, optimization, and performance
management to manage and monitor batch or continuous manufacturing. It delivers the tools
required to design, implement, document, and maintain an automated process. For information
about purchasing PPS software, refer to the Support website.

1.2.3 PACSystems CPU Model
Family Catalog Number Description

RX3i Rackless CPUs IC695CPE400 1.2 GHz AMD G-Series Quad Core, 64 MB user
memory with Field Agent
RX3i CPUs IC695CPU310 300MHz Celeron CPU, 10 MB user memory
IC695CPU315 1 GHz Celeron-M CPU, 20 MB user memory
IC695CPU320 1 GHz Celeron-M CPU, 64 MB user memory
IC695NIU001+ 1.1 GHz Atom 510 NIU. For information, refer to
versions –AAAA & later the PACSystems RX3i Ethernet Network Interface
Unit User’s Manual, GFK-2439
IC695NIU001 300MHz Celeron NIU. For information, refer to the
PACSystems RX3i Ethernet Network Interface Unit
User’s Manual, GFK-2439
RX3i CPUs with IC695CPE305 1.1GHz Atom CPU, 5 MB user memory
embedded Ethernet
IC695CPE310 1.1GHz Atom CPU, 10 MB user memory
Interface1
IC695CPE330 1 GHz AMD G-Series Dual Core, 64 MB user
memory
RX3i Redundancy IC695CRU320 1 GHz Celeron-M CPU, 64 MB user memory
CPU
RX7i CPUs with IC698CPE010 300MHz, Celeron CPU, 10MB user memory
embedded Ethernet
IC698CPE020 700MHz, Pentium CPU, 10 MB user memory
Interface
IC698CPE030 600MHz, Pentium-M CPU, 64MB user memory
IC698CPE040 1800MHz, Pentium-M CPU, 64MB user memory
RX7i Redundancy IC698CRE020 700MHz, Pentium CPU, 10 MB user memory
CPUs with
IC698CRE030 600MHz, Pentium-M CPU, 64MB user memory
embedded
Ethernet Interface IC698CRE040 1800MHz, Pentium-M CPU, 64MB user memory
1 The RX3i CPE305/CPE310 embedded Ethernet interface provides a maximum of two programmer connections. It does not
support the full set of Ethernet interface features described in this manual. For a summary of RX3i embedded Ethernet
interface features, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224K or later.

1.3 RX3i Overview

The RX3i control system hardware consists of an RX3i universal backplane and up to seven
Series 90-30 expansion or remote racks. The CPU can be in any slot in the universal backplane
except the last slot, which is reserved for the serial bus transmitter, IC695LRE001.
The RX3i supports user defined Function Blocks (LD logic only) and Structured Text programming.
The RX3i universal backplane uses a dual bus that provides both:
 High-speed PCI for fast throughput of new advanced I/O.
 Serial backplane for easy migration of existing Series 90-30 I/O
The RX3i universal backplane and Series 90-30 expansion/remote racks support the Series 90-30
Genius Bus Controller and Motion Control modules, and most Series 90-30/RX3i discrete and analog
I/O with catalog prefixes IC693 and IC694. RX3i modules with catalog prefixes IC695, including the
Ethernet and other communications modules can only be installed in the universal backplane. See
the PACSystems RX3i System Manual, GFK-2314 for a list of supported modules.
RX3i supports hot standby (HSB) CPU redundancy, which allows a critical application or process to
continue operating if a failure occurs in any single component. A CPU redundancy system consists of
an active unit that actively controls the process and a backup unit that is synchronized with the
active unit and can take over the process if it becomes necessary. Each unit must have a redundancy
CPU, (IC695CRU320). The redundancy communication path is provided by IC695RMX128 Redundancy
Memory Xchange (RMX) modules set up as redundancy links. For details on the operation of
PACSystems redundancy systems, refer to the PACSystems Hot Standby CPU Redundancy User
Manual, GFK-2308.
RX3i communications features include:
 Open communications support includes Ethernet, PROFIBUS, PROFINET, Modbus TCP, Ethernet
Global Data (EGD), DNP3 and serial protocols.
 On the CPE400 one of its embedded Ethernet ports is set up as a dedicated Field Agent port.
 The CPE305, CPE310, and CPE330 and CPE400 CPUs provide an embedded Ethernet interface
which is used to connect to the programmer (Proficy Machine Edition).
 Effective with RX3i CPE310/CPE305 Firmware Release 7.30, or CPE330 Firmware Release 8.50, the
embedded Ethernet port on the CPU provides support for Service Request Transfer Protocol
(SRTP) channels and for Modbus TCP. This feature is available on all firmware releases of CPE400.
 Effective with CPE310/CPE305 Firmware Release 8.20, or CPE330 Firmware Release 8.45, the CPE
embedded Ethernet port supports OPC UA Server. This feature is available on all firmware
releases of CPE400. Refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User
Manual, GFK-2224 version M or higher (Chapter 10).
 Effective with RX3i Firmware Release 8.302, the CPE310/CPE305 CPUs also support Ethernet
Global Data (EGD). Prior to that firmware release, EGD was only available in the RX3i via the RX3i
Ethernet Interface Module (IC695ETM001). With this upgrade, these CPUs are positioned as a
direct replacement for S90-30 IC693CPU374.
 Effective with RX3i Firmware Release 8.603, the CPE330 supports Ethernet Global Data (EGD)
Class 1. This feature is available on all firmware releases of CPE400.
2 Proficy Machine Edition Release 8.50 SIM 7 is required for EGD Class 1 on Embedded Ethernet interface of CPE305/CPE310.
3 Proficy Machine Edition Release 8.60 SIM 5 is required for EGD Class 1 on both LAN1 and LAN2 of CPE330. This PME version
also supports Advanced Configuration Parameters for EGD on CPE330. Alternately, PME Release 8.60 (not SIM 5) supports
EGD on CPE330 LAN1 only, and does not support Advanced Configuration Parameters for EGD.

 The rack-based IC695ETM001 Ethernet Interface has dual RJ45 ports connected through an
auto-sensing switch. This eliminates the need for rack-to-rack switches or hubs. The ETM001
supports upload, download and online monitoring, and provides 32 SRTP channels with a
maximum of 48 simultaneous SRTP server connections. It also supports Modbus TCP. For details
on Ethernet Interface capabilities, refer to PACSystems RX7i & RX3i TCP/IP Ethernet
 PROFIBUS communications via the PROFIBUS Master module, IC695PBM300. For details, refer to
the PACSystems RX3i PROFIBUS Modules User’s Manual, GFK-2301.
 PROFINET communications via any supported PROFINET Controller and any supported PROFINET
Scanner.
o Supported PROFINET Controllers include the embedded PROFINET Controller function
offered by IC695CPE400 and IC695CPE330, and the rack-mounted PROFINET Controller
module IC695PNC001.
o Supported PROFINET Scanners include the RX3i PROFINET Scanner module
IC695PNS0014, the RX3i IC695CEP001, and the VersaMax PROFINET Scanner modules
IC200PNS001 & IC200PNS002.
For details, refer to the PACSystems RX3i PROFINET IO-Controller Manual, GFK-2571F or later and
PACSystems RX3i PROFINET Scanner Manual, GFK-2737F or later.
 Effective with the release of IC695CEP001 and IC694CEE001, the RX3i may be configured to
control a remote drop consisting of one or two I/O modules. The RX3i interface to the remote
drop is managed by the PROFINET Controller, IC695PNC001. Refer to PACSystems RX3i CEP
PROFINET Scanner User Manual, GFK-2883.
 HART Pass Through allows an RX3i CPU to communicate HART asset management data between
HART-capable I/O modules and PC-based asset management tools. This entails usage of PC-
based applications, RX3i Analog modules with HART functionality and (optionally) supporting
PROFINET products. HART Pass Through operation is described in the PACSystems HART Pass
Through User Manual, GFK-2929.
The following RX3i CPUs support HART Pass Through: IC695CPE305, IC695CPE310, IC695CPU315,
IC695CPU320, IC695CRU320, IC695CPE3305,6 (Firmware Release 8.50 or later).
The following RX3i analog modules support HART:
IC695ALG626
IC695ALG628
IC695ALG728
If used for HART Pass Through, the supporting RX3i PROFINET Controller and PROFINET Scanner
must also contain HART-compatible firmware:
IC695PNC001-AK Firmware Release 2.20
IC695PNS001-ABAH Firmware Release 2.307
IC695CEP001-AAAD Firmware Release 2.30.
4 IC695PNS001 firmware release 2.40 added support for a number of I/O modules not previously supported, as documented
in PACSystems RX3i PROFINET Scanner Important Product Information, GFK-2738L.
5 When used to support HART Pass Through, CPE330 must do so via a PNC001 and cannot employ its embedded PROFINET
feature for this purpose.

6 IC695CPE330 firmware release 8.95 added support for the Remote Get HART Device Information COMMREQ.
7 IC695PNS001 firmware release 2.41 added support for the Remote Get HART Device Information COMMREQ not previously
supported, as documented in PACSystems RX3i PROFINET Scanner Important Product Information, GFK-2738L. The syntax
and usage for this COMMREQ are described in the PACSystems RX3i System Manual, GFK-2314M or later.

 Effective with the release of IC695GCG001, the RX3i may be equipped to control a Genius Bus.
The RX3i interface to the Genius Gateway is managed by the PROFINET Controller, IC695PNC001.
Refer to PACSystems RX3i Genius Communications Gateway User Manual, GFK-2892.
 Effective with the release of IC695EDS001, the RX3i may be configured as a DNP3 Outstation.
Refer to PACSystems RX3i DNP3 Outstation Module IC695EDS001User’s Manual, GFK-2911.
 Effective with the release of IC695EIS001, the RX3i may be configured to act as an IEC 104 Server.
Refer to PACSystems RX3i IEC 104 Server Module IC695EIS001 User’s Manual, GFK-2949.
 IC695CMM002 and IC695CMM004 expand the serial communications capability of the RX3i
system. Refer to PACSystems RX3i Serial Communications Modules User’s Manual, GFK-2460.
 CPE310, CPU310, CPU315, CPU/CRU320 and NIU001 provide two serial ports, one RS-232 and
one RS-485.
 CPE305 provides one RS-232 serial port.
 CPE330 provides no serial ports.
 The serial port on CPE400 is disabled.

1.4 RX7i Overview

The RX7i control system hardware consists of an RX7i rack and up to seven Series 90-70 expansion
racks. The CPU resides in slot 1 of the main rack. RX7i racks use a VME64 backplane that provides up
to four times the bandwidth of existing VME based systems, including the current Series 90-70
systems for faster I/O throughput. The VME64 base supports all standard VME modules including
Series 90-70 I/O and VMIC modules.
Expansion racks support Series 90-70 discrete and analog I/O, the Genius Bus Controller, and the
High-Speed Counter. The CPU provides an embedded auto-sensing 10/100 Mbps half/full duplex
Ethernet interface.
RX7i supports hot standby (HSB) CPU redundancy, which allows a critical application or process to
continue operating if a failure occurs in any single component. A CPU redundancy system consists of
an active unit that actively controls the process and a backup unit that is synchronized with the
active unit and can take over the process if it becomes necessary. Each unit must have a redundancy
CPU, (IC698CRE020, CRE030 or CRE040). The redundancy communication path is provided by
IC698RMX016 Redundancy Memory Xchange (RMX) modules set up as redundancy links. For details
on the operation of PACSystems redundancy systems, refer to the PACSystems Hot Standby CPU
Redundancy User Manual, GFK-2308.
Note: Extended operation with dissimilar CPU types is not allowed. During normal operation, the
primary and secondary units in an HSB redundancy system must have the same CPU
model type.
The primary and secondary units of an HSB redundancy system can have dissimilar model types for
a limited time, for the purpose of system upgrade only. Fail wait times for the higher performance
CPU in a dissimilar redundant pair may need to be increased to allow synchronization.
RX7i communications features include:
 Open communications support includes Ethernet, Genius, and serial protocols.
 A built-in 10/100mb Ethernet interface that has dual RJ45 ports connected through an auto-
sensing switch for upload, download and online monitoring. This eliminates the need for
rack-to-rack switches or hubs. The CPU Ethernet Interface provides basic remote control
system monitoring from a web browser and allows a combined total of up to 16 web server
and FTP connections. For details on Ethernet Interface capabilities, refer to PACSystems RX7i
& RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
 Two serial ports, one RS-232 and one RS-485.
 An RS-232 isolated Ethernet Station Manager serial port.

1.5 Migrating Series 90 Applications to PACSystems

The PACSystems control system provides cost-effective expansion of existing systems. Support for
existing Series 90 modules, expansion racks and remote racks protects your hardware investment.
You can upgrade on your timetable without disturbing panel wiring.
 The RX3i supports most Series 90-30 modules, expansion racks, and remote racks. For a list of
supported I/O, Communications, Motion, and Intelligent modules, see the PACSystems RX3i
System Manual, GFK-2314.
 The RX7i supports most existing Series 90-70 modules, expansion racks and Genius networks. For
a list of supported I/O, Communications, and Intelligent modules, see the PACSystems RX7i
Installation Manual, GFK-2223.
 Conversion of Series 90-70 and Series 90-30 programs preserves existing development effort.
 Conversion of VersaPro and Logicmaster applications to Machine Edition allows smooth
transition to PACSystems.

1.6 Documentation
PACSystems Manuals
PACSystems RX7i and RX3i CPU Reference Manual GFK-2222
PACSystems RX7i and RX3i CPU Programmer’s Reference Manual GFK-2950
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual GFK-2224
PACSystems TCP/IP Ethernet Communications Station Manager User Manual GFK-2225
C Programmer’s Toolkit for PACSystems GFK-2259
PACSystems Memory Xchange Modules User’s Manual GFK-2300
PACSystems Hot Standby CPU Redundancy User Manual GFK-2308
PACSystems Battery and Energy Pack Manual GFK-2741
Proficy Machine Edition Logic Developer Getting Started GFK-1918
Proficy Process Systems Getting Started Guide GFK-2487
PACSystems RXi, RX3i, and RX7i Controller Secure Deployment Guide GFK-2830
RX3i Manuals
PACSystems RX3i System Manual GFK-2314
PACSystems RX3i IC695CPE400 1.2GHz 64MB Rackless CPU w/Field Agent QSG GFK-3002
PACSystems RX3i IC695ACC403 Rackless Energy Pack Quick Start Guide GFK-3000
PACSystems RX3i IC695CPE330 1GHz 64MB CPU w/Ethernet Quick Start Guide GFK-2941
PACSystems RX3i IC695ACC402 Energy Pack Quick Start Guide GFK-2939
PACSystems RX3i IC695ACC400 Energy Pack Data Sheet GFK-2724
DSM324i Motion Controller for PACSystems RX3i and Series 90-30 User’s GFK-2347
Manual
PACSystems RX3i PROFIBUS Modules User’s Manual GFK-2301
PACSystems RX3i Max-On Hot Standby Redundancy User’s Manual GFK-2409
PACSystems RX3i Ethernet Network Interface Unit User’s Manual GFK-2439
PACMotion Multi-Axis Motion Controller User’s Manual GFK-2448
PACSystems RX3i PROFINET IO-Controller Manual GFK-2571
PACSystems RX3i PROFINET Scanner Manual GFK-2737
PACSystems RX3i CEP PROFINET Scanner User Manual GFK-2883
PACSystems RX3i Serial Communications Modules User’s Manual GFK-2460
PACSystems RX3i Genius Communications Gateway User Manual GFK-2892
PACSystems RX3i DNP3 Outstation Module IC695EDS001User’s Manual GFK-2911
PACSystems RX3i IEC 104 Server Module IC695EIS001User’s Manual GFK-2949

PACSystems HART Pass Through User Manual GFK-2929

Field Agent Manuals
Field Agent User’s Guide GFK-2993
RX7i Manuals
PACSystems RX7i Installation Manual GFK-2223
PACSystems RX7i User's Guide to Integration of VME Modules GFK-2235
Series 90-70 Genius Bus Controller User’s Manual GFK-2017
Series 90 Manuals
Series 90 Programmable Coprocessor Module and Support Software GFK-0255
Series 90 PLC Serial Communications User’s Manual GFK-0582
Series 90-70 DLAN/DLAN+ Interface Module User’s Manual GFK-0729
Series 90-30 Genius Bus Controller User’s Manual GFK-1034
Distributed I/O Systems Manuals
Genius I/O System User’s Manual GEK-90486-1
Genius I/O Analog and Discrete Blocks User’s Manual GEK-90486-2
In addition to these manuals, datasheets and product update documents describe individual
modules and product revisions. The most recent PACSystems documentation is available on GE’s
Automation and Controls support website www.geautomation.com.
.

Chapter 2 CPU Features & Specifications
This chapter provides details on the hardware features of the PACSystems CPUs and their
specifications.
 Common CPU Features
 RX3i CPU Features and Specifications
 RX7i CPU Features and Specifications

Chapter 2. CPU Features & Specifications
2.1 Common CPU Features

2.1.1 Features Shared by All PACSystems CPU Models
 Programming in Ladder Diagram, Function Block Diagram, Structured Text and C.
 Floating point (real) data functions.
 Configurable data and program memory.
 Non-volatile built-in flash memory for user data (program, configuration, register data, and
symbolic variable) storage. Use of this flash memory is optional.
 Configurable RUN/STOP Mode switch.
 Embedded serial and/or Ethernet communications (refer to comparison charts in RX3i CPU
Features and Specifications and RX7i CPU Features and Specifications).
 Up to 512 program blocks. Maximum size for a block is 128KB.
 Auto Located Symbolic Variables, which allows you to create a variable without specifying a
reference address.
 Bulk memory area accessed via reference table %W. The upper limit of this memory area can
be configured to the maximum available user RAM.
 Larger reference table sizes, compared to Series 90* CPUs: 32Kbits for discrete %I and %Q
and up to 32K words each for analog %AI and %AQ.
 Online Editing mode that allows you to easily test modifications to a running program. (For
details on using this feature, refer to the programming software online help and Proficy Logic
Developer Getting Started, GFK-1918.)
 Bit in word referencing that allows you to specify individual bits in a WORD reference in
retentive memory as inputs and outputs of Boolean expressions, function blocks, and calls
that accept bit parameters.
 In-system upgradeable firmware for CPU
 Indirect mechanism for upgrading firmware in backplane modules via the CPU.
2.1.2 Features Shared by Certain PACSystems CPU Models
 CPE305, CPE310, CPE330 and CPE400 have battery-less retention of user memory when each
is connected to its compatible Energy Pack.
 All prior models have battery-backed RAM for user data (program, configuration, register
data, and symbolic variable) storage and clocks.
 CPE305, CPE310, CPE330 and CPE400 models have coin battery backup for their real-time
clocks (elapsed time clock).
 CPE305, CPE310 and CPE330 models have the ability to upload and download data from a
Removable Data Storage Device (RDSD). This feature is pending on CPE400.
 CPE305, CPE310, CPE330 and CPE400 models support OPC-UA.
 CPE305, CPE310, CPE330 and CPE400 models support Ethernet Global Data Class 1.
For a comparative review of CPU features, refer to RX3i CPU Features and Specifications and RX7i
CPU Features and Specifications. Note that each specific feature may require a corresponding
firmware release of the CPU firmware.
14 RX7i & RX3i CPU Reference Manual GFK-2222Y

2.1.3 Firmware Storage in Flash Memory

The CPU uses non-volatile flash memory for storing the operating system firmware. This allows
firmware to be updated without disassembling the module or replacing EPROMs. The operating
system firmware is updated by connecting to the CPU with a PC compatible computer and running
the software included with the firmware upgrade kit.
Each upgrade kit contains specific instructions for performing the upgrade. Depending on the CPU
Model and Firmware Version, the method employed is one of the following:
a) Use a serial port and the WinLoader utility (applies to CPU310, CPU315 & CPU320 models and
to CPE305/CPE310 models containing firmware versions prior to v7.30)
b) Use a USB port and memory stick for CPE305/CPE310 models with firmware version 7.30 and
later
c) Use an Ethernet port and a Web-based mechanism for RXi CPUs, CPE330 and CPE400.
2.1.4 Operation, Protection, and Module Status
Operation of the CPU can be controlled by the three-position RUN/STOP Switch or remotely by an
attached programmer and programming software. Program and configuration data can be locked
through software passwords. The status of the CPU is indicated by the CPU LEDs on the front of the
module. For details, see Indicators for each PACSystems family.
Note: The RESET pushbutton is provided to support future features and has no effect on CPU
operation in the current version.
2.1.5 Ethernet Global Data
Notes: Effective with RX3i Firmware Release 8.302, the CPE310/CPE305 CPUs also support EGD
Class 1. Prior to that firmware release, EGD was only available in the RX3i via the RX3i
Ethernet Interface Module (ETM001).
Effective with RX3i Firmware Release 8.603, CPE330 also supports EGD Class 1. This feature is
available on all firmware releases of CPE400.
Each PACSystems CPU supports up to 255 simultaneous EGD pages across all Ethernet interfaces in
the Controller. EGD pages must be configured in the programming software and stored into the CPU.
The EGD configuration can also be loaded from the CPU into the programming software. Both
produced and consumed pages can be configured. PACSystems CPUs support the use of only part of
a consumed EGD page, and EGD page production and consumption to the broadcast IP address of
the local subnet.
The PACSystems CPU supports 2ms EGD page production and timeout resolution. EGD pages can be
configured for a production period of 0, indicating the page is to be produced every output scan. The
minimum period for these “as fast as possible” pages is 2 ms. Refer to the section, A3.6 for EGD
configuration on Embedded Ethernet interface of CPE305/310.
During EGD configuration, PACSystems Ethernet interfaces are identified by their Rack/Slot location.

2.1.6 Embedded PROFINET Controller

The following CPUs support a feature that permits an Ethernet LAN to be configured for use as a
PROFINET Controller:
 CPE400
 CPE330 (firmware version 8.90 or later required)
If the Embedded PROFINET Controller feature is to be configured, it must be configured on LAN2 for
CPE400 and CPE330. In the case of CPE400, which is a Rackless CPU, this will be its only PROFINET
Controller. In the case of CPE330, the Embedded PROFINET Controller can co-exist with any rack-
mounted PROFINET Controllers (IC695PNC001) present in its CPU rack.
To enable the Embedded PROFINET Controller in a project in Proficy Machine Edition8, select the
CPE400 (or CPE330) target in the PME Navigator (Figure 1) and open the Hardware Configuration. On
the Settings tab, change the designated LAN Mode of the selected port to PROFINET. The PROFINET
Controller node description then displays that a PROFINET node exists on the selected LAN. For
further details, refer to the PACSystems RX3i PROFINET IO-Controller User Manual, GFK-2571F or later.
Figure 1: Configuring an Embedded PROFINET Controller

A PROFINET configuration may be transferred between a PROFINET Controller module (IC695PNC001)
and the target Embedded PROFINET IO-Controller using the cut / copy / paste functions in Proficy
Machine Edition.
The Embedded PROFINET Controller may be configured as a Simplex PROFINET IO-Controller with
support for up to 32 I/O devices. For update rates, loading and other considerations, refer to the
PACSystems RX3i PROFINET IO Controller User Manual, GFK-2571F or later.
The Embedded PROFINET Controller supports Media Redundancy Protocol (MRP) and may be used as
either a Media Redundancy Manager (MRM) or Media Redundancy Client (MRC) on a redundant media
ring. For details concerning the Media Redundancy Protocol, refer to the PACSystems RX3i PROFINET
IO Controller User Manual, GFK-2571F or later.
8 Proficy Machine Edition Logic Developer PLC 8.60 SIM 13 or 9.00 SIM 4 or later is required for configuration of the
Embedded PROFINET Controller function.

2.1.7 OPC UA
Each PACSystems CPE305/CPE310/CPE330/CPE400 supports Open Productivity and Connectivity
Unified Architecture (OPC UA) Server communications on the embedded Ethernet port only.
For more information on OPC UA support refer to PACSystems RX7i & RX3i TCP/IP Ethernet
Communications User Manual, GFK-2224 version M or higher (Chapter 10).
Note: Effective with CPE310/CPE305 Firmware Release 8.20, the CPE embedded Ethernet port
supports OPC UA Server.
2.1.8 Removable Data Storage Devices (RDSDs)
The CPE305/CPE310/CPE3309 CPUs provide the ability to transfer applications to and from
Removable Data Storage Devices (RDSD). Typically, these are USB-compatible devices, such as a
memory stick, smart phone, digital camera or an MP3 device. Once the data is copied to the RDSD, it
can be written to other RX3i CPUs of the same type. In order to copy using RDSD, no PME
programming software is needed. The RDSD interface requires a user-supplied flash memory device
that complies with the USB 2.0 Specification.
The USB port must be enabled in the RX3i configuration in order to transfer data between the CPU
and the RDSD. The compatible CPUs are shipped with the RDSD (USB) port enabled.
The RDSD load and store operations can include the following data:
 An entire application, including logic and configuration, reference table data, and cam files for
Motion applications. (Motion files and local logic for DSM motion applications are supported.)
Configuration can include Ethernet Global Data and Advanced User Parameters for the rack-
based Ethernet interface. (Although a complete, unmodified application must be placed on the
RDSD, you can use an options.txt file to download selected components of the application to the
target CPU.)
 Passwords and OEM key, if any, are encrypted and written to the RDSD when the project is
loaded from the CPU. When the project is stored to a CPU that has no passwords or OEM key,
those are copied to the CPU.
Note: With Enhanced Security enabled, the RDSD update will fail if the RDSD source controller
has Level 4 password protection and the destination controller is password protected,
regardless of whether the passwords match.
With Legacy security, when the project is stored to a CPU that has passwords and/or
OEM key, the passwords must match or the store will fail.
 Fault tables are written to the RDSD before and after a load to or store from the RDSD.
 If a hardware configuration that disables the USB port is successfully stored to the CPU, the fault
tables will not be written to the RDSD at completion of the store operation.
Note: The USB port is for transfer of application data only. It is not intended for permanent
connection. Do not leave RDSD devices connected during normal operation.
Note: When using RDSD, all programming software connections must be in the Offline state for the
RDSD to function properly.
Note: CPE330 does not support Cfast memory cards as RDSD devices.
9 Pending for CPE400 at time of publication.

2.1.8.1 Uploading a Project from the CPU to the RDSD

Notes: Only one application project can be stored to the RDSD at a time. Before the RX3i writes the
project to the RDSD, any previous application is removed; if a directory named PACS_Folder
exists on the RDSD at the start of the upload, it is deleted with all of its contents.
Flash devices write in whole memory blocks and memory block sizes vary among devices.
The amount of space used by a project may vary between RDSDs due to the differences in
minimum block sizes and therefore the number of blocks used by a project. The minimum
amount of memory required will be the size of the entire project plus an additional block for
the options.txt file, if used.
1. Place the CPU that contains the project to be transferred in RUN Mode or STOP Mode.
2. If PME is online with the RX3i, either go Offline or select Monitor mode.
3. Insert the RDSD into the USB connector on the CPU. (After 1 – 2 sec, the RDSD LED turns solid
green.)
4. For CPE305/CPE310, push the RDSD direction switch to the left (UPLOAD), then momentarily
depress the START pushbutton. For CPE330, depress the RDSD UPLD pushbutton.
5. Do not remove the RDSD from the CPU during the transfer.
 The RDSD LED blinks green during the transfer. This can take from 10 – 150 sec, depending
upon the size of the project data.
 The RDSD LED should turn solid green, indicating that the transfer completed successfully.
 If the RDSD LED turns solid red, the transfer has failed. There will be a copy of the fault tables
as they existed at the end of the attempted transfer on the RDSD. Insert the RDSD into a PC
which has the PACS Analyzer software and select the plcfaultafter.dat file on the RDSD for
fault table analysis by the Analyzer. The PACS Analyzer software can be downloaded from the
Support website, www.geautomation.com.
 If the RDSD LED turns solid red, indicating an error, another RDSD operation cannot be
initiated until the device is disconnected then reconnected.
Caution
 If the RDSD is removed during data transfer from the CPU, the
integrity of the RDSD and the files on it cannot be guaranteed.
The RDSD status LED may indicate an RDSD fault, and the CPU
will abort the data transfer and remain in its current operating
mode.
 The project files, consisting of the entire contents of the PACS_Folder
directory and all of its subdirectories, loaded on the RDSD must not be
modified. If they are modified, the files transferred to the CPU will be
invalid.
6. When the RDSD LED turns solid green, indicating the transfer has been successfully completed,
remove the RDSD from the CPU. The RDSD can now be used to transfer the application to other
RX3i controllers of the same model type.
You can copy the entire applications directory to another USB device and use that device as the
source for downloads to CPE305/CPE310/CPE330 CPUs, provided none of the files in that
directory are changed in any way during the transfer.

2.1.8.2 Downloading a Project from the RDSD to the CPU

To download a project to the RX3i, the RDSD must contain a valid project, consisting of the hardware
configuration, application logic, and reference memory in a compiled format (originating from
another RX3i controller). The project files, consisting of the entire contents of the PACS_Folder
directory and all of its subdirectories, loaded on the RDSD must not be modified. If they are modified,
the files transferred to the CPU will be invalid.
By default, all project components are stored to the CPU and are written to flash. You can change
this operation by placing an options.txt file on the RDSD as described below.
1. Ensure that the RX3i is in STOP Mode
2. If PROFICY Machine Edition is online with the RX3i, either go Offline or select Monitor mode.
3. Connect the RDSD to the USB connector on the CPU that will be receiving the files. The RDSD LED
turns solid green.
4. For CPE305/CPE310, move the RDSD direction switch to the right (DOWNLOAD), then momentarily
depress the START pushbutton. For CPE330, depress the RDSD DNLD pushbutton.
5. Do not remove the RDSD from the CPU during the transfer.
 If the target name in the RDSD is different from the target name in the RX3i, the RDSD LED will
blink red. If this is expected or acceptable, momentarily depress the START pushbutton again.
 The RDSD LED blinks green during the transfer. This can take from 10 – 150 sec, depending
upon the size of the project data.
 The RDSD LED should turn solid green, indicating that the transfer completed successfully.
Unless the RUN/STOP Switch has been disabled in the hardware configuration just stored, it
can be used to place the RX3i into RUN Mode after the transfer.
 If the RDSD LED turns solid red, the transfer has failed.
- The target memory area(s) in the CPU are cleared. For example, if only the Logic is being
download from the RDSD and the store fails (e.g. stick pulled, problem with transfer or
data), Logic memory is cleared following the failed RDSD download. If other memory
areas were also queued up for transfer, those memory areas are also cleared as a result
of the failure.
- There will be a copy of the fault tables as they existed at the end of the attempted
transfer on the RDSD. Insert the RDSD into a PC which has the PACS Analyzer software
and select the plcfaultafter.dat file on the RDSD for fault table analysis by the Analyzer.
- If the RDSD LED turns solid red, indicating an error, another RDSD operation cannot be
initiated until the device is disconnected then reconnected.
Caution
If the RDSD is removed during data transfer to the CPU, the
RX3i controller will generate a fatal fault (sequence store
fault) and SYS FLT LED will turn red. You will need to clear the
fault tables through a programmer connection or by power
cycling the CPU with the Energy Pack disconnected before
attempting to download again. Each type of data being
downloaded (logic, config, and/or data) is cleared within the
target CPU.
6. When the RDSD LED turns solid green, indicating the transfer has been successfully completed,
remove the RDSD from the CPU.

The RUN/STOP Switch can be used to place the RX3i into RUN Mode after the transfer, unless it
has been disabled in the hardware configuration just stored. If the RUN/STOP Switch is disabled,
you will first need to connect with the programmer to place the RX3i in RUN Mode.
2.1.8.3 Using an Options.txt File to Modify Download Operation
An options.txt file can be used to modify the operation of the RDSD during a store to the RX3i. This is a
plain-text file which can contain some or all of the following statements, in any order. The format of
each option line is the option keyword, followed by a space, followed by either a capital Y or a capital
N. The option keyword must be spelled exactly as indicated below. If an option statement is omitted
from the file, the default value will be used.
If you want to use all of the default operations, the options.txt file is not necessary.
Options.txt File Format
Option Keyword Default value Description
Download_LogicAndCf Y (yes) Logic and configuration are copied to the
g CPE305/CPE310/CPE330 (including symbolic variables)
Download_Data Y (yes) Reference memory is copied to the CPE305/CPE310/CPE330
(excluding symbolic variables)
Download_CamFiles Y (yes) CAM files are copied to the CPE305/CPE310/CPE330
Write_Flash Y (yes) The downloaded CPE305/CPE310/CPE330 contents (as specified
by the above keywords) by default will be written to flash upon
completion of the store
Sample options.txt File

If the following options.txt file is present on the RDSD, logic, configuration and reference data are
copied to the CPU, and files are written to flash. Cam files are not copied.
Download_LogicAndCfg Y
Download_Data Y
Download_CamFiles N
Write_Flash Y

2.1.8.4 Security
When the application is written to the RDSD from a controller that has passwords and/or an OEM key
defined, the passwords and OEM key are encrypted and stored on the RDSD. When the project is
written from the RDSD to a CPE305/CPE310/CPE3309, the passwords and OEM key are copied to it.
If an OEM key is defined on the RDSD, when transfer is complete, the OEM protection will be enabled
(locked). When an application is being stored to a CPE305 that already has passwords and/or an OEM
key defined, the passwords/key on the RDSD must match the passwords/key in the target
CPE305/CPE310/CPE330, or the transfer will fail.
2.1.8.5 RDSD Error Reporting
Errors are indicated when the RDSD LED becomes solid red (not blinking). All errors are reported in the
Controller fault tables. If the Controller has faults in its fault tables before it receives a store, the fault
tables are written to plcfaultbefore.dat and iofaultbefore.dat on the RDSD. If the Controller has faults
in its fault tables after it receives a store, the fault tables are written to plcfaultafter.dat and
iofaultafter.dat on the RDSD. Previous versions of these files are deleted before the transfer. If either
fault table is empty, the corresponding file is not written and will not be present.
To read any of the .dat files mentioned above, open PACS Analyzer. In settings, enable file analyze.
Then click the file analyze button on the main screen. Select as Input File the .dat file to be analyzed.
Select as Output File the filename and folder into which you wish to deposit the resulting text. The
text will be in English.
If a hardware configuration that disables the USB port is stored to the CPU, the fault tables will not be
written to the RDSD at completion of the store operation because the USB port will be disabled at the
end of the store process.

2.2 RX3i CPU Features and Specifications

CPU320/
CPU310 CPU315 CPE305 CPE310 CPE330 CPE400
CRU32010
Mature -
Discontinued - Mature -
Lifecycle Phase use CPE310 Active Active Active Active
use CPE310 use CPE330
or CPE330
1.1 GHz Intel 1.1 GHz Intel 1 GHz AMD
1.2 GHz AMD
300 MHz Intel 1 GHz Intel 1 GHz Intel Z510PT Z510PT G-Series Dual
Microprocessor Specification G-Series Quad
Celeron Celeron M Celeron M Silverthorne Silverthorne Core SoC
Core SoC
XL “Atom” XL “Atom” GX-209HA
Operating System VxWorks VxWorks VxWorks VxWorks VxWorks VxWorks VxWorks
#RX3i Slots Occupied 2 2 2 1 2 2 N/A
Backplane <----------------------Supports High-Speed PCI IC695* and Serial IC694* Modules --------------------------> Field Agent
Temperature Range
RX3i 0°C to 60°C 0°C to 60°C 0°C to 60°C 0°C to 60°C 0°C to 60°C 0°C to 60°C -40°C to 70°C
Power Requirements
RX3i +3.3Vdc 1.25 A 1.0 A 1.0 A 1.0 A 1.0 A 0A N/A
1.0 A 1.0 A
RX3i +5 Vdc 1.0 A 1.2 A 1.2 A (up to 1.5 A if (up to 1.5 A if 0A N/A
USB draws 0.5A) USB draws 0.5A)
0.5 A at start-up; 0.5 A at start-up;
RX3i +24Vdc Relay with Energy Pack 0.1 A otherwise 0.1 A otherwise
0.750 A N/A
RX3i +24Vdc Relay w/o Energy Pack 0.625 A N/A
Input Power (Max) 20 W
Input Voltage (Min) 18 Vdc
Input Voltage (Max) 30 Vdc
Battery Battery Battery Energy Pack: Energy Pack: Energy Pack: Energy Pack:
Memory Backup Mechanism11
see GFK-2741 see GFK-2741 see GFK-2741 IC695ACC400 IC695ACC400 IC695ACC402 IC695ACC403
Display
LEDs LEDs LEDs LEDs LEDs LEDs LEDs & OLED
10 For CRU-type CPUs, see Redundancy section at bottom of this table.

11 See Battery Compatibility and Memory Retention (Time in Days at 20°C) in GFK-2741

CPU320/
CRU32010
Firmware Upgrade
v7.30 & later: v7.30 & later:
USB USB
<---------------WinLoader/Serial Port---------------> Web Interface Web Interface
CPU Firmware Upgrade Mechanism earlier: earlier:
Ethernet Port Ethernet Port
WinLoader/ WinLoader/
Serial Port Serial Port
Web Interface
Indirect Backplane Module Upgrade <-----------------------------------WinLoader/Serial Port------------------------------------> N/A
Ethernet Port
Program Portability
CPU310, CPU315,
Direct Import (with limitations)12 N/A
CPU315 CPU320
RX3i PACSystems Applications using
Y
Family Type Conversion
Program Security
Secure Boot Pending Y
Trusted Platform Module (TPM) Y Y
Program Storage
Battery-backed RAM 10 Mbytes13 20 Mbytes13 64 Mbytes13 5 Mbytes14 10 Mbytes14 64 Mbytes14 64 Mbytes14
Non-Volatile Flash 10 Mbytes 20 Mbytes 64 Mbytes 5 Mbytes 10 Mbytes 64 Mbytes 64 Mbytes
Battery Life Expectancy, RAM Backup11 see GFK-2741 see GFK-2741 see GFK-2741 N/A
Life Expectancy, Energy Pack
5 years 5 years 5 years 5 years
Capacitors
Auxiliary Storage
CFast Inactive N/A
Remote Data Storage Device (RDSD) Y - USB Y - USB Y - USB USB - pending
Micro SD pending
12 See corresponding IPI for target CPU.

13 Battery-backed RAM.
14 RAM backup with compatible Energy Pack attached.

CPU320/
CRU32010
Programming Capabilities
Max Number of Program Blocks 512 512 512 512 512 512 512
Program Block Max Size 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB
Discrete Reference Memory (%I, %Q)15 32 Kbits 32 Kbits 32 Kbits 32 Kbits 32 Kbits 32 Kbits 32 Kbits
Analog Reference Memory (%AI, %AQ)15 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords
up to max up to max up to max up to max up to max up to max up to max user
Bulk Reference Memory (%W)15
user RAM user RAM user RAM user RAM user RAM user RAM RAM
Managed Memory (Symbolic + I/O up to 10 up to 20 up to 64 up to 10 up to 64 up to 64
up to 5 Mbytes
Variables)15,16 Mbytes Mbytes Mbytes Mbytes Mbytes Mbytes
Floating Point y y y y y y y
Ladder Diagram (LD) y y y y y y y
Function Block Diagram (FBD) y y y y y y y
Structured Text (ST) y y y y y y y
PID Built-In Function Block y y y y y y y
"C" Language External Blocks y y y y y y y
15 Note: Whenever the size of any reference memory is changed, the content of the corresponding reference memory is automatically cleared.
16 For discussion of memory types and how they are managed, refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 3.

CPU320/
CRU32010
Communications
Ethernet Non-Switched RJ45 10/100/1000 10/100/1000
(dedicated NIC) x1 x1
Embedded Field Agent Ethernet RJ45 10/100/1000
(dedicated NIC) x1
10/100/1000 10/100/1000
Ethernet Switched RJ45 (shared NIC)
x2 x4 (2 pairs)
10BaseT/100BaseT RJ45 10/100 x1 10/100 x1 N
Built-in and Built-in and Built-in and
Ethernet Communications Platform ETM001 only ETM001 only ETM001 only Built-in
/or ETM001 /or ETM001 /or ETM001
Advanced User Parameters (AUP file) N/A N/A N/A Y17 Y17 N18 N18
RS-232 9-pin D x1 9-pin D x1 9-pin D x1 RJ-25 x1 9-pin D x1 N/A pending
RS-485 15-pin D x1 15-pin D x1 15-pin D x1 15-pin D x1 N/A N/A
USB-A 2.0 or USB 3.0 x 2
USB USB-A 2.0 x1 USB-A 2.0 x1
USB-A 1.1 x1 (inactive)
Time-of-Day Clock
Time-of-Day Clock Accuracy (@60°C) ±2 secs/day ±2 secs/day ±2 secs/day ±2 secs/day ±2 secs/day ±2 secs/day ±2 secs/day
Elapsed Time Clock (internal timing)
±0.01% max ±0.01% max ±0.01% max ±0.01% max ±0.01% max ±0.01% max ±0.01% max
accuracy
Simple Network Time Protocol (SNTP) ±2 ms using ±2 ms using ±2 ms using ±2 ms using ±2 ms using ±2 ms using
N/A
accuracy to timestamp19 ETM001 ETM001 ETM001 ETM001 ETM001 ETM001
RTC Battery Backup Y Y Y Y
RTC Battery Life expectancy 5 years 5 years 5 years 5 years
17 Refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224M or later for supported AUPs.
18 The Advanced User Parameters (AUP) feature has been incorporated into PME Hardware Configuration (HWC) effective with PME release 8.60 SIM5.
19 SNTP is not supported by the embedded CPU Ethernet interfaces at time of publication. Use ETM001 for SNTP.

CPU320/
CRU32010
Protocols
Modbus RTU Slave Y Y Y Y Y N/A N/A
SNP Slave Y Y Y Y Y N/A N/A
Serial I/O Y Y Y Y Y N/A N/A
SRTP (# simultaneous server conns) up to 2 up to 2 up to 48 up to 48
Modbus TCP
up to 16 up to 16 up to 16 up to 16
(# simultaneous server connections)
SRTP Channel or Modbus TCP Client
up to 16 up to 16 up to 32 up to 32
(# simultaneous)
Ethernet Global Data (EGD) FW 8.3020 FW 8.3020 FW 8.6020 Y
Number of EGD Exchanges (max) 21 255 255 255 255
Selective Consumption of EGD Y Y pending pending
PROFINET22 N N FW 8.90 Y
OPC-UA Server23 FW 8.2024 FW 8.2024 Y24 Y24
Remote Station Manager over UDP Y Y Y - limited Y - limited
Station Manager over Serial Comm Port via ETM001 via ETM001 via ETM001 via ETM001 via ETM001 via ETM001 N/A
20 EGD Class 1 only

21 Limit is per target, so all producers and consumers in the rack are counted towards this limit.
22 CPE400 and CPE330 (firmware version 8.80 or later) provide PROFINET support via an embedded PROFINET Controller: no external hardware is required. All other
CPUs that support PROFINET require a rack-mounted PROFINET Controller (IC695PNC001). CPE330 may also host IC695PNC001 modules in the CPU rack. Refer to the
PACSystems RX3i PROFINET IO-Controller Manual, GFK-2571F or later.
23 For a discussion of OPC UA, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224M Chapter 10.
24 Supports up to 12,500 Variables and up to 5 sessions.

CPU320/
CRU32010
Model Configurable Configurable
Redundancy Features
CRU320 only in CPE330 in CPE400
Single bit Single bit

Memory Error Checking and Correction correcting & correcting &
pending
(ECC) Multiple bit Multiple bit
checking checking
Switchover Time (max)25 1 logic scan 1 logic scan pending
Switchover Time (min)25 3.133 ms TBD pending
Max data in redundancy transfer list26 2 Mbytes 2 Mbytes pending
RMX128 x2 RMX128 x2
Redundant Synchronized Links max max
pending
Supported RMX228 x2 RMX228 x2
max max
25 Switchover time is defined as the time from failure detection until backup CPU is active in a redundancy system.
26 Symbolic variable and Reference data can be exchanged between redundancy controllers, up to the stipulated limit.

2.2.1 CPE400
2.2.1.1 Introduction
The IC695CPE400 is the first RX3i Rackless CPU. It operates in stand-alone fashion. All prior RX3i CPUs
slotted into an RX3i backplane. The CPE400 does not.
There are two mounting options:
1) As shipped, it mounts onto a DIN rail using a DIN-rail adaptor plate YAVD-I2C2-01-A.
2) Alternately, it mounts directly in a cabinet, using a panel-mount adaptor plate YA-l2-C2.04-A.
The mounting instructions and power requirements are documented in the RX3i IC695CPE400
1.2GHz 64MB Rackless CPU w/Field Agent Quick Start Guide, GFK-3002, and are not replicated here.
The physical features of the CPE400 are shown in Figure 2 and Figure 3.
Figure 2: CPE400 Front View and Features

The PACSystems* RX3i CPE400 is a richly featured programmable controller CPU equipped with a
1.2GHz quad-core microprocessor, 64Mbytes of built-in program memory and six high-speed
Ethernet ports, one of which is a dedicated Field Agent port. The CPE400 is ideally suited for multi-tier
communications and for synchronizing large amounts of data. Its metal housing provides superior
electrical noise immunity.

The CPE400 is programmed and configured over Ethernet via GE’s Proficy* Machine Edition (PME)
software. It is a stand-alone CPU with the following features:
 An OLED display that provides access to basic CPE400 status and control information.
 A micro-SD slot which may be used for program transfer and/or data collection. The slot is
protected by a cover that protects the memory card from ESD. This slot is not yet functional.
 A built-in RX3i PLC, supported by a dedicated microprocessor core.
o User may program in Ladder Diagram, Structured Text, Function Block Diagram, or C.
o Contains 64Mbytes of configurable data and program memory.
o Supports auto-located Symbolic Variables that can use any amount of user memory.
o Reference table sizes include 32k bits for discrete %I and %Q and up to 32k words each for
analog %AI and %AQ. Bulk memory (%W) also supported for data exchanges.
o Supports up to 512 program blocks. Maximum size for a block is 128KB.
 Supports four independent 10/100/1000 Ethernet LANs. Three are located on the front panel, as
shown in Figure 2. LAN1 attaches via the upper, dedicated RJ45 connector. LAN2 and LAN327
each attach via a pair of internally-switched RJ45 connectors. The fourth LAN, labeled EFA
(Embedded Field Agent), is an RJ45 port located on the underside (Figure 3), and is a dedicated
Field Agent port.
 The embedded communications interface is supported by a dedicated microprocessor core. This
dedicated processing capability permits the CPU to independently support LAN1, LAN2 and
LAN327 with:
o up to 48 simultaneous SRTP Server connections;
o up to 16 simultaneous Modbus/TCP Server connections;
o 32 Clients are permitted; each may be SRTP or Modbus/TCP.
o OPC UA Server with support for up to 5 concurrent sessions with up to 10 concurrent variable
subscriptions and up to 12,500 variables;
o up to 255 simultaneous Class 1 Ethernet Global Data (EGD) exchanges.
 The embedded PLC may use one or both of the Ethernet LAN2 ports to support the embedded
Simplex PROFINET I/O Controller. PROFINET supports up to 32 I/O devices with update rates of
1 – 512ms. I/O device update rates of 8ms and faster are possible with 16 or fewer devices.
Update rates of 16ms and higher result whenever more than 16 devices are configured.
 Field Agent permits the CPE400 to securely exchange data with the Predix™ Cloud, allowing
users to configure and view extensive data from an entire installation, such as a wind turbine
farm, within the Predix Cloud environment. This functionality is supported by two of the four
CPE400 microprocessor cores.
 Optional Energy Pack, IC695ACC403, allows CPE400 to instantly save user memory to non-
volatile storage in the event of loss of power. Upon restoration of power, with the ACC403
connected, the CPE400 PLC function is able to resume operations from the state saved at power-
down.
 Ability to display serial number and date code in PME Device Information Details.
 Ability to display IP Address of each LAN on the OLED display.
27 At time of publication, CPE400 LAN3 is not operational.

2.2.1.2 Switches CPE400

All user-accessible switches are provided as pushbuttons on the front panel, as described in the
following table.
Pushbutton Function
DISP Permits user to navigate menus in the OLED display.
SEL Permits user to select the menu item on the OLED display.
RUN Activates OLED Menu to select RUN/Enabled or RUN/Disabled Mode for the embedded PLC.
STOP Activates OLED Menu to select STOP/Enabled or STOP/Disabled Mode for the embedded PLC.
PHY PRES Not functional.
PWR Hold down for brief period to induce CPU Reset.
2.2.1.3 OLED Display

The monochrome organic light-emitting diode (OLED) display (Figure 2) is used to display operating
system menus. It measures 34.5 x 23 cm and displays 128 dots horizontally and 64 dots vertically. It
interacts with the DISP pushbutton, which jogs the cursor from one menu item to the next, and with
the SEL pushbutton, which activates the currently indicated menu item for further action.
The OLED display permits the user to:
 Display Ethernet LAN Settings: IPv4 address.
 Display the PLC firmware revision.
 Set/view PLC mode and view sweep time.
 Set the PLC mode to RUN/STOP with I/O Enabled/Disabled via the display.
Note: the RUN and STOP pushbuttons activate the PLC Mode menu items per Section 2.2.1.2
above.
 View whether all, some, or none of the PROFINET I/O devices are connected.
 Display EFA Settings: IPv4 address, subnet mask, gateway, MAC address, IPv6 address.
 Issue Field Agent Commands: Enter/Exit Configuration mode, Clear Configuration,
Perform factory reset.
 View Field Agent Status: Off, Starting, Connecting, Connected, Connected-ACT.

Figure 3: CPE400 Underside Ports & Connectors

2.2.1.4 Status Indicator LEDs

LED LED State Operating State
RUN28 On Green PLC is in RUN mode.
Off PLC is in STOP mode.
RUN Blinking in CPU is updating an internal programmable hardware device.
unison
OE
PHY On Green TPM Physical Presence (not functional).

PRES
Off
SSD On Green Activity detected on Solid State Disk.
Off No activity detected on Solid State Disk.
TEMP On Red CPU Overtemperature condition detected.
Off Overtemperature condition not detected.
OK On Green CPU has passed its power-up diagnostics and is functioning properly.
(Following initialization sequence.)
Off Power is not applied or CPU has a problem.
Blinking; PLC in STOP/Halt state; possible watchdog timer fault. If the programmer
All other LEDs cannot connect, cycle power with charged Energy Pack attached and refer
off to fault tables.
OK Blinking CPU encountered a Secure Boot Error.
alternately
OE
OE On Green Output scan is enabled.

Off Output scan is disabled.
FRC On Yellow One or more Overrides active in I/O Reference Tables.
Off No Overrides active in any I/O Reference Table.
FLT On Red PLC is in STOP/Faulted mode: a fatal fault has occurred.
Off No fatal faults detected.
IO On Green PROFINET Connection Status = OK.
Off PROFINET Connection Status not OK.
RACT On Green Active Redundant Unit (not functional).
Off
RBOK On Green Redundant Backup Unit (not functional).
Off
28 This LED is located between the RUN and STOP pushbuttons. It indicates the PLC Mode.


FAOK On Green Field Agent Running and Connected to Cloud.
Blinking Green Blink at 0.5 Hz: Field Agent Starting.
Blink at 1 Hz: Field Agent Running.
Off Field Agent Off.
PWR On Green CPU running.
Blinking Green Booting up – diagnostics in progress.
On Red Off
Off Reset / Power not detected.

2.2.1.5 Micro-SD Card Interface

The Micro SD Card slot is located on the right-hand side of the equipment (Figure 2), level with the
OLED display. This port is not functional at time of publication. Once functional, it will support the
Removable Data Storage Device features discussed in Section 2.1.8.
The interface supports SD, SDHC and SDXC µSD-Cards up to Version 3.0.
Insert the card into to slot, oriented as described below. Apply pressure it until you feel some
resistance. The card will latch into place and can then be read by the equipment. Apply pressure
again to remove the card from the slot.
Figure 4: CPE400 Micro-SD & USB Pinouts

Note that the µSD-Card needs to be inserted in the slot with the correct orientation. The pins of the
card need to face towards the front of the equipment (Figure 4).
A cover and screw are provided. To minimize CPE400 susceptibility to electrical noise interference,
keep the cover in place during normal operation.

2.2.1.6 USB 3.0 Interface

The USB ports are not functional at time of publication. Once functional, they will support the
Removable Data Storage Device features discussed in Section 2.1.8.
Two USB ports, using standard USB Type A connectors (Figure 2), are located on the faceplate below
the OLED display.
This pair of ports is protected with a 1.5A fuse. For normal operation, do not exceed 0.9 A per
connector. The USB overcurrent detection does not identify which port created the situation: it could
be either one. Remove the root cause of the overcurrent in order to permit normal operation.
Pinouts for the USB ports (Figure 4) are:
Pin# Signal Name
1 USB_VCC29
2 USB-
3 USB+
4 GND
5 SSRX-
6 SSRX+
7 GND
8 SSTX-
9 SSTX+
The maximum cable length for USB 3.0 cables is 3m (=118”) for Port 1 and 15cm (=6”) for Port 2.
29 USB_VCC is limited to 1500mA by an electronic fuse shared by the two USB ports. For normal operation, do not exceed
900mA at this pin for either port.

2.2.1.7 Ethernet Ports CPE400

CPE400 supports a total of four independent 10/100/1000 Ethernet Local Area Networks (LANs).
 LAN1 connects to the uppermost faceplate RJ45 connector (Figure 2). It is not switched.
 LAN2 connects to the next two lower faceplate RJ45 connectors (Figure 2). These two
connectors are switched internally. If desired, one or both of these ports may be configured
as the Embedded PROFINET port.
 LAN327 connects to the two lowest faceplate RJ45 connectors (Figure 2). These two
connectors are also switched internally. LAN3 is intended for use in Redundancy applications.
This feature set is not available yet.
1. The fourth LAN is marked EFA (Embedded Field Agent) and is located on the underside of the
equipment (Figure 3). It supports the Field Agent function and may not be used as a standard
Ethernet port. Refer to Section 0. Each of the embedded Ethernet interfaces automatically senses
the data rate (10 Mbps or 100 Mbps or 1 Gbps), communications mode (half-duplex or full-duplex),
and cabling arrangement (straight-through or crossover) of the attached link.
For improved performance, the LAN1, LAN2 and LAN3 are serviced by a dedicated microprocessor
core. In this way, the servicing of the Ethernet ports is independent of the controller logic, I/O
scanning and Field Agent activities. The EFA port is independently serviced by two of the four
microprocessor cores. This superior level of servicing is required at the higher communications rates.
Any of the front-panel Ethernet ports may be used to communicate with the PME programming
software using the Service Request Transport Protocol (SRTP, a proprietary GE protocol, used
primarily for communication with the programmer). The EFA port cannot be used for this purpose.
LAN2 may be configured as an embedded PROFINET Controller, as discussed in Section 2.1.6. While
configured as a PROFINET Controller, LAN2 may concurrently be used for Ethernet protocols. This
topic is discussed in the PACSystems RX3i PROFINET IO Controller User Manual, GFK-2571F or later.
LAN2 and LAN3 each support a pair of RJ45 connectors. In this way, network devices on the same
LAN, but operating at different data rates may be connected to a suitably configured port.
To establish Ethernet communications between the PME programming and configuration software
and the CPU, you first need to know the target IP address. Use the OLED menu function to check
the IP Address. For default IP Address and other details, refer to Establishing Initial Ethernet
Communications, Section 3.4.1.
CAT 5 cables (or superior) are required for proper operation with 100/1000BaseT LANs. The pin
arrangements are:
Pin Name 10/100BASE-T Name 1000BASE-T
1 TxD+ LP_DA+
2 TxD- LP_DA-
3 RxD+ LP_DB+
4 NC LP_DC+
5 NC LP_DC-
6 RxD- LP_DB-
7 NC LP_DD+
8 NC LP_DD-

Two LEDs are integrated into each RJ45 connector. These LEDs indicate the link status and link
speed, as follows:
Ethernet Indicators (LAN1, LAN2, LAN3 RJ45 Built-in LEDs)
Link On Green The corresponding link has been established.

Status
(upper) Blinking Traffic is detected at the corresponding port.
Green
Off No connection established at corresponding port.
Link On Green Corresponding data speed is 1 Gbps or 100 Mbps.

Speed
(lower) Off Corresponding network data speed is 10 Mbps

2.2.1.8 Field Agent

The Embedded Field Agent (EFA) port on the underside of CPE400 (Figure 3) is an Ethernet port
dedicated to the Field Agent functionality.
Figure 5: Typical Field Agent Application
Figure 5 shows a typical Field Agent application, in which the role of the CPE400 Embedded Field
Agent (EFA) is to gather data locally, then securely transfer selected data to the Predix Cloud via the
EFA port. The PACSystems RX3i maintains control over the remaining Ethernet ports on the CPE400,
as well as its serial port. Data from the local environment may be obtained via any of these ports can
be manipulated by the RX3i PLC and tagged for use in the Field Control application.
The remote user with an acceptable security profile can then access data in the cloud from multiple
installations, aggregate selected data and make decisions based on the bigger picture. For instance,
the CPE400 could be installed in a control system monitoring a single wind turbine. The remote user
might be monitoring several hundred such turbines. With a suitable dashboard-style application on
his computer, the remote user could identify turbines that need to come offline for maintenance, or
turbines whose power generation output could be enhanced or retarded to fit demand.

To utilize the EFA port (for detailed steps, refer to the Field Agent User’s Guide, GFK-2993):
1. Connect a Cat 6 Ethernet cable between a computer and the CPE400 EFA port.
2. Set the IP address of the computer to 172.31.0.101 (or any IP address on the 172.31.0.0/16
subnet other than 172.31.0.100, which is the default IP address for the CPE400 EFA port).
Note that the EFA IP address can be read from the CPE400’s OLED display in the “FA Settings”
-> “Network Config” -> “IP Address” and “Subnet Mask”.
3. Use the OLED display to enable Configuration Mode by toggling “FA Settings” -> “Commands”
-> “Config Mode”. The Predix Machine Web Console is only accessible while the EFA is in
Configuration Mode. Note that Configuration Mode will automatically disable after one hour if
not explicitly disabled earlier.
4. Using a browser on the computer, browse to the Predix Machine Web Console at
https://172.31.0.100:8443/system/console. The Google Chrome browser is recommended for
accessing the Predix Machine Web Console.
a. Log in using the default password, then update the password.
b. Verify that the Log Service page displays. This confirms that log in has been successful.
c. Configure the EFA port for WAN network.
d. Configure a Network proxy, if required.
e. Configure Time Synchronization.
f. For maximum security, update the Field Agent firmware before connecting to the
Internet. This procedure is outlined in the Field Agent User’s Guide, GFK-2993. See the
chapter on Updating the Field Agent, specifically Method 1: Manual Local Update Using a
Local Area Network.
5. Provide a means of connecting to the Internet.
6. Enroll the CPE400 in the Predix Cloud:
a. The Administrator logs into the EdgeManager and creates one of the following:
i. Two user accounts: one with the Operator role and the other with the Technician role
ii. One user account with both the Operator and Technician roles
b. From the customer’s EdgeManager URL, the Operator logs into the EdgeManager and
creates a Field Agent device representation with the desired Device Name and Device ID.
c. The Operator assigns the newly created Field Agent device to an EdgeManager user with
the Technician role.
d. The Technician obtains the following enrollment information from the Operator:
i. The EdgeManager Enrollment URL
ii. The User Authentication and Authorization (UAA) URL used to authenticate the
Technician
iii. The Device ID selected by the Operator
iv. The device’s Activation Code
e. The Technician logs into the Web Console on the Field Agent to be enrolled, and navigates
to the Predix Cloud Enrollment page under Technician Console, Predix Cloud Enrollment.
f. The Technician enters the enrollment information, presses the Enroll Device button, and
authorizes the enrollment (which may include providing the Technician’s EdgeManager
Username and Password).
g. From EdgeManager, the Operator verifies that the Field Agent is displayed as Reachable.
7. For security, toggle Configuration Mode to disable access to the Predix Machine Web
Console.
8. Disconnect the local computer once enrollment has been completed.
9. Configure and Manage the activities on the EFA using Predix EdgeManager. This involves
selecting tags in the CPE400’s OPC-UA server and configuring these as read, write or
read/write. In this way, the system is set up to allow data to pass securely from the CPE400 to

the Predix Cloud, where that data may be used by external cloud applications. Detailed steps
are as follows:
a. Using a computer, download the default EFA configuration from:
https://digitalsupport.ge.com/communities/en_US/Download/IC695CPE400-Embedded-
Field-Agent-EFA-Configuration-Templates
b. Configure the OPC UA Data Source to opc.tcp://localControllerHost:4840
c. Configure the OPC UA tags and subscriptions in the OPCUA Machine Adaptor xml file.
d. Configure the data destination in the WebSocket River configuration.
e. Leave the Store and Forward service enabled.
f. Zip up the configuration and upload it to the Edge Manager repository.
g. Deploy the configuration to the Field Agent using Edge Manager.
Note that data will now be transferring from the Field Agent to the Predix Time Series Database.
Note that communications between the CPE400 and the Predix Cloud is secured using
authentication and encryption.
Note that the Field Agent firmware within the CPE400 may need to be updated from time to time. GE
recommends that all such firmware be kept up-to-date. The Technician has the ability to configure
the Field Agent for scheduled automatic updates or manual updates. Refer to the chapter on
Updating the Field Agent in the Field Agent User’s Guide, GFK-2993.
Two LEDs are integrated into the EFA RJ45 connector. These LEDs indicate the link status and link
speed, as follows:
Ethernet Indicators (EFA RJ45 Built-in LEDs)
Link On Green The corresponding link has been established.

Status
(upper) Blinking Traffic is detected at the corresponding port.
Green
Off No connection established at corresponding port.
Link On Green Corresponding network data speed is 1 Gbps.

Speed
(lower) On Yellow EFA port only: Corresponding network data speed is 100 Mbps
Off Corresponding network data speed is 10 Mbps

2.2.1.9 Serial Port CPE400

The Serial Port (COM1) is not functional at time of publication.
CPE400 is equipped with an RJ45 serial port. It is marked COM and is located on the underside of the
equipment (Figure 3). Its default settings are RS-232C, 115kBaud, 8 data bits, no parity and 1 stop bit.
For pinout, refer to Section 5.2.3.3. For more general information on serial port usage, refer to
Chapter 5.
Note that CPE400 does not support PME connection via the serial port; use an Ethernet port,
Also note CPE400 supports only the Modbus function on its serial port.
2.2.1.10 Display Port

The Display port is not functional at time of publication.
The Display Port is a DP++ video port located on the underside of the CPE440 (Figure 3). It provides
signals for connecting a suitable monitor or video adapter. Pinouts for the Display Port (Figure 6) are:
Pins Signal Name

1/3 TxD0+/-
4/6 TxD1+/-
7/9 TxD2+/-
10/12 TxD3+/-
13 AUXSEL
15 CLK/AUX+
17 DAT/AUX-
18 HTPLG
14 NC
20 DP_VCC30
2, 5, 8, 11, 16, 19 GND
Figure 6: Display Port Connector
30 DP_VCC is limited to 720mA by an electronic fuse. However, for normal operation do not exceed 500mA at this pin.

2.2.1.11 Energy Pack Connector

The CPE400 compatible Energy Pack, IC695ACC403, is supplied with a purpose-built cable which
installs in the connector shown in Figure 3.
Use of the Energy Pack is optional. Once charged up, the ACC403 allows the CPE400 to instantly save
user memory to non-volatile storage in the event of loss of power. Upon restoration of power, with
the ACC403 connected, the CPE400 PLC function is able to resume operations from the state saved
at power-down.
Refer to the PACSystems RX3i Rackless Energy Pack IC695ACC403 Quick Start Guide, GFK-3000, for
complete wiring and grounding instructions.
Note that the connector shown in Figure 3 is not supplied with the CPE400.
2.2.1.12 Input Power Connector

If no Energy Pack is to be connected, refer to Section 2.4 of the RX3i IC695CPE400 1.2GHz 64MB
Rackless CPU w/Field Agent Quick Start Guide, GFK-3002. Otherwise, refer to the PACSystems RX3i
Rackless Energy Pack IC695ACC403 Quick Start Guide, GFK-3000,
2.2.1.13 Backwards Compatibility of CPE400
In Proficy Machine Edition, the CPE400 is identified as a PLC within the PACSystems RX3i Rackless
family. To convert an existing project which uses any other PLC, use the Family Conversion feature in
PME. Be aware of the constraints involved. For instance, the first PROFINET Controller in an RX3i
CPU320 application will be assigned to the Embedded PROFINET Controller feature (refer to Section
2.1.6) of the CPE400.

2.2.1.14 Replacement of Real-Time Clock Battery on CPE400
Figure 7: Location of RTC battery on CPE400

The CPE400 is shipped with a real-time clock (RTC) battery installed on an internal circuit board (see
Figure 7). This battery will need to be replaced periodically by a qualified service technician. Typically,
no action is required during initial installation.
Should the RTC battery fail, the CPU date and time will be reset to 12:00 AM, 01-10-2000 at start-up.
The CPU operates normally with a failed or missing RTC battery; however, the initial CPU time-of-day
(TOD) clock information will be incorrect.
There are no diagnostics or indicators to monitor RTC battery status. The RTC battery has an
estimated life of 5 years and must be replaced every 5 years on a preventative maintenance
schedule.
To replace a depleted battery:
1. Power down the CPE400.
2. Disconnect the external cables attached to the CPE400, labelling each for later reconnection.
3. Remove the CPE400 from its installed location.
4. Take the CPE400 to a clean environment.
5. Remove the DIN-rail or panel-mount adaptor plate, as applicable.
6. Place the CPE400 on a workbench so that the heat-sink adjacent to the GE logo on the front
panel is facing up.
7. With ESD protection in place, remove the four screws holding the upper side heat sink in place.
8. Remove the heat sink. This exposes the circuit board, connectors and coin battery shown in
Figure 7.

9. Take care to collect any thermal pads that may have been dislodged. These will be needed
during reassembly.
10. While removing or replacing the battery, take care not to damage the nearby ribbon cable (not
shown).
11. Using a non-conductive pliers, grip the battery and simultaneously hold back the retaining clip so
it is clear of the battery.
12. Remove the depleted battery and dispose of it by an approved method.
13. Install the replacement battery so that the inscribed positive face is up.
14. Check that the retaining clip has engaged the edge of the newly installed battery.
15. Apply any dislodged thermal pads to the surface of the corresponding components on the circuit
board.
16. Replace the heat sink.
17. Tighten all four retaining screws to 0.6Nm.
18. Reattach the adaptor plate removed in step 5.
19. Restore the CPE400 module to its original location and secure it in place.
20. Reconnect all cables to their original connectors.
21. Turn power back on.
22. If needed, set the current date and time via Proficy Machine Edition.
The replacement battery must be IC690ACC001 from GE Automation & Controls, or an equivalent,
such as Rayovac™ Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C.
Warning
Use of a different type of battery than that specified here
may present a risk of fire or explosion.
Battery may explode if mistreated. Do not recharge,
disassemble, heat above 100°C (212°F), or incinerate.
Caution
To avoid damage from electrostatic discharge, use proper
precautions when performing these procedures:
 Wear a properly functioning antistatic strap and be sure that you
are fully grounded. Never touch the printed circuit board, or
components on the board, unless you are wearing an antistatic
strap.
 Any surface upon which you place the unprotected circuit board
should be static-safe, facilitated by antistatic mats if possible.
Extra caution should be taken in cold, dry weather, when static charges can
easily build up.

2.2.1.15 Replacement of CPE400 Mounting Bracket

When shipped, the CPE400 is attached to the DIN-rail mounting bracket. The panel-mount bracket is
supplied in the shipping carton, unattached. If the application requires panel-mounting rather than
DIN-Rail mounting, exchange the mounting brackets, as follows.
1. Using a T10 TORX screwdriver, remove the four machine screws (Figure 8) that secure the
DIN-Rail Mounting Bracket to the CPE400 chassis.
2. Keep the DIN-Rail Mounting Bracket and its four screws together in case of future need;
otherwise discard.
3. Install the panel-mount bracket as shown in Figure 9, using the four machine screws supplied
with that bracket. Note that the closed eyelet is towards the top of the chassis.
4. Using a T10 TORX screwdriver, torque these four machine screws to 0.6Nm (0.44 ft-lbs) in
order to securely attach the bracket to the CPE400 chassis.
5. If reversing the bracket switch, note that each bracket requires its own set of machine
screws. Torque requirements are the same.
Figure 8: DIN-Rail Mount Bracket Assembly Figure 9: Panel-Mount Bracket Assembly CPE400
CPE400

2.2.2 CPE330
Figure 10: CPE330 Front View & Features

2.2.2.1 Serial Ports CPE330

CPE330 is not equipped with a serial port. Use the embedded Ethernet ports for all communications
with the CPU; use IC695CMM002 or IC695CMM004 modules for serial communications.
2.2.2.2 Ethernet Ports CPE330
CPE330 supports two independent 10/100/1000 Ethernet Local Area Networks (LANs).
 LAN1 connects to the uppermost RJ45 connector (Figure 10). It is not switched.
 LAN2 connects to the two lower RJ45 connectors. They are switched internally.
Space is provided beside each connector (Figure 10) to record the IP address used on each LAN.
Each of the embedded Ethernet interfaces automatically senses the data rate (10 Mbps or 100 Mbps
or 1 Gbps), communications mode (half-duplex or full-duplex), and cabling arrangement (straight-
through or crossover) of the attached link.
Any of the embedded Ethernet ports may be used to communicate with the Proficy Machine Edition
(PME) programming and configuration software using the Service Request Transport Protocol (SRTP, a
proprietary GE protocol, used primarily for communication with the programmer).
For default IP Address and other details, refer to Establishing Initial Ethernet Communications, Section
3.4.1.
Ethernet Network Configuration CPE330
The user must be careful when assigning IP Addresses and Subnet Masks for CPE330:
 Each LAN supports a unique IP Address
 LAN1 and LAN2 interfaces should not be configured for the same network.
By default, PME prohibits configuring both LAN interfaces on an overlapping IP subnet.
Care must also be taken when assigning IP Addresses and subnet masks to each LAN so that each
network does not overlap any remote subnets in the network infrastructure:
 Subnets overlap with one another when the subnet portions of the IP Addresses are not
completely unique
 Overlapping subnets may result in intermittent Ethernet communications, or none at all. This
would be due to packets being routed to the wrong LAN.
 Duplicate IP Addresses may also result in intermittent Ethernet communications, or none at
all. This is due to collisions on the LAN induced by two devices with the same IP Addresses
communicating at the same time.
Ethernet Gateway Operation CPE330
The CPE330 allows configuration of an Ethernet gateway on both LAN1 and LAN2. Since the CPE330
contains two LAN interfaces, each one supporting a unique IP Address, only one gateway is active at
a time.
 Whenever a gateway is configured on only one of the two LAN interfaces and the other is not
configured (0.0.0.0), the single gateway is shared by both interfaces;
 Whenever a gateway is configured on both LAN interfaces, the LAN1 gateway is given priority
over the LAN2 gateway as long as LAN1 is functional. For example, in the event the LAN1
cable is disconnected, the CPE330 will use the LAN2 gateway as a backup.

2.2.2.3 Switches CPE330

The RDSD and RUN/STOP Switches are located behind
the protective door, as shown in Figure 11.
Refer to RUN/STOP Switch Operation in Chapter 4.
The Reset pushbutton, located just above these
switches, is currently not used.
Figure 11: CPE330 RUN/STOP Switch and

RDSD Switches
RDSD Switch Operation CPE330

RDSD Pushbuttons Function
RDSD UPLD Loads user program or data from CPU to RDSD.
RDSD DNLD Stores user program or data from RDSD to CPU.
Refer to Removable Data Storage Devices (RDSDs) for full description of RDSD functionality.

2.2.2.4 Indicators CPE330

CPU Status Indicators On Blinking Off
CPE330 LED LED State Operating State

CPU OK On Green CPU has passed its power-up diagnostics and is functioning
properly. (After initialization sequence is complete.)
Off Power is not applied or CPU has a problem, which may be
indicated by blink pattern.
Blinking CPU in STOP-Halt state; possible watchdog timer fault. If PME
Other LEDs off cannot connect, cycle power with charged Energy Pack attached
and refer to fault tables.
On Amber Whenever CPU OK and FORCE are both amber, CPU is indicating
CPU320/CRU320 compatibility status. 31
RUN
Blinking in CPU is updating an internal programmable hardware device.
OUT EN unison
RUN On Green CPU is in RUN Mode.
Off CPU is in STOP Mode.

OUT EN On Green Output scan is enabled.

FORCE On Amber Override is active on a bit reference.
Note: CPU OK is not simultaneously amber.31
Off No Overrides active in I/O Reference Tables.
RDSD On Green USB or Cfast Device detected (No Activity)
Blinking Green Port activity detected on USB or Cfast Interface
Off No port activity detected on USB or Cfast Interface
On Red RDSD Failure
Blinking Red Target name mismatch: Press same RDSD pushbutton again to
dismiss.
SYS FLT On Red CPU is in Stop/Faulted mode: a fatal fault has occurred.
Off No fatal faults detected.
31 Refer to Backwards Compatibility of CPE330 with CPU320, CRU320, or CPU315.

Ethernet Indicators CPE330 (embedded in RJ45 connectors) On Blinking Off

LINK (upper) On Green The corresponding link is physically connected.
Blinking Green Traffic is detected at the corresponding port.
Off No connection detected at the corresponding port.

1Gbps (lower) On Amber (LAN1)
or Corresponding network data speed is 1 Gbps.
On Green (LAN2)
Off Corresponding network data speed is 100 Mbps or 10 Mbps.

2.2.2.5 Replacement of Real-Time Clock Battery on CPE330

The CPE330 is shipped with a real-time clock (RTC) battery installed
(see Figure 12). There is no isolation barrier between the battery
and the circuit. This battery will need to be replaced periodically.
Typically, no action is required during initial installation.
Should the RTC battery fail, the CPU date and time will be reset to
12:00 AM, 01-10-2000 at start-up. The CPU operates normally with
a failed or missing RTC battery; however, the initial CPU time-of-
day (TOD) clock information will be incorrect.
There are no diagnostics or indicators to monitor RTC battery
status. The RTC battery has an estimated life of 5 years and must
be replaced every 5 years on a preventative maintenance
schedule.
To replace a depleted battery,
1. Power down the RX3i rack.
2. Disconnect cables attached to the CPE330 module, labeling
each for later reconnection.
3. Remove the CPE330 module.
4. Take the CPE330 module to a clean environment.
5. Place the module on a workbench with the heat-sink side
down.
6. With ESD protection in place, remove the four screws holding
the upper side sheet metal in place.
7. Remove the sheet metal. This exposes the circuit board,
connectors and coin battery shown in Figure 12.
8. Using a non-conductive pliers, grip the battery and
simultaneously hold back the retaining clip so it is clear of the Figure 12: Location and
battery. Orientation of Real-Time Clock
9. Remove the depleted battery and dispose of it by an approved Battery in CPE330
method.
10. Install the replacement battery so that the inscribed positive face is towards the green
connector (i.e. downwards as shown in Figure 12).
11. Check that the retaining clip has engaged the edge of the newly installed battery.
12. Replace the sheet metal cover.
13. Tighten all four retaining screws to 0.9Nm (8 in-lbs).
14. Restore the CPE330 module to its original location and secure it in place.
15. Reconnect all cables to their original connectors.
16. Turn power on to the RX3i rack.
17. If needed, set the current date and time via PME or using SVC_REQ 7 (refer to PACSystems RX7i
and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 6).
Note: Battery replacement on CPE305 & CPE310 is different: see Figure 17.
Replacement Real-Time Clock Battery

such as Rayovac™ Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C.

Warning
Caution
strap.
easily build up.
2.2.2.6 Backwards Compatibility of CPE330 with CPU320, CRU320, or CPU315

The CPE330 may be interchanged with a corresponding CPU320/CRU320 with no upgrade to Proficy
Machine Edition (PME) software. Logic and configuration equality in PME are maintained when
storing the same project to either a CPU320/CRU320 or a CPE330.
An Extra Option Module fault is logged in the Controller Fault Table on the CPE330’s slot location after
downloading a CPU320/CRU320 configuration to a CPE330. This indicates that the Embedded
Ethernet interface did not receive a configuration. This fault is expected and does not interfere with
normal controller operation.
Migration of CPU315 applications to the CPE330 is possible with no upgrade to PME by converting
them to a CPU320 application and storing the project to the CPE330.
Versions of PME with native CPE330 support allow either a CPU320/CRU320 or a CPE330
configuration to be stored to the CPE330. When a CPE330 is configured as a CPU320/CRU320,
Ethernet properties cannot be configured. However, the embedded Ethernet ports may be used with
their previously configured IP Addresses or their default IP Addresses if the default IP Addresses were
never changed.
Since CPE330 has no serial ports, any serial port activity associated with the previous
CPU320/CRU320 application needs to be migrated to a suitable rack-based module (IC695CMM002
or IC695CMM004).

To download projects intended for the CPU320/CRU320 to a CPE330 with versions of PME that do not
support the CPE330, you must change the CPE330’s compatibility setting. To change the
compatibility setting, perform the following operations:
1. Remove any USB stick that might be attached to the USB connector on the CPE330.
2. Place the RUN/STOP switch on the CPE330 in the STOP position.
3. Hold down the RDSD UPLD button and turn power on to the CPE330. Continue to depress the RDSD
UPLD button until the CPE330 powers up and displays one of the following patterns on the LEDs.
CPU Status Indicators On Blinking Off
CPE330 LED LED State Operating State

CPU OK On Amber CPU320 Compatibility mode.
FORCE On Amber
RUN Off
RDSD On Red
OUT EN Off
SYS FLT On Red
CPU OK On Amber CRU320 Compatibility mode.
FORCE On Amber
RUN On Red
RDSD Off
OUT EN Off
SYS FLT On Red
i. To toggle the compatibility setting, press the RDSD DNLD button. The compatibility indication will
toggle between the CPU320 compatibility and CRU320 compatibility patterns each time the RDSD
DNLD button is pressed.
ii. When the desired compatibility setting is displayed, press the RDSD UPLD button to save the setting
and allow the CPE330 to continue its normal startup procedures with the new setting. The setting is
maintained over a power cycle and firmware upgrade.
Note that with versions of PME that do not have native CPE330 support, only CPU320 projects can be
stored to a CPE330 that is in CPU320 compatibility mode. Similarly, only CRU320 projects can be
stored to a CPE330 that is in CRU320 compatibility mode.
Users of a CPE330 with PME versions 8.60 SIM8 or later do not need to change this compatibility
setting. PME versions 8.60 SIM8 or later allow for storing a CPU320 or CRU320 project without the
need to change this setting. By factory default, the CPE330 identifies as a CPU320.
Note that CPE330s with firmware versions 8.45 through 8.60 support compatibility with the CPU320
and CPU315 only. The compatibility setting using the RDSD buttons (described above) is not
supported for these firmware versions. Beginning with firmware version 8.70, CPE330s support
compatibility with the CPU320, CPU315, and CRU320 using the RDSD buttons to set the compatibility
setting.

2.2.3 CPE305 and CPE310
Figure 13: IC695CPE305 Front View Figure 14: IC695CPE310 Front View
2.2.3.1 Serial Ports

These ports provide serial interfaces to external devices and can be used for firmware upgrades. For
serial port pin assignments, electrical isolation, and details on serial communications, refer to
Chapter 5.
CPE305: one RS-232 port (using RJ-25 connector).
CPE310: one RS-232 port (COM1) and one RS-485 port (COM2).
The RS-232 port does not supply the 5Vdc power offered by other RX3i and Series 90-30 CPUs.
Use cable IC693CBL316 to connect to the serial RJ-25 port on the CPE305. This 3m shielded cable
provides a 9-pin D-connector on the other end.

2.2.3.2 Ethernet Port

The embedded Ethernet interface connects via one RJ45 Ethernet port that automatically senses the
data rate (10 Mbps or 100 Mbps), communication mode (half-duplex or full-duplex), and cabling
arrangement (straight-through or crossover) of the attached link.
The embedded Ethernet interface supports communications with the Proficy Machine Edition (PME)
programming and configuration software using the proprietary SRTP protocol. The CPE305/CPE310
CPUs provide two SRTP-server connections.
Refer to Establishing Initial Ethernet Communications, Section 3.4.1.

2.2.3.3 Switches CPE305 & CPE310

The RDSD and RUN/STOP Switches are located behind the protective door, as shown in Figure 15 and
Figure 16. Refer to RUN/STOP Switch Operation in Chapter 4. The Reset pushbutton is not used.
Figure 15: External Features of CPE305 Figure 16: External Features of CPE310
RDSD Switch Operation CPE305 & CPE310

RDSD Switches Function
Start pushbutton Pressing this switch initiates RDSD data transfer. (The three-position switch must
have previously been set to Upload or Download.)
See Removable Data Storage Devices (RDSDs) for full description of RDSD
functionality.
Three-position switch Enables/disables RDSD data transfer and selects the direction of data transfer.
Upload Loads application from CPU to RDSD.
Off Disables RDSD data transfer.
Download Stores application from RDSD to CPU.

2.2.3.4 Indicators CPE305 & CPE310

CPU Indicators On Blinking Off
CPE305 LED CPE310 LED LED State CPU Operating State

OK CPU OK On Green CPU has passed its power-up diagnostics and is
functioning properly. (After initialization sequence is
complete.)
Off CPU problem. RUN and OUTPUTS ENABLED LEDs
may be blinking in an error code pattern, which can
be used by technical support for troubleshooting.
This condition and any error codes should be
reported to your technical support representative.
Blinking CPU in STOP-Halt state; possible watchdog timer
Other LEDs off fault. Refer to the fault tables. If PME cannot
connect, cycle power with a charged Energy Pack
attached and refer to fault tables.
OK CPU OK Blinking in CPU is in boot mode and is waiting for a firmware
unison update through a serial port.
EN OUTPUTS
ENABLED
RN RUN On Green CPU is in RUN Mode.

EN OUTPUTS On Green Output scan is enabled.
ENABLED
I/O FORCE I/O FORCE On Yellow Override is active on a bit reference.
STATUS STATUS Blinking Energy Pack charging; not yet charged above the
Green minimum operating voltage.
On Red Energy Pack circuit fault.
Blinking Red Energy Pack near its end-of-life and should be

replaced soon.
On Green Energy Pack is charged above its minimum
operating voltage.
Off Energy Pack not connected.
SYS FLT SYS FLT On Red CPU is in Stop/Faulted mode because a fatal fault
(System Fault) has occurred.
CM COM1 Blinking Signals activity on serial port COM1.
Green
Off No activity on serial port COM1.
N/A RDSD / Blinking Signals activity on serial port COM2.
COM2 Green
Off No activity on serial port COM2.
(RDSD not attached)

RDSD Indicators CPE305 & CPE310 On Blinking Off
CPE305
CPE310 LED LED State RDSD Operating State
LED
SYS FLT On Red The RDSD has been removed during a store. The CPU
must be power cycled to resume RDSD operations.
RDSD / COM2 Off or
Blinking
Green
RDSD32 RDSD32/COM2 On Green Valid RDSD connected or data transfer complete.
Blinking Data transfer in progress.

Green
On Red RDSD fault. Check for and correct the following
conditions:
 CPU type mismatch with project on RDSD.
 Data transfer error.
 Corrupted or invalid USB file system.
 Insufficient space on RDSD.
Blinking RDSD-Controller project name mismatch.
Red
Off RDSD not attached or USB port is disabled.
Ethernet Indicators CPE305 & CPE310 On Blinking Off
LED LED State CPU Operating State

100 On Green Network data speed is 100 Mbps.
Off Network data speed is 10 Mbps.
LINK On Amber The link is physically connected.
Blinking Amber Traffic is detected at the corresponding port.
Off No connection detected.
32 RDSD active: RDSD attached to USB-A RDSD port.

2.2.3.5 Real-Time Clock Battery CPE305 & CPE310

The CPE305 and CPE310 are both shipped with a
real-time clock (RTC) battery (IC690ACC001) installed
(Figure 17), and with an isolation barrier on the
battery. Remove the isolation barrier via its pull-tab
before installing the CPE305 or CPE310 module;
otherwise the battery will not function.
There are no diagnostics or indicators to monitor
RTC battery status.
The RTC battery has an estimated life of 5 years and
must be replaced every 5 years on a preventative
maintenance schedule.
If the RTC battery fails, the CPU date and time is
reset to 12:00 AM, 01-10-2000 at startup. The CPU
operates normally with a failed or missing RTC
battery; only the initial CPU TOD clock information
will be incorrect.
Note: Battery replacement on CPE330 is different.
Refer to Figure 12.
Figure 17: Accessing Real-Time Clock Battery
(CPE305 and CPE310)
Replacing the Real-Time Clock Battery in CPE305/CPE310

such as Rayovac Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C.
Warning
Caution
strap.
easily build up.

Battery Removal Method 1

1. Power down the rack and remove the CPU from the backplane.
2. Using a curved probe with a non-conducting surface, for example a non-metallic dental pick,
reach in from the back of the module and pull the battery out of its retaining clip. (You can
use needle-nose pliers to grasp the battery and pull it the rest of the way out.)
Sample Tool for Battery Removal
Figure 18: Sample Tool for Coin Battery Extraction

Battery Removal Method 2
1. Power down the rack and remove the CPU from the backplane.
2. Squeeze both sides of the module and remove the front section of the plastic housing.
3. Lift the two clips on the side of the plastic housing to release the circuit board and pull the
board out of the housing.
4. Pull the battery out of its retaining clip.
Installing a New RTC Battery
Install the battery with the positive (+) side up. That is, with the + side away from the board and
toward the housing plastic.

2.2.3.6 Backwards Compatibility of CPE310 with CPU310

The CPE310 may be swapped with a CPU310 with no upgrade to the Proficy Machine Edition Logic
Developer-PLC programming software. Logic and configuration equality in the programming
software is maintained when storing the same project to either a CPU310 or a CPE310. Proficy
Machine Edition versions that recognize the CPE310 (7.0 SIM3 and newer), allow either a CPU310
configuration or a CPE310 configuration to be stored to the CPE310. For all programming software
versions (both current and legacy) a CPU310 device can accept only a CPU310 configuration.
Legacy CPU310 Projects
The CPE310 supports CPU310 projects. Proficy Machine Edition versions earlier than 7.10 SIM 3
interpret the CPE310 as a CPU310. The CPE310 can be configured as a CPU310 using Proficy Machine
Edition versions as old as 5.5, Service Pack 1.
RDSD Port
If a CPU310 configuration is stored to a CPE310, the RDSD port is enabled to allow you to transfer
CPU310 projects to CPE310 models without using Proficy Machine Edition.
Fault Behavior
Faults related to the embedded CPE310 Ethernet interface may be generated on power-up, as
detailed in the following section.
Replacing a CPU310 with a CPE310
 A CPE310 that is configured as a CPU310 logs the following faults in the Controller fault table:
- A LAN Transceiver Fault is generated because the RX3i system detects that the embedded
Ethernet module does not have a network connection.
- An Extra Option Module fault is generated because the embedded Ethernet module is
detected as an unconfigured module.
- If the Energy Pack capacitor pack is disconnected or fails, the legacy faults for a missing or
failed battery are logged.
 When a CPE310 is configured as a CPU310, Ethernet properties cannot be configured and there
should be no cable connected to the Ethernet port.
 When a CPE310 is configured as a CPU310, the Show Status dialog box in Proficy Machine Edition
displays CPU310A.

2.2.3.7 CPE310 versus CPU310 Performance Differences

The following differences should be considered when converting legacy applications or developing
new applications.
 Some exceptionally lengthy CPE backplane operations, such as MC_CamTableSelect, Data Log
and Read Event Queue functions, will take longer to complete compared to other RX3i CPU
models, and may delay backplane operations to IC695 modules.
For example, when an MC_CamTableSelect function block is executed on the PMM335 module,
the CPU’s acknowledgement of the PMM355 module interrupt may be delayed. In this situation,
you may see the following fault in the I/O Fault Table, even when the interrupt has not been
dropped: Error initiating an interrupt to the CPU.
 Performance specifications for many features, such as power-up time, function block execution
times and I/O module sweep times have changed. For details, refer to Appendix A.
 The RS-232 port on the CPE310 does not provide 5Vdc power on pin 5.
2.2.3.8 CPU305 Performance Differences vs. CPE310 and Legacy RX3i CPUs
The CPE305 exhibits the same performance differences as listed above for the CPE310.
The CPE305 supports legacy CPU310 projects that fit within 5 Mbytes of user memory. The project
configuration must be changed to support this conversion.
Because the CPE305 has less user memory than the other RX3i CPUs, operations that involve
transferring large files could fail.
For example, depending on the number and sizes of Data Log files already stored, the Get_DL (Get
Data Log) command could fail with a C10 hex (file transfer failure occurred while sending the data log
file to the CPU) error. To correct this error
1. Upload the data logs to Machine Edition and delete the logs from the CPU.
2. Take steps to reduce the size of the log file, such as reducing the number of samples, the
sample rate, or the number of parameters logged.

2.2.4 CPU315 and CPU320/CRU320
Figure 19: IC695CPU320 Front View
2.2.4.1 Serial Ports CPU315, CPU320 & CRU320

Each CPU has two independent, on-board serial ports, accessed by connectors on the front of the
module. COM1 and COM2 provide serial interfaces to external devices. Either port can be used for
firmware upgrades. For serial port pin assignments, electrical isolation, and details on serial
communications, refer to Chapter 5.

2.2.4.2 Indicators CPU315, CPU320 & CRU320

Eight CPU LEDs indicate the operating status of various CPU functions.
Two Comm LEDs indicate activity on COM1 and COM2.
LED State
CPU Operating State
On Blinking Off
CPU OK On Green CPU has passed its power-up diagnostics and is
functioning properly. 33
Blinking Green CPU in Stop/Halt state; possible watchdog timer
connect, cycle power with battery attached and
refer to fault tables.
CPU OK Blinking in unison CPU is in boot mode and is waiting for a firmware
update through a serial port.
RUN
OUTPUS ENABLED
OUTPUTS On Green Output scan is enabled.
ENABLED
I/O FORCE On Yellow Override is active on a bit reference.
BATTERY Off Normal battery34
Blinking Red Battery low34
On Red Battery has failed or is not attached3
SYSTEM FAULT On Red CPU is in Stop/Faulted mode because a fatal fault
has occurred.
COM1 Blinking Green Signals activity on corresponding serial port.
COM2
33 After initialization sequence is complete.

34 Low battery detection requires hardware revision –Fx or later and a smart battery. For details, refer to the PACSystems
Battery and Energy Pack Manual, GFK-2741.

2.2.4.3 Error Checking and Correction, IC695CRU320

RX3i Redundancy CPUs provide error checking and correction (ECC), which results in slightly slower
system performance, primarily during power-up, because it uses an extra 8 bits that must be
initialized.
For details on ECC, refer to the PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
Note: Multiple Recoverable Memory Error faults may be generated when a single-bit ECC error is
detected. When a single-bit ECC error is detected, the value presented to the microprocessor
is corrected. However, the value stored in RAM is not corrected until the next time the
microprocessor writes to that RAM location.

2.2.5 CPU310
Figure 20: IC695CPU310 Front View
2.2.5.1 Serial Ports CPU310

The CPU has two independent, on-board serial ports, accessed by connectors on the front of the
module. COM1 and COM2 provide serial interfaces to external devices. Either port can be used for
firmware upgrades. For serial port pin assignments and other details on serial communications, refer
to Chapter 5.

2.2.5.2 Indicators CPU310

The eight CPU LEDs indicate the operating status of various CPU functions.
The two Comm LEDs indicate activity on COM1 and COM2.
LED State On Blinking Off CPU Operating State

functioning properly.35
CPU OK Blinking in unison CPU is in boot mode and is waiting for a firmware
RUN update through a serial port.
OUTPUTS
ENABLED
OUTPUTS On Green Output scan is enabled.
ENABLED
I/O FORCE On Yellow Override is active on a bit reference.
BATTERY Off Normal battery36
Blinking Red Battery low36
On Red Battery has failed or is not attached36
SYSTEM FAULT On Red CPU is in Stop/Faulted mode because a fatal fault
has occurred.
COM1 Blinking Green Signals activity on corresponding serial port.
COM2
35 After initialization sequence is complete.

36 Low battery detection requires a smart battery. For details, refer to PACSystems Battery and Energy Pack Manual,
GFK-2741.

2.3 RX7i CPU Features and Specifications

CPE010 CPE020 CPE030 CPE040
CPE020 & CRE020

Lifecycle Phase Discontinued Active Active
Discontinued
Microprocessor Specification 300 MHz Intel Celeron 700 MHz Intel Pentium 600 MHz Pentium-M 1.8 GHz Pentium-M
Operating System VxWorks VxWorks VxWorks VxWorks
#RX7i Slots Occupied 1 1 1 1
Backplane VME64 ANSI/VITA 1 VME64 ANSI/VITA 1 VME64 ANSI/VITA 1 VME64 ANSI/VITA 1
Temperature Range
With fan tray 0°C to 60°C 0°C to 60°C 0°C to 60°C 0°C to 60°C
Without fan tray 0°C to 50°C N/A 0°C to 50°C N/A
Power Requirements
RX7i +5 Vdc 3.2 A nominal 4.5 A nominal 3.2 A nominal 6.8 A nominal
RX7i +12 Vdc 0.042 A nominal 0.042 A nominal 0.003 A nominal 0.003 A nominal
RX7i -12 Vdc 0.008 A nominal 0.008 A nominal 0.003 A nominal 0.003 A nominal
Battery Battery Battery Battery
Memory Backup Mechanism11
see GFK-2741 see GFK-2741 see GFK-2741 see GFK-2741
Firmware Upgrade
CPU Firmware Upgrade Mechanism <--------------------------------WinLoader/Serial Port------------------------------------>
Indirect Backplane Module Upgrade37 <--------------------------------WinLoader/Serial Port------------------------------------>
Program Portability
CPE010, CPE020,
Direct Import (with limitations) CPE010 CPE010, CPE020
CPE030
37 The ability of the RX7i module to accept a firmware update is dependent on that particular module. See related module specification for details.


Program Storage
Battery-backed RAM11 10 Mbytes 10 Mbytes 64 Mbytes 64 Mbytes
Non-Volatile Flash 10 Mbytes 10 Mbytes 64 Mbytes 64 Mbytes
Battery Life Expectancy, RAM Backup11 See GFK-2741 See GFK-2741 See GFK-2741 See GFK-2741
Programming Capabilities
Max Number of Program Blocks 512 512 512 512
Program Block Max Size 128 KB 128 KB 128 KB 128 KB
Discrete Reference Memory (%I, %Q)15 32 Kbits 32 Kbits 32 Kbits 32 Kbits
Analog Reference Memory (%AI, %AQ)15 32 Kwords 32 Kwords 32 Kwords 32 Kwords
Bulk Reference Memory (%W)15 Up to max user RAM Up to max user RAM Up to max user RAM Up to max user RAM
Managed Memory (Symbolic + I/O Variables)15,16 up to 10 Mbytes up to 10 Mbytes up to 10 Mbytes up to 10 Mbytes

Floating Point y y y y
Ladder Diagram (LD) y y y y
Function Block Diagram (FBD) y y y y
Structured Text (ST) y y y y
PID Built-In Function Block y y y y
"C" Language External Blocks y y y y


Communications
10BaseT/100BaseT RJ45 10BaseT/100BaseT x2 10BaseT/100BaseT x2 10BaseT/100BaseT x2 10BaseT/100BaseT x2
Advanced User Parameters (AUP file) config Y Y Y Y
RS-232 9-pin D-conn x1 9-pin D-conn x1 9-pin D-conn x1 9-pin D-conn x1
RS-485 15-pin D-conn x1 15-pin D-conn x1 15-pin D-conn x1 15-pin D-conn x1
Station Manager Port (dedicated RS-232) 38 9-pin D-conn x1 9-pin D-conn x1 9-pin D-conn x1 9-pin D-conn x1
Protocols
Modbus RTU Slave Y Y Y Y
SNP Slave Y Y Y Y
Serial I/O Y Y Y Y
SRTP (# simultaneous server connections) up to 16 up to 16 up to 16 up to 16
Web-server (http) and FTP connections up to 16 up to 16 up to 16 up to 16
Ethernet Global Data (EGD)20 Y Y Y Y
Number of EGD Exchanges (max)21 255 255 255 255
Selective Consumption of EGD Y Y Y Y
Remote Station Manager over UDP Y Y Y Y
Station Manager over Serial Comm Port Y Y Y Y
38 [Optional] Serial Port cable: IC200CBL001


Time-of-Day Clock
Time-of-Day Clock Accuracy (@60°C) ±9 secs/day ±9 secs/day ±2 secs/day ±2 secs/day
Elapsed Time Clock (internal timing) accuracy ±0.01% max ±0.01% max ±0.01% max ±0.01% max
Simple Network Time Protocol (SNTP) accuracy to timestamp ±2 ms ±2 ms ±2 ms ±2 ms
RTC Battery Backup39 Y Y Y Y

RTC Battery Life expectancy See GFK-2741 See GFK-2741 See GFK-2741 See GFK-2741
Redundancy Features Model CRE020 Only Model CRE030 Only Model CRE040 Only
Single bit correcting & Single bit correcting & Single bit correcting &
Memory Error Checking and Correction (ECC)
Multiple bit checking Multiple bit checking Multiple bit checking
Switchover Time (max)40 1 logic scan 1 logic scan 1 logic scan

Switchover Time (min)40 3.133 ms 3.133 ms 3.133 ms
Max data in redundancy transfer list41 2 Mbytes 2 Mbytes 2 Mbytes
Redundant Synchronized Links Supported RMX128 x2 max RMX128 x2 max RMX128 x2 max
Environmental See GFK-2223 App A See GFK-2223 App A See GFK-2223 App A See GFK-2223 App A
39 Same battery as for memory backup

40 Switchover time is defined as the time from failure detection until backup CPU is active in a redundancy system.
41 Symbolic variable and Reference data can be exchanged between redundancy controllers, up to the stipulated limit.

2.3.1 CPE030/CRE030 and CPE040/CRE040

2.3.1.1 Serial Ports CPE030/CRE030 & CPE040/CRE040
Each CPU has three independent, on-board serial ports, accessed by
connectors on the front of the module. COM1 and COM2 provide serial
interfaces to external devices; either can be used for firmware upgrades. The
third serial port is a dedicated Ethernet Station Manager port. For serial port pin
assignments, electrical isolation and details on serial communications, refer to
Chapter 5.
2.3.1.2 Ethernet Ports CPE030/CRE030 & CPE040/CRE040
Two RJ45 ports support Ethernet communications. Refer to RX7i Embedded
Ethernet Interface for details.
2.3.1.3 Indicators CPE030/CRE030 & CPE040/CRE040
Seven CPU LEDs indicate the operating status of various CPU functions.
Figure 21:
CPE040 Front
View
LED State CPU Operating State
On Blinking Off


functioning properly.
may be blinking in an error code pattern, which
can be used by technical support for diagnostics.
CPU OK Blinking in CPU is in boot mode and is waiting for a firmware
RUN unison update through a serial port.
OUTS ENA
OUTS ENA On Green Output scan is enabled.
I/O FORCE On Yellow Override is active on a bit reference
(Not used by CRE030 or CRE040.)
BATTERY On Red Battery has failed or is not attached.
SYS FLT On Red CPU is in Stop/Faulted mode because a fatal fault
has occurred.
C1 (COM1) Blinking Green Signals activity on corresponding serial port.
C2 (COM2)
2.3.1.4 Error Checking and Correction, IC698CRE030 and IC698CRE040

Redundancy CPUs are shipped with error checking and correction (ECC) enabled. Enabling ECC
results in slightly slower system performance, primarily during power-up, because it uses an extra
eight bits that must be initialized. If you upgrade the firmware on a non-redundancy CPU model to
support redundancy, you must set the ECC jumper to the enabled state as described in the
installation instructions provided with the upgrade kit.
Note: Multiple Recoverable Memory Error faults may be generated when a single-bit ECC error is
detected. When a single-bit ECC error is detected, the value presented to the microprocessor
is corrected. However, the value stored in RAM is not corrected until the next time the
microprocessor writes to that RAM location.

2.3.2 CPE010, CPE020 and CRE020

2.3.2.1 Serial Ports CPE010, CPE020 & CRE020
Each CPU has three independent, on-board serial ports, accessed by connectors
on the front of the module. COM1 and COM2 provide serial interfaces to external
devices; either can be used for firmware upgrades. The third on-board serial port
is a dedicated Ethernet Station Manager port. For serial port pin assignments,
electrical isolation and details on serial communications, refer to Chapter 5.
2.3.2.2 Ethernet Ports CPE010, CPE020 & CRE020
Two RJ45 ports support Ethernet communications. Refer to RX7i Embedded
Ethernet Interface for details.
2.3.2.3 CPU Indicators CPE010, CPE020 & CRE020
Three CPU LEDs indicate the operating status of various CPU functions.
Figure 22:
CPE010 Front
View

LED State CPU Operating State

On Blinking Off
OK On Green CPU has passed its power-up diagnostics and is
functioning properly.
Off CPU problem. EN and RUN LEDs may be blinking
in an error code pattern, which can be used by
technical support for troubleshooting. This
condition and any error codes should be
reported to your technical support
representative.
OK Blinking in unison CPU is in boot mode and is waiting for a
RUN firmware update through a serial port.
ENA
RUN On Green CPU is in RUN Mode
ENA On Green Output scan is enabled.
C1 (COM1) Blinking Green Signals activity on corresponding serial port.
C2 (COM2)
2.3.2.4 Error Checking and Correction, IC698CRE020

Redundancy CPUs are shipped with error checking and correction (ECC) enabled. Enabling ECC
results in slightly slower system performance, primarily during power-up, because it uses an extra
eight bits that must be initialized. If you upgrade the firmware on the non-redundancy CPU model
IC698CPE020 to support redundancy, you must set the ECC jumper to the enabled state as described
in the installation instructions provided with the upgrade kit.
The CRE020 performance measurements provided in Appendix A were taken with ECC enabled.

2.3.3 RX7i Embedded Ethernet Interface

2.3.3.1 Ethernet Ports
The RX7i embedded Ethernet Interface provides two RJ45 Ethernet ports. Either or both of these ports
may be connected to other Ethernet devices. Each port automatically senses the data rate (10 Mbps
or 100 Mbps), communication mode (half-duplex or full-duplex), and cabling arrangement (straight-
through or crossover) of the attached link. For Ethernet port pin assignments, refer to Chapter 5. See
also Establishing Initial Ethernet Communications, Section 3.4.1.
For details on Ethernet communications, refer to the following manuals:
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224
PACSystems TCP/IP Ethernet Communications Station Manager User Manual, GFK-2225
Caution
The two ports on the Ethernet Interface must not be
connected, directly or indirectly to the same device. The hub
or switch connections in an Ethernet network must form a
tree; otherwise duplication of packets may result.
2.3.3.2 Ethernet Interface Indicators

The Ethernet Interface indicators consist of seven light emitting diodes (LEDs). All are single-color
green LEDs controlled by the Ethernet interface.
 Ethernet Interface OK (EOK)
 LAN online (LAN)
 Status (STAT)
 Two activity LEDS (LINK)
 Two speed LEDS (100)
The EOK, LAN, and STAT LEDs are grouped together and indicate the status of the Ethernet interface.
Each Ethernet port has two green LED indicators, LINK and 100.
 The LINK LED indicates the network link status and activity. This LED is illuminated when the
link is physically connected and blinks when traffic is detected at the port. Note that traffic at
the port does not necessarily mean that traffic is present at the Ethernet interface, since the
traffic may be going between ports of the switch.
 The 100 LED indicates the network data speed (10 or 100 Mbps). This LED is illuminated if the
network connection is 100 Mbps.
LED operation is described in the following tables.

Ethernet LED Operation

LED State
Ethernet Operating State
On Blinking Off
EOK Blink error code Hardware Failure
LAN Off
STAT Off
EOK Fast Blink Performing Diagnostics
LAN Off
STAT Off
EOK Slow Blink Waiting for Ethernet configuration from CPU
LAN Off
STAT Off
EOK Slow Blink† Waiting for IP Address
LAN On/Traffic/Off
STAT Slow Blink†
(† EOK and STAT blink in unison)
EOK On Operational
LAN On/Traffic/Off
STAT On/Off
EOK Slow Blink‡ Software Load
LAN Slow Blink‡
STAT Slow Blink‡
(‡ All LEDs blink in unison)

EOK LED Operation

The EOK LED indicates whether the Ethernet interface is able to perform normal operation. This LED is
on for normal operation and blinks for all other operations. When a hardware or unrecoverable
runtime failure occurs, the EOK LED blinks a two-digit error code identifying the failure. The LED first
blinks to indicate the most significant error digit, then after a brief pause blinks again to indicate the
least significant error digit. After a long pause the error code display repeats.
EOK LED Blink Codes for Ethernet Hardware Failures
Blink Code Description
0x12 Undefined or Unexpected Interrupt.
0x13 Timer failure during power up diagnostics.
0x14 DMA failure during power up diagnostics.
0x21 RAM failure during power up diagnostics.
0x22 Stack error during power up diagnostics.
0x23 Shared Memory Interface error during power up diagnostics.
0x24 Firmware CRC (cyclic redundancy check) error during power up or Factory Test.42
0x25 Run time exception
0x31 Undefined instruction or divide by zero
0x32 Software interrupt
0x33 Instruction pre-fetch abort
0x34 Data abort
0x35 Unexpected Runtime IRQ
0x36 Unexpected Runtime FIQ (fast interrupt request)
0x37 Reserved Exception or branch through zero
42 CRC error or software error during normal operation causes Ethernet restart.

LAN LED Operation

The LAN LED indicates access to the Ethernet network. During normal operation, and while waiting
for an IP address, the LAN LED blinks to indicate network activity. This LED remains on when the
Ethernet interface is not actively accessing the network but the network is available, and it is off if
network access is not available. The definition of the network being available as indicated by this LED
is that the Ethernet physical interface is available and one or both of the Ethernet ports is connected
to an active network.
STAT LED Operation
The STAT LED indicates the condition of the Ethernet interface in normal operational mode. If the
STAT LED is off, an event has been entered into the exception log and is available for viewing via the
Station Manager interface. The STAT LED is on during normal operation when no events are logged.
In the other states, the STAT LED is either off or blinking and helps define the operational state of the
module.
Ethernet Port LEDs (100 Mb/Speed and LINK/Activity) Operation
Each of the two Ethernet ports has two green LED indicators, 100 and LINK.
The 100 LED indicates the network data speed (10 Mbps or 100 Mbps. This LED is illuminated if the
network connection is 100 Mbps.
The LINK LED indicates the network link status and activity. This LED is illuminated when the link is
physically connected and blinks when traffic is detected at the port. Note that traffic at the port does
not necessarily mean that traffic is present at the Ethernet interface, since the traffic may be going
between ports of the switch.

2.3.3.3 Ethernet Restart Pushbutton

The Ethernet Restart pushbutton is used to manually restart the Ethernet firmware without power
cycling the entire control system. It is recessed to prevent accidental operation. The restart does not
occur until the pushbutton is released.
The type of restart behavior is selected by the length of time that the pushbutton is depressed. The
pushbutton-controlled restart operations are listed in the following table, along with the LED
indications for each. In all cases, the EOK, LAN and STAT LEDs briefly turn on in unison as an LED test.
The Ethernet port LEDs are not affected by a manual restart of the Ethernet firmware.
Restart Operation Depress Ethernet Restart Ethernet LEDs
pushbutton for Illuminated
Normal restart Less than 5 seconds EOK, LAN, STAT
Restart without Ethernet plug-in 5 to 10 seconds LAN, STAT
applications
Restart into Firmware Update More than 10 seconds STAT
operation
Normal Restart
When the Ethernet Restart pushbutton is pressed for less than 5 seconds, the Ethernet interface will
restart into normal operation.
Restart without Ethernet Plug-in Applications
When the Restart pushbutton is pressed and held for 5 to 10 seconds, the Ethernet interface will
restart into normal operation but does not start any optional Ethernet plug-in applications. This is
typically done during troubleshooting.
Restart into Firmware Update Operation
When the Ethernet Restart pushbutton is pressed and held for more than 10 seconds, the Ethernet
interface will restart into firmware update operation. This is typically done during troubleshooting to
bypass possibly invalid firmware and allow valid firmware to be loaded using WinLoader.
Until the firmware update actually begins, you can manually exit the firmware update and restart
with the existing firmware by pressing the Ethernet Restart pushbutton again.

Chapter 3 CPU Configuration
The PACSystems CPU and I/O system is configured using Proficy Machine Edition (PME) Logic
Developer-PLC programming software.
The CPU verifies the physical module and rack configuration at power-up and periodically during
operation. The physical configuration must be the same as the programmed configuration.
Differences are reported to the CPU alarm processor for configured fault response. Refer to the
Machine Edition Logic Developer-PLC Getting Started Manual, GFK-1918 and the online help for a
description of configuration functions.
Note: A CPE020, CPE030 or CPE040 can be converted to the corresponding redundancy CPU
(CRE020, CRE030 or CRE040) by installing different firmware and moving a jumper. Detailed
instructions are included in the firmware upgrade kit for the redundancy CPU.
This chapter covers:
■ Configuring the CPU
■ Configuration Parameters
■ Storing (Downloading) Hardware Configuration
■ Configuring the Embedded Ethernet Interface

Chapter 3. CPU Configuration
3.1 Configuring the CPU

To configure the CPU using the Logic Developer-PLC programming software, do the following:
1. In the Project tab of the Navigator, expand your
PACSystems Target, the hardware configuration, and
the main rack (Rack 0).
2. Right click the CPU slot and choose Configure. The
Parameter Editor window displays the CPU
parameters.
Note: An RX7i CPU must be installed in Rack 0, Slot
1. A double-wide RX3i CPU occupies two slots
and can be installed in any pair of slots in
Rack 0 except the two highest numbered lots
in the rack. The single-wide CPE305 RX3i CPU
requires one slot and can be installed in any
slot in RX3i Rack 0, except the highest
Figure 23: PME Expansion of PACSystems
numbered slot or slot 0.
Target
3. To edit a parameter value, click the desired tab, then
click in the appropriate Values field. For information on
these fields, refer to Configuration Parameters.
4. Store the configuration to the Controller so these
settings can take effect. For details, see Storing
(Downloading) Hardware Configuration.
Note: If available, the embedded Ethernet Interface is displayed in a sub-slot of the CPU. For
configuration details, refer to Configuring the Embedded Ethernet Interface.

3.2 Configuration Parameters

3.2.1 Settings Parameters
These parameters specify basic operating characteristics of the CPU. For details on how these
parameters affect CPU operation, refer to PACSystems RX7i and RX3i CPU Programmer’s Reference
Manual, GFK-2950 Chapter 2.
Settings Parameters
Passwords Specifies whether passwords are Enabled or Disabled. Default: Enabled.
Note: If Enhanced Security43 is enabled in the target properties, the Passwords
setting will be Enabled and read-only, and the Access Control tab appears.
When passwords are disabled, they cannot be re-enabled without clearing PLC
memory.
Stop-Mode I/O Specifies whether the I/O is scanned while the PLC is in STOP Mode. Default: Disabled.
Scanning (Always Disabled for Redundancy CPU.)
Note: This parameter corresponds to the I/O ScanStop parameter on a Series 90-
70 PLC.
Watchdog Timer (Denominated in ms, set in 10ms increments.) Requires a value that is greater than
(ms) the program sweep time.
The software watchdog timer is designed to detect failure to complete sweep
conditions. The CPU restarts the watchdog timer at the beginning of each sweep. The
watchdog timer accumulates time during the sweep. The software watchdog timer is
useful in detecting abnormal operation of the application program, which could
prevent the PLC sweep from completing within the watchdog time period.
Valid range: 10 ms through 2550 ms, in increments of 10 ms.
Default: 200.
For details on setting the watchdog timer in a CPU redundancy system, refer to the
PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
Logic/Configuratio Specifies the location/source of the logic and configuration data that is to be used (or
n Power-up Source loaded/copied into RAM) after each power up.
Choices: Always RAM, Always Flash, Conditional Flash.
Default: Always RAM.
Data Power-up Specifies the location/source of the reference data that is to be used (or
Source loaded/copied into RAM) after each power up.
Choices: Always RAM, Always Flash, Conditional Flash.
Default: Always RAM.
43 For availability, refer to the Important Product Information document for the CPU firmware version that you are using.

Settings Parameters
RUN/STOP Switch Enables or disables the physical operation of the RUN/STOP Switch.
Choices:
Enabled: Enables you to use the physical switch on the PLC to switch the PLC into
STOP Mode or from STOP Mode into RUN Mode and clear non-fatal faults.
Disabled: Disables the physical RUN/STOP Switch on the PLC.
Default: Enabled.
Note: If COM1 and COM2 are configured for any protocol other than RTU Slave or
SNP Slave, the RUN/STOP Switch should not be disabled without first must
making sure that there is a way to stop the CPU, or take control of the CPU
through another device such as an Ethernet interface. If the CPU can be set
to STOP Mode, it will switch the protocol from Serial I/O to the STOP Mode
protocol (default is RTU Slave). For details on STOP Mode settings, refer to
COM1 and COM2 Parameters.
This applies to COM1 on the CPE305, which has only one serial port.
This note does not apply to CPUs which have no serial ports.
Memory Protection Enables or disables the Memory Protect feature associated with the RUN/STOP
Switch Switch.
Choices:
Enabled: Memory Protect is enabled, which prevents writing to program memory and
configuration and forcing or overriding discrete data.
Disabled: Memory Protect is disabled.
Default: Disabled.
Power-up Mode Selects the CPU mode to be in effect immediately after power-up.
Choices: Last, Stop, Run.
Default: Last (the mode it was in when it last powered down).
Note: If the battery or Energy Pack is missing or has failed and if Logic/
Configuration Power-up Source is set to Always RAM, the CPU powers up in
STOP Mode regardless of the setting of the Power-up Mode parameter.
Modbus Address Specifies the type of memory mapping to be used for data transfer between Modbus
Space Mapping TCP/IP clients and the PACSystems controller.
Type Choices:
Disabled: The Disabled setting is intended for use in systems containing Ethernet
firmware that does not support Modbus TCP.
Standard Modbus Addressing: Causes the Ethernet firmware to use the standard
map, which is displayed on the Modbus TCP Address Map tab.
Default: Disabled
For details on the PACSystems implementation of Modbus/TCP server, refer to
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
Universal Serial Bus RX3i CPE305/CPE310/CPE330/CPE400 CPUs only. Enables or disables the USB port
for use with RDSD (Removable Data Storage Devices). The USB port is enabled by
default in the CPE305/CPE310/CPE330 and in the hardware configuration.
If a CPU310 configuration is stored to a CPE310, the USB port will be enabled.

3.2.2 Modbus TCP Address Map

This read-only tab displays the standard mapping assignments between Modbus address space and
the CPU address space. Ethernet modules and daughterboards in the PACSystems controller use
Modbus-to-PLC address mapping based on this map.
Modbus The Modbus protocol uses five reference table designations:

Register 0xxxx Coil Table. Mapped to the %Q table in the CPU.
1xxxx Input Discrete Table. Mapped to the %I table in the CPU.
3xxxx Input Register Table. Mapped to the %AI register table in the CPU.
4xxxx Holding Register Table. Mapped to the %R table in the CPU.
6xxxx File Access Table. Mapped to the %W table in the CPU.
Start Address Lists the beginning address of the mapped region.
End Address Lists the ending address of the mapped region. For word memory types (%AI, %R and
%W) the highest address available is configured on the Memory tab.
PLC Memory Lists the memory type of the mapped region.
Length Displays the length of the mapped region.

3.2.3 Scan Parameters

These parameters determine the characteristics of CPU sweep execution.
Scan Parameters
Sweep Mode The sweep mode determines the priority of tasks the CPU performs during the sweep
and defines how much time is allotted to each task. The parameters that can be
modified vary depending on the selection for sweep mode.
The Controller Communications Window, Backplane Communications Window, and
Background Window phases of the PLC sweep can be run in various modes, based on
the PLC sweep mode.
Choices:
 Normal mode: The PLC sweep executes as quickly as possible. The overall
PLC sweep time depends on the logic program and the requests being
processed in the windows and is equal to the time required to execute the
logic in the program plus the respective window timer values. The window
terminates when it has no more tasks to complete. This is the default value.
 Constant Window mode: Each window operates in a Run-to-Completion
mode. The PLC alternates among three windows for a time equal to the
value set for the window timer parameter. The overall PLC sweep time is
equal to the time required to execute the logic program plus the value of the
window timer. This time may vary due to sweep-to-sweep differences in the
execution of the program logic.
 Constant Sweep mode: The overall PLC sweep time is fixed. Some or all of
the windows at the end of the sweep might not be executed. The windows
terminate when the overall PLC sweep time has reached the value specified
for the Sweep Timer parameter.
Logic Checksum The number of user logic words to use as input to the checksum algorithm each sweep.
Words Valid range: 0 through 32760, in increments of 8.
Default: 16.
Controller (Available only when Sweep Mode is set to Normal.) Execution settings for the Controller
Communication Communications Window.
Window Mode Choices:
 Complete: The window runs to completion. There is no time limit.
 Limited: Time sliced. The maximum execution time for the Controller
Communications Window per scan is specified in the Controller
Communications Window Timer parameter.
Default: Limited.
Note: This parameter corresponds to the Programmer Window Mode parameter on a
Series 90-70 PLC.

Scan Parameters
Controller (Available only when Sweep Mode is set to Normal. Read-only if the Controller
Communications Communications Window Mode is set to Complete.) The maximum execution time for
Window Timer the Controller Communications Window per scan. This value cannot be greater than the
(ms) value for the watchdog timer.
The valid range and default value depend on the Controller Communications Window
Mode:
 Complete: There is no time limit.
 Limited: Valid range: 0 through 255ms. Default: 10.
Note: This parameter corresponds to the Programmer Window Timer parameter on a
Series 90-70 PLC.
Backplane (Available only when Sweep Mode is set to Normal.) Execution settings for the Backplane
Communication Communications Window.
Window Mode Choices:
Complete: The window runs to completion. There is no time limit.
Limited: Time sliced. The maximum execution time for the Backplane Communications
Window per scan is specified in the Backplane Communications Window Timer
parameter.
Default: Complete.
Backplane (Available only when Sweep Mode is set to Normal. Read-only if the Backplane
Communications Communications Window Mode is set to Complete.) The maximum execution time for
Window Timer the Backplane Communications Window per scan. This value can be greater than the
(ms) value for the watchdog timer.
The valid range and the default depend on the Backplane Communications Window
Mode:
 Complete: There is no time limit. The Backplane Communications Window
Timer parameter is read-only.
 Limited: Valid range: 0 through 255ms. Default: 255. (10ms for Redundancy
CPUs.)
Background (Available only when Sweep Mode is set to Normal.) The maximum execution time for
Window the Background Communications Window per scan. This value cannot be greater than
Timer (ms) the value for the watchdog timer.
Valid range: 0 through 255
Default: 0 (5ms for Redundancy CPUs)
Sweep Timer (Available only when Sweep Mode is set to Constant Sweep.) The maximum overall PLC
(ms) scan time. This value cannot be greater than the value for the watchdog timer.
Some or all of the windows at the end of the sweep might not be executed. The
windows terminate when the overall PLC sweep time has reached the value specified
for the Sweep Timer parameter.
Valid range: 5 through 2550 ms, in increments of 5 ms. If the value entered is not a
multiple of 5ms, it is rounded to the next highest multiple of 5ms.
Default: 100.

Scan Parameters
Window Timer (Available only when Sweep Mode is set to Constant Window.) The maximum combined
(ms) execution time per scan for the Controller Communications Window, Backplane
Communications Window, and Background Communications Window. This value
cannot be greater than the value for the watchdog timer.
Valid range: 3 through 255, in increments of 1.
Default: 10.
Number of Last (Available only for CPUs with firmware version 1.5 and greater.)
Scans The number of scans to execute after the PACSystems CPU receives an indication that a
transition from RUN Mode to STOP Mode should occur. (Used for STOP and STOP-Fault,
but not STOP-Halt.)
Choices: 0, 1, 2, 3, 4, 5.
Default:
0 when creating a new PACSystems target.
0 when converting a Series 90-70 target to a PACSystems target.
1 when converting a Series 90-30 target to a PACSystems target.

3.2.4 Memory Parameters

The PACSystems user memory contains the application program, hardware configuration (HWC),
registers (%R), bulk memory (%W), analog inputs (%AI), analog outputs (%AQ), and managed memory.
Managed memory consists of allocations for symbolic variables and I/O variables. The symbolic
variables feature allows you to create variables without having to manually locate them in memory.
An I/O variable is a symbolic variable that is mapped to the inputs and outputs of a module in the
hardware configuration. For details on using symbolic variables and I/O variables, refer to
The amount of memory allocated to the application program and hardware configuration is
automatically determined by the actual program (including logic C data, and %L and %P), hardware
configuration (including EGD and AUP), and symbolic variables created in the programming software.
The rest of the user memory can be configured to suit the application. For example, an application
may have a relatively large program that uses only a small amount of register and analog memory.
Similarly, there might be a small logic program but a larger amount of memory needed for registers
and analog inputs and outputs. Note that the content of reference memory is cleared any time the
size of reference memory is changed.
Appendix B provides a summary of items that count against user memory.
3.2.4.1 Calculation of Memory Required for Managed Memory
The total number of bytes required for symbolic and I/O variables is calculated as follows:
[((number of symbolic discrete bits) × 3) / (8 bits/byte)]
+ [((number of I/O discrete bits) × Md) / (8 bits/byte)]
+ [(number of symbolic words × (2 bytes/word)]
+ [(number of I/O words) × (Mw bytes/word)]
Md = 3 or 4. The number of bits is multiplied by 3 to keep track of the force, transition, and value of
each bit. If point faults are enabled, the number of I/O discrete bits is multiplied by 4.
Mw = 2 or 3. There are two 8-bit bytes per 16-bit word. If point faults are enabled, the number of
bytes is multiplied by 3 because each I/O word requires an extra byte.
3.2.4.2 Calculation of Total User Memory Configured
The total amount of configurable user memory (in bytes) configured in the CPU is calculated as
follows:
Total managed memory (bytes)
+ total reference words × (2 bytes/word)
+ [if Point Faults are enabled] (total words of %AI memory + total words of %AQ
memory) × (1 byte / word)
+ [if Point Faults are enabled] (total bits of %I memory + total bits of %Q memory)
/ 8 bits/byte)
Note: The total number of reference points is considered system memory and is not counted
against user memory.

3.2.4.3 Memory Allocation Configuration

Memory Parameters
Reference Points
%I Discrete Input, %Q Discrete The upper limit for the range of each of these memory types. Read only.
Output, %M Internal Discrete, %S
System, %SA System, %SB System,
%SC System, %T Temporary
Status, %G Genius Global
Total Reference Points Read only. Calculated by the programming software.
Reference Words
%AI Analog Input Valid range: 0 through 32,640 words.
Default: 64
%AQ Analog Output Valid range: 0 through 32,640 words.
Default: 64
%R Register Memory Valid range: 0 through 32,640 words.
Default: 1024.
%W Bulk Memory Valid range: 0 through maximum available user RAM.
Increments of 2048 words.
Default: 0.
Total Reference Words Read only. Calculated by the programming software.
Managed Memory
Symbolic Discrete (Bits) The configured number of bits reserved for symbolic discrete variables.
Valid range: 0 through 83,886,080 in increments of 32768 bits.
Default: 32,768.
Symbolic Non-Discrete (Words) The configured number of 16-bit register memory locations reserved for
symbolic non-discrete variables.
Valid range: 0 through 5,242,880 in increments of 2048 words.
Default: 65,536.
I/O Discrete (Bits) The configured number of bits reserved for discrete IO variables.
Valid range: 0 through 83,886,080 in increments of 32768 bits.
Default: 0
I/O Non-Discrete (Words) The configured number of 16-bit register memory locations reserved for
non-discrete IO variables.
Valid range: 0 through 5,242,880 in increments of 2048 words.
Default: 0
Total Managed Memory Required Read only. See Calculation of Memory Required for Managed
(Bytes) Memory.
Total User Memory Required Read only. See Calculation of Total User Memory Configured.
(Bytes)

Memory Parameters
Point Fault References The Point Fault References parameter must be enabled if you want to
use fault contacts in your logic. Assigning point fault references causes
the CPU to reserve additional memory.
When you download both the HWC and the logic to the PLC, the
download routine checks if there are fault contacts in the logic and if
there are, it checks if the HWC to download has the Point Fault
References parameter set to Enabled. If the parameter is Disabled, an
error is displayed in the Feedback Zone.
When you download only logic to the PLC, the download routine checks if
there are fault contacts in the logic and if there are, it checks if the HWC
on the PLC has the Point Fault References parameter set to Enabled. If
the parameter is Disabled, an error is displayed in the Feedback Zone.
3.2.5 Fault Parameters

You can configure each fault action to be either diagnostic or fatal.
A diagnostic fault does not stop the PLC from executing logic. It sets a diagnostic variable and is
logged in a fault table.
A fatal fault transitions the PLC to the Stop Faulted mode. It also sets a diagnostic variable and is
logged in a fault table.
Fault Parameters
Loss of or Missing (Fault group 1.) When BRM failure or loss of power loses a rack or when a configured
Rack rack is missing, system variable #LOS_RCK (%SA12) turns ON. (To turn it OFF, fix the
hardware problem and cycle power on the rack.)
Default: Diagnostic.
Loss of or Missing (Fault group 2.) When a Bus Controller stops communicating with the PLC or when a
I/O Controller configured Bus Controller is missing, system variable #LOS_IOC (%SA13) turns ON. (To
turn it OFF, replace the module and cycle power on the rack containing the module.)
Loss of or Missing (Fault group 3.) When an I/O module stops communicating with the PLC CPU or a
I/O Module configured module is missing, system variable #LOS_IOM (%SA14) turns ON. (To turn it
OFF, replace the module and cycle power on the rack containing the module.)
Loss of or Missing (Fault group 4.) When an option module stops communicating with the PLC CPU or a
Option Module configured option module is missing, system variable #LOS_SIO (%SA15) turns ON. (To
turn it OFF, replace the module and cycle power on the rack containing the module.)
System Bus Error (Fault group 12.) When a bus error occurs on the backplane, system variable
#SBUS_ER (%SA32) turns ON. (To turn it OFF, cycle power on the main rack.)
Default: Fatal.
I/O Controller or (Fault group 9.) When a Bus Controller reports a bus fault, a global memory fault, or an
I/O Bus Fault IOC hardware fault, system variable #IOC_FLT (%SA22) turns ON. (To turn it OFF, cycle
power on the rack containing the module when the configuration matches the
hardware after a download.)

Fault Parameters
System (Fault group 11.) When a configuration mismatch is detected during system power-up
Configuration or during a download of the configuration, system variable #CFG_MM (%SA9) turns
Mismatch ON. (To turn it OFF, power up the PLC when no mismatches are present or download a
configuration that matches the hardware.)
This parameter determines the fault action when the CPU is not running. If a system
configuration mismatch occurs when the CPU is in RUN Mode, the fault action will be
Diagnostic. This prevents the running CPU from going to STOP/FAULT mode. To
override this behavior, see Configuring the CPU to Stop Upon the Loss of a Critical
Module.
Default: Fatal.
Fan Kit Failure (Fault group 0x17.) When a fault is detected in the Smart Fan kit, system variable
#FAN_FLT (%SA7) turns ON. (To turn a fan kit fault OFF, clear the Controller fault table
or reset the PLC.)
Recoverable Local Redundancy CPUs only. (Fault group 38) Determines whether a single-bit ECC error
Memory Error causes the CPU to stop or allows it to continue running.
Choices: Diagnostic, Fatal.
Note: When a multiple-bit ECC error occurs, a Fatal Local Memory Error fault (error
code 169) is logged in the CPU Hardware Fault Group (group number 13).
CPU Over (Fault group 24, error code 1.) When the operating temperature of the CPU exceeds
Temperature the normal operating temperature, system variable #OVR_TMP (%SA8) turns ON. (To
turn it OFF, clear the Controller Fault Table or reset the PLC.)
Controller Fault (Read-only.) The maximum number of entries in the Controller Fault Table.
Table Size Value set to 64.
I/O Fault Table (Read-only.) The maximum number of entries in the I/O Fault Table.
Size Value set to 64.
3.2.5.1 Configuring the CPU to Stop Upon the Loss of a Critical Module
In some cases, you may want to override the RUN Mode behavior of the System Configuration
Mismatch fault. A given module may be critical to the PLC’s ability to properly control a process. In
this case, if the module fails then it may be better to have the CPU go to STOP Mode, especially if the
CPU is acting as a backup unit in a redundant system.
One way to cause the CPU to stop is to set the configured action for a Loss-of-Module fault to Fatal
so that the CPU stops if a module failure causes a loss-of-module fault. The correct loss-of-module
fault must be chosen for the critical module of interest: I/O controller, I/O module, and Option
module. The Ethernet communications module is an example of an Option module.
This approach has a couple of disadvantages. First, it applies to all modules of that category, which
may include modules that are not critical to the process. Second, it relies on the content of the fault
table. If the table is cleared via program logic or user action, the CPU will not stop.
In systems that use Ethernet Network Interface Units (ENIUs) for remote I/O, a critical module of
interest may be the Ethernet module that provides the network connection to the ENIU. Other
techniques can be used to provide a more selective response to an Ethernet module failure than the
Loss-of-Option module fault. One technique is to use application logic to monitor the Ethernet
Interface Status bits, which are described in Monitoring the Ethernet Interface Status Bits in the
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224. If the logic

determined that a critical Ethernet module was malfunctioning, it could execute SVC_REQ #13 to
stop the CPU.
Since the ENIU uses Ethernet Global Data to communicate with the PACSystems CPU, another
selective technique is to monitor the Exchange Status Words to determine the health of individual
EGD exchanges. For details on this status word, refer to Exchange Status Word Error Codes in
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224. Because the types
of errors indicated by the exchange status word may be temporary in nature, stopping the CPU may
not be an appropriate response for these errors. Nevertheless, the status could be used to tailor the
response of the application to changing conditions in the EGD network.
In some cases, the critical module may reside in an expansion rack. In that case, in addition to the
loss-of-module fault, it is recommended to set the Loss-of-Rack fault to Fatal. Then if the rack fails or
loses power, the CPU will go to STOP Mode.

3.2.6 Redundancy Parameters (Redundancy CPUs Only)

These parameters apply only to redundancy CPUs or to those CPUs where the optional redundancy
features have been activated. For details on configuring CPU for redundancy, refer to the
PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
3.2.7 Transfer List
These parameters apply only to redundancy CPUs. For details on configuring CPU for redundancy,
refer to the PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
3.2.8 COM1 and COM2 Parameters
These parameters configure the operating characteristics of the CPU serial ports. COM1 and COM2
have the same set of configuration parameters. The protocol (Port Mode) determines the parameters
that can be set for each port.
Port Parameters
Port Mode The protocol to execute on the serial port. Determines the list of parameters displayed on the
Port tab. Only the parameters required by the selected protocol are displayed.
Choices:
 RTU Slave mode: Reserved for the use of the Modbus RTU Slave protocol. This mode
also permits connection to the port by an SNP master, such as the WinLoader utility
or the programming software.
 Message mode: The port is open for user logic access. This mode enables C
language blocks to perform serial port I/O operations via the C Runtime Library
functions.
 Available: The port is not to be used by the PLC firmware. (The CPE305 does not
support this selection.)
 SNP Slave: Reserved for the exclusive use of the SNP slave. This mode permits
connection to the port by an SNP master, such as the WinLoader utility or the
programming software.
 Serial I/O: Enables you to perform general-purpose serial communications by using
COMMREQ functions.
Default: RTU Slave.
Note: If both serial ports are configured for any protocol other than RTU Slave or SNP Slave,
the RUN/STOP Switch should not be disabled without first making sure that there is a
way to stop the CPU, or take control of the CPU through another device such as the
Ethernet module. The Serial I/O protocol is only active when the CPU is in RUN Mode. If
the CPU can be set to STOP Mode, it will switch the protocol from Serial I/O to the STOP
Mode protocol (default is RTU Slave). If an SNP Master, such as the programming
software in Serial mode, begins communicating on a port, the RTU protocol
automatically switches to SNP Slave. As long as the CPU can be stopped, the protocol
of the port can be auto-switched to one that enables serial programmer connection.
Refer to STOP Mode protocols.
If an Ethernet port is available, you can communicate with the CPU by connecting PME
software via the Ethernet port.

Port Parameters
Station (RTU Slave only) ID for the RTU Slave.
Address Valid range: 1 through 247.
Default: 1.
Note: You should avoid using station address 1 for any other Modbus slave in a PACSystems
control system because the default station address for the CPU is 1. The CPU uses the
default address in two situations:
1. If you power up without a configuration, the default station address of 1 is used.
2. When the Port Mode parameter is set to Message Mode, and Modbus becomes the
protocol in STOP Mode, the station address defaults to 1.
In either of these situations, if you have a slave configured with a station address of 1,
confusion may result when the CPU responds to requests intended for that slave.
Note: The least significant bit of the first byte must be 0. For example, in a station address of
090019010001, 9 is the first byte.
Data Rate (All Port Modes, except Available.) Data rate (bits per second) for the port.
Choices: 1200 Baud, 2400 Baud, 4800 Baud, 9600 Baud, 19.2k Baud, 38.4k Baud, 57.6k Baud,
115.2k Baud.
Default: 19.2k Baud.
Data Bits (Available only when Port Mode is set to Message mode or Serial I/O.) The number of bits in a
word for serial communication. SNP uses 8-bit words.
Choices: 7, 8.
Default: 8.
Flow (RTU slave, Message Mode, or Serial I/O.) Type of flow control to be used on the port.
Control Choices:
 For Serial I/O Port Mode: None, Hardware, Software (XON/XOFF).
 For all other Port Modes: None, Hardware.
Default: None.
Note: The Hardware flow-control is RTS/CTS crossed.
Parity (All Port Modes, except Available.) The parity used in serial communication. Can be changed if
required for communication over modems or with a different SNP master device.
Choices: None, Odd, Even.
Default: Odd.
Stop bits (Available only when Port Mode is set to Message Mode, SNP Slave or Serial I/O.) The number of
stop bits for serial communication. SNP uses 1 stop bit.
Choices: 1, 2.
Default: 1.
Physical (All port modes except Available.) The type of physical interface that this protocol is
Interface communicating over.
Choices:
 2-wire: There is only a single path for receive and transmit communications.
The receiver is disabled while transmitting.
 4-wire: There is a separate path for receive and transmit communications and
the transmit line is driven only while transmitting.
 4-wire Transmitter on: There is a separate path for receive and transmit
communications and the transmit line is driven continuously. Note that this
choice is not appropriate for SNP multi-drop communications, since only one
device on the multi-drop line can be transmitting at a given time.
Default: 4-wire Transmitter On.

Port Parameters
Turn (Available only when Port Mode is set to SNP Slave.) The Turn Around Delay Time is the minimum
Around time interval required between the reception of a message and the next transmission. In 2-wire
Delay Time mode, this interval is required for switching the direction of data transmission on the
(ms) communication line.
Valid range: 0 through 2550ms, in increments of 10 ms.
Default: 0.
Timeout (s) (Available only when Port Mode is set to SNP Slave.) The maximum time that the slave will wait
to receive a message from the master. If a message is not received within this timeout interval,
the slave will assume that communications have been disrupted, and then it will wait for a new
attach message from the master.
Valid range: 0 through 60 seconds.
Default: 10.
SNP ID (Available only when Port Mode is set to SNP Slave.) The port ID to be used for SNP
communications. In SNP multi-drop communications, this ID is used to identify the intended
receiver of a message. This parameter can be left blank if communication is point to point. To
change the SNP ID, click the values field and enter the new ID. The SNP ID is up to seven
characters long and can contain the alphanumeric characters (A through Z, 0 through 9) or the
underline (_).
Specify (All port modes except Available.) Determines whether you accept the default STOP Mode or set
STOP Mode it yourself.
Choices:
No: The default STOP Mode is used.
Yes: The STOP Mode parameters appear and you can select the STOP Mode. If you set the STOP
Mode to the same protocol as the RUN Mode, then the other STOP Mode parameters are read-
only and are set to the same values as for the RUN Mode.
Default: No.
STOP Mode (Available only when Specify STOP Mode is set to Yes.)
The STOP Mode protocol to execute on the serial port. If you set the STOP Mode to the same
protocol as for the RUN Mode, then the other STOP Mode parameters are read-only and are set
to the same values as for the RUN Mode.
Choices and defaults are determined by the Port Mode setting.
■ SNP Slave: Reserved for the exclusive use of the SNP slave.
■ RTU Slave: Reserved for the exclusive use of the Modbus RTU Slave protocol.
If the STOP Mode protocol is different from the Port mode protocol, you can set parameters for
the STOP Mode protocol.
If you do not select a STOP Mode protocol, the default protocol with default parameter settings
is used.
Port (RUN) Mode STOP Mode
RTU Slave Choices: SNP Slave, RTU Slave
Default: RTU Slave.
Message Mode Choices: SNP Slave, RTU Slave
Default: RTU Slave.
Available Available (Not supported on CPE305)
SNP Slave SNP Slave
Serial I/O Choices: SNP Slave, RTU Slave
Default: RTU Slave.
Note: Setting the Port Mode to RTU Slave and the STOP Mode to SNP Slave may cause loss of
programmer connection and delayed reconnection when the controller transitions
from STOP to RUN Mode. To avoid this behavior, select SNP Slave for the Port Mode and
do not specify a STOP Mode. For additional details, see RTU Slave/SNP Slave Operation
with Programmer Attached.

Port Parameters
Turn (Available only when STOP Mode is set to SNP Slave.) The Turn Around Delay Time is the
Around minimum time interval required between the reception of a message and the next transmission.
Delay Time In 2-wire mode, this interval is required for switching the direction of data transmission on the
(ms) communication line.
Valid range: 0 through 2550ms, in increments of 10 ms.
Default:
 When the STOP Mode is different from the Port Mode: 0ms.
 When the STOP Mode is the same as the Port Mode: the value is read-only and is
set to the same value as the Turn-Around Delay Time for the Port Mode.
Timeout (s) (Available only when STOP Mode is set to SNP Slave.) The maximum time that the slave will wait
to receive a message from the master. If a message is not received within this timeout interval,
the slave will assume that communications have been disrupted, and then it will wait for a new
attach message from the master.
Valid range: 0 through 60 seconds.
Default:
 When the STOP Mode is different from the Port Mode: 10 seconds.
set to the same value as the Timeout for the Port Mode.
SNP ID (Available only when STOP Mode is set to SNP Slave.) The port ID to be used for SNP
communications. In SNP multi-drop communications, this ID is used to identify the intended
receiver of a message. This parameter can be left blank if communication is point to point. To
change the SNP ID, click the values field and enter the new ID. The SNP ID is up to seven
characters long and can contain the alphanumeric characters (A through Z, 0 through 9) or the
underline (_).
Default:
 When the STOP Mode is different from the Port Mode: the default is blank.
set to the same value as the SNP ID for the Port Mode.
Station (Available only when STOP Mode is set to RTU slave.) ID for the RTU Slave.
Address Valid range: 1 through 247.
Default:
 When the STOP Mode is different from the Port Mode: 1.
set to the same value as the Station Address for the Port Mode.

3.2.9 Scan Sets Parameters

You can create multiple sets of asynchronous I/O scans, with a unique scan rate assigned to each
scan set. You can assign up to 31 scan sets for a total of 32. Scan set 1 is the standard scan set
where I/O is scanned once per sweep. Each module is assigned to a scan set during the
configuration of that module. Scan Set 1 is the default scan set.
Scan Set Parameters
Number A sequential number from 1 to 32 is automatically assigned to each scan set. Scan set 1 is
reserved for the standard scan set.
Scan Type Determines whether the scan set is enabled (as a fixed scan) or is disabled.
Choices: Disabled, Fixed Scan.
Default: Disabled.
Number of (Editable only when the Scan Type is set to Fixed Scan.) The scan rate of the scan set.
Sweeps Double-click the field, then select a value. A value of 0 prevents the I/O from being scanned.
Valid range: 0 through 64.
Default: 1.
Output (Editable only when the Number of Sweeps is non-zero.) The number of sweeps that the
Delay output scan is delayed after the input scan has occurred. Double-click on field, then select a
value.
Valid range: 0 to (number of Sweeps - 1)
Default: 0.
Description (Editable only when the Scan Type is set to Fixed Scan.) Brief description of the scan set (32
characters maximum).
3.2.10 Power Consumption Parameters

The programming software displays the power consumed by the CPU (in Amps) for each voltage
provided by the power supply.

3.2.11 Access Control

The Access Control List allows you to specify the reference address ranges that can be accessed by
non-local devices such as HMIs and other controllers. To use this feature, Enhanced Security must be
enabled in the properties of the target.
When Enhanced Security mode is enabled, any reference address range not defined cannot be
accessed by other devices. External reads and writes that do not exist in the table are rejected by the
firmware.
If overlapping memory ranges are defined, they must have the same Access level.
For symbolic variables, access control is specified by the Publish property of the variable, which
includes a Read Only and Read/Write setting.
Note: When requesting data from an external device, some drivers packetize data to optimize
communication. If a request attempts to read a value that is not published, the entire packet
will fail. A fault has been added to the fault table to help you understand a failed read/write.
After addressing the fault, you must clear the fault in order to try again.
3.2.11.1 Access Control List Settings
Memory The memory area in which the reference address range is defined.
Area Default: Select an Area
Choices: %AI Analog Input, %AQ Analog Output, %I Discrete Input, %G Genius Global,
%M Internal Discrete, %Q Discrete Output, %R Register Memory, %S System, %SA
System, %SB System, %SC System, %T Temporary Status, %W Bulk Memory.
Start The starting offset of the reference address range.
Default: 0 (not valid)
Valid range:
For %S, %SA, %SB and %SC, must be 1.
All other memory types: 1 through the upper limit of the reference address range. Must be
less than the End value.
End The ending offset of the reference address range.
Default: 0 (not valid)
Valid range:
For %S, %SA, %SB and %SC, must be 128.
All other memory types: Any value greater than Start, through the upper limit of the reference
address range.
For word memory types (%AI, %R and %W) the highest address available is configured on the
Memory tab.
Access Selects the type of external access allowed for the defined address range.
Choices: Read-Only, Read/Write
Default: Read-Only

3.3 Storing (Downloading) Hardware Configuration

A PACSystems control system is configured by creating a configuration file using the PME
programming and configuration software, then transferring (downloading) the file from the
programmer to the CPU via serial port COM1, serial port COM2, or via an Ethernet port. If you use a
serial port, it must be configured as RTU Slave (default) or SNP Slave.
The CPU stores the configuration file in its non-volatile RAM memory. After the configuration is stored,
I/O scanning is enabled or disabled per the newly stored configuration parameters.
Before you can use an Ethernet Interface to store the hardware configuration to the PACSystems,
you must first set the IP Address in the Ethernet Interface either by using the Set Temporary IP
Address utility (refer to Setting a Temporary IP Address) or by downloading a hardware configuration
through a serial connection.
2. In the programmer software, go to the
Project tab of the Navigator, right click the
Target, and choose Go Online.
3. Right click the Target and choose Online
Commands, Set Programmer Mode. Make
sure the CPU is in STOP Mode.
4. Right click the Target node, and choose
Download to Controller.
5. In the Download to Controller dialog box,
select the items to download and click OK.
Figure 24: Downloading Hardware Config

to CPU
Notes: If you download to a PACSystems target that already has a project on it, the existing project
is overwritten.
If I/O variables are configured, hardware configuration and logic cannot be stored
independently. They must be stored at the same time.
If passwords have been set, when you go online, you will be taken to the highest unprotected
level. If no passwords have been set, you will go online with Privilege Level 4.

3.4 Configuring the Embedded Ethernet Interface

Before you can use the embedded Ethernet Interface, you must configure it using the programming
software. To configure the embedded Ethernet interface:
1. In the Project tab of the Navigator, expand
your PACSystems Target, the hardware
configuration, and the main rack (Rack 0).
2. Expand the CPU slot (Slot 1). The Ethernet
Interface daughterboard is displayed as
Ethernet.
3. Right click the daughterboard slot and
choose Configure. The Parameter Editor
window displays the Ethernet Interface
parameters.
Figure 25: Selecting Embedded Ethernet for

Configuration
Ethernet interface configuration includes the following additional procedures. For details on
completing these steps, refer to the PACSystems RX7i & RX3i TCP/IP Ethernet Communications User
Manual, GFK-2224.
▪ Assigning an IP Address for initial network operation, such as connecting the programmer to
download the hardware configuration, using the Set Temporary IP Address utility (refer to Setting
a Temporary IP Address) or by downloading a hardware configuration through a serial
connection.
▪ Configuring the characteristics of the Ethernet interface.
▪ Configuring Ethernet Global Data, if used.
▪ (Optional, not required for most systems). Setting up the RS-232 port for Local Station Manager
Operation. This is part of the basic Ethernet Interface configuration.
▪ (Optional, not required for most systems). Configuring advanced user parameters. This requires
creating a separate ASCII parameter file that is stored to the Controller with the hardware
configuration. The Ethernet Interface has a set of default Advanced User Parameter values that
should be changed only in exceptional circumstances by experienced users.
▪ (Optional) Setting up the Controller for Modbus/TCP Server operation.
Note: Whenever a CPE310 is configured as a CPU310, Ethernet properties cannot be configured.
The embedded Ethernet interface is not supported when CPE310 is configured as a CPU310
and the Ethernet port should not be connected to any network because it may have adverse
effects on the network and/or operation of the CPU.
Note: Whenever a CPE330 is configured as a CPU320, Ethernet properties cannot be configured.
However, the embedded Ethernet ports may be used with their default IP Addresses.

3.4.1 Establishing Initial Ethernet Communications

To establish Ethernet communications between the PME programming and configuration software
and the CPU, you first need to set an IP address. Use one of the following methods:
Default IP Addresses for Initial Ethernet communication with the CPU may be established using
CPE305/CPE310/CPE330/CPE400 the default IP addresses programmed at the factory:
Embedded Ethernet
CPE305/CPE310 and CPE330/CPE400 LAN2 CPE400
CPE330/CPE400 LAN1 LAN327
IP 192.168.0.100 10.10.0.100 0.0.0.0

Address:
Subnet 255.255.255.0 255.255.255.0 0.0.0.0

Mask:
Gateway: 0.0.0.0 0.0.0.0 0.0.0.0
Connecting to CPE305/CPE310 If the IP address of the CPE305/CPE310 embedded Ethernet interface is

Embedded Ethernet when not known, communication may be established using one of these
IP Addresses are not known methods to set a permanent IP addresses:
 Connect to the CPE305/CPE310 via its serial port and assign an IP
Address to the embedded Ethernet interface by downloading a
hardware configuration.
 Connect to the CPE305/CPE310 with PME using an IC695ETM001
module with a known IP address and located in the same rack.
Download a new hardware configuration with the desired IP
address for the embedded Ethernet interface.
Connecting to CPE330 Embedded If the IP addresses of the CPE330 embedded LAN 1 and LAN 2 Ethernet
Ethernet when IP Addresses are interfaces are not known, communication may be established using
not known one of these methods to set new IP addresses:
 Setting a Temporary IP Address using the Set Temporary IP Address
tool in Proficy Machine Edition (PME). After setting the temporary
address, connect to the selected CPE330 LAN using PME and
download a new hardware configuration with the desired
permanent IP addresses.
 Connect to the CPE330 with PME using an IC695ETM001 module
with a known IP address and located in the same rack. Download a
new hardware configuration with the desired permanent IP
addresses for the CPE330 embedded Ethernet interfaces.
Connecting to CPE400 Embedded Use the OLED display to read the IP Address of any LAN. Note: the Set
Ethernet when IP Addresses are Temporary IP Address tool is not available for CPE400.
not known

3.4.2 Setting a Temporary IP Address

If supported by the host CPU44, use the Set Temporary IP Address utility to specify an IP address in
place of one that has been lost or forgotten.
The following restrictions apply when using the Set Temporary IP Address utility:
 To use the Set Temporary IP Address utility, the PLC CPU must not be in RUN Mode. IP address
assignment over the network will not be processed until the CPU is stopped and is not scanning
outputs.
 The Set Temporary IP Address utility does not function if communications with the networked
PACSystems target travel through a router. The Set Temporary IP Address utility can be used if
communications with the networked PACSystems target travel across network switches and
hubs.
 The current user logged on the computer running the Set Temporary IP Address utility must have
full administrator privileges.
 The target PACSystems must be located on the same local sub-network as the computer running
the Set Temporary IP Address utility. The sub-network is specified by the computer's subnet mask
and the IP addresses of the computer and the PACSystems Ethernet Interface.
Note: To set the IP address, you will need the MAC
address of the Ethernet Interface to which PME
will be connected.
1. Connect the PACSystems CPU LAN to the Ethernet
network on which PME is communicating.
2. In the Project tab of the Navigator, right click the
PACSystems target, choose Offline Commands, and
then choose Set Temporary IP Address. The Set
Temporary IP Address dialog box (Figure 26) appears.
3. In the Set Temporary IP Address dialog box, do the
following:
 Key in the 12-digit hexadecimal MAC address (two
digits per field).
 In the IP Address to Set box, specify the temporary
IP address you want to set for the PACSystems
LAN.
 If necessary, select the Enable Network Interface
Selections check box and specify the IP address of
the network interface on which the PACSystems is
located.
4. When the fields are properly configured, click the
Set IP button.
5. The IP Address of the specified PACSystems LAN will
be set to the specified temporary address. This may Figure 26: Set Temporary IP Address
take up to a minute.
After the programmer connects over Ethernet, the permanent IP address for the Ethernet interface,
which is set in the hardware configuration, will have been downloaded to the CPU.
44 Not supported by CPE400

The temporary IP address remains in effect until the Ethernet interface is restarted, power-cycled or
until the hardware configuration is downloaded or cleared.
Caution
The temporary IP Address set by the Set Temporary IP
Address utility is not retained through a power cycle. To set a
permanent IP Address, you must set the IP Address property
of the target and download (store) HWC to the PACSystems.
The Set Temporary IP Address utility can assign a temporary
IP Address even if the target Ethernet Interface has
previously been configured to a non-default IP Address. (This
includes overriding an IP Address previously configured by
the programmer.)
Use this IP Address assignment mechanism with care.

Chapter 4 CPU Operation
This chapter describes the operating modes of a PACSystems CPU and describes the tasks the CPU
carries out during these modes. The following topics are discussed:
■ CPU Sweep
■ Program Scheduling Modes
■ Window Modes
■ Data Coherency in Communications Windows
■ Run/Stop Operations
■ Flash Memory Operation
■ Logic/Configuration Source and CPU Operating Mode at Power-Up
■ Clocks and Timers
■ System Security
■ PACSystems I/O System
■ Power-Up and Power-Down Sequences

Chapter 4. CPU Operation
4.1 CPU Sweep

The application program in the CPU executes repeatedly until stopped by a command from the
programmer, from another device, from the RUN/STOP Switch on the CPU module, or a fatal fault
occurs. In addition to executing the application program, the CPU obtains data from input devices,
sends data to output devices, performs internal housekeeping, performs communications tasks, and
performs self-tests. This sequence of operations is called the sweep.
The CPU sweep runs in one of three sweep modes:
Normal In this mode, each sweep can consume a variable amount of time.
Sweep The Logic Window is executed in its entirety each sweep. The
Communications and Background Windows can be set to execute in
Limited or Run-to-Completion mode.
Constant In this mode, each sweep begins at a user-specified Constant Sweep
Sweep time after the previous sweep began. The Logic Window is executed
in its entirety each sweep. If there is sufficient time at the end of the
sweep, the CPU alternates among the Communications and
Background Windows, allowing them to execute until it is time for the
next sweep to begin.
Constant In this mode, each sweep can consume a variable amount of time.
Window The Logic Window is executed in its entirety each sweep. The CPU
alternates among the Communications and Background Windows,
allowing them to execute for a time equal to the user-specified
Constant Window timer.
Note: The information presented above summarizes the different sweep modes. For additional
information, refer to CPU Sweep Modes.
The CPU also operates in one of four RUN/STOP Modes (for details, refer to Run/Stop Operations):
■ Run/Outputs Enabled
■ Run/Outputs Disabled
■ Stop/IO Scan
■ Stop/No IO

4.1.1 Parts of the CPU Sweep

There are seven major phases in a typical CPU sweep as shown in the following figure.
Housekeeping
Start-of-Sweep
input scan
Application Program
Task Execution
(Logicwindow)
WINDOW)
Output Scan
Prog
window no
scheduled
?
yes
Controller
Communications
Window
Comm
no
window
scheduled
?
yes
Backplane
Communications
Window
Background no
task
scheduled
?
yes
Background task
Window
Start next sweep

SWEEP
Figure 27: Major Phases of a Typical CPU Sweep

4.1.1.1 Major Phases in a Typical CPU Sweep

Phase Activity
Housekeeping The housekeeping portion of the sweep performs the tasks necessary to prepare for the
start of the sweep. This includes updating %S bits, determining timer update values,
determining the mode of the sweep (Stop or Run), and polling of expansion racks.
Expansion racks are polled to determine if power has just been applied to an expansion
rack. Once an expansion rack is recognized, then configuration of that rack and all of its
modules are processed in the Controller Communications Window.
Input Scan During the input scan, the CPU reads input data from the Genius Bus Controllers and input
modules. If data has been received on an EGD page, the CPU copies the data for that page
from the Ethernet interface to the appropriate reference memory. For details, see
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
Note: The input scan is not performed if a program has an active Suspend I/O function
on the previous sweep.
Application The CPU solves the application program logic. It always starts with the first instruction in
Program Task the program. It ends when the last instruction is executed. Solving the logic creates a new
Execution (Logic set of output data.
Window) For details on controlling the execution of programs, refer to PACSystems RX7i and RX3i
CPU Programmer’s Reference Manual, GFK-2950 Chapter 2.
Interrupt driven logic can execute during any phase of the sweep. For details, refer to
A list of execution times for instructions can be found in Appendix A.
Output Scan The CPU writes output data to bus controllers and output modules. The user program
checksum is computed.
During the output scan, the CPU sends output data to the Genius Bus Controllers and
output modules. If the producer period of an EGD page has expired, the CPU copies the
data for that page from the appropriate reference memory to the Ethernet interface. The
output scan is completed when all output data has been sent.
If the CPU is in RUN Mode and it is configured to perform a background checksum
calculation, the background checksum is performed at the end of the output scan. The
default setting for number of words to checksum each sweep is 16. If the words to
checksum each sweep is set to zero, this processing is skipped. The background
checksum helps ensure the integrity of the user logic while the CPU is in RUN Mode.
The output scan is not performed if a program has an active Suspend I/O function on the
current sweep.

Phase Activity
Controller Services the onboard Ethernet and serial ports. In addition, reconfiguration of expansion
Communications racks and individual modules occurs during this portion of the sweep.
Window The CPU always executes this window. The following items are serviced in this window:
 Reconfiguration of expansion racks and individual modules. During the Controller
Communications Window, highest priority is given to reconfiguration. Modules are
reconfigured as needed, up to the total time allocated to this window. Several sweeps
are required to complete reconfiguration of a module.
 Communications activity involving the embedded Ethernet port and the two serial
ports of the CPU.
Time and execution of the Controller Communications Window can be configured using
the programming software. It can also be dynamically controlled from the user program
using Service Request function #3. The window time can be set to a value from 0 to 255
ms (default is 10 ms).
Note that if the Controller Communications Window is set to 0, there are two alternate
ways to open the window: perform a power-cycle without the battery (or Energy Pack)
attached, or go to STOP Mode.
Backplane Communications with intelligent devices occur during this window. The rack-based
Communications Ethernet Interface module communicates in the Backplane Communications window.
Window During this part of the sweep the CPU communicates with intelligent modules such as the
Genius Bus Controller and TCP/IP Ethernet modules.
In this window, the CPU completes any previously unfinished request before executing any
pending requests in the queue. When the time allocated for the window expires,
processing stops.
The Backplane Communications Window defaults to Complete (Run to Completion) mode.
This means that all currently pending requests on all intelligent option modules are
processed every sweep. This window can also run in Limited mode, in which the maximum
time allocated for the window per scan is specified.
The mode and time limit can be configured and stored to the CPU, or it can be dynamically
controlled from the user program using Service Request function #4. The Backplane
Communications Window time can be set to a value from 0 to 255ms (default is 255ms).
This allows communications functions to be skipped during certain time-critical sweeps.
Background CPU self-tests occur in this window.
Window A CPU self-test is performed in this window. Included in this self-test is a verification of the
checksum for the CPU operating system software.
The Background Window time defaults to 0 ms. A different value can be configured and
stored to the CPU, or it can be changed online using the programming software.
Time and execution of the Background Window can also be dynamically controlled from
the user program using Service Request function #5. This allows background functions to
be skipped during certain time-critical sweeps.

4.1.2 CPU Sweep Modes

4.1.2.1 Normal Sweep Mode
In Normal Sweep mode, each sweep can consume a variable amount of time. The Logic window is
executed in its entirety each sweep. The Communications windows can be set to execute in a Limited
or Run-to-Completion mode. Normal Sweep is the most common sweep mode used for control
system applications.
The following figure illustrates three successive CPU sweeps in Normal Sweep mode. Note that the
total sweep times may vary due to sweep-to-sweep variations in the Logic window, Communications
windows, and Background window.
SWEEP n SWEEP n+1 SWEEP n+2
HK HK HK
INPUT INPUT INPUT
LOGIC LOGIC LOGIC
OUTPUT
CC
OUTPUT
BPC
CC
BG
BPC OUTPUT
BG CC
BPC
Abbreviations:
HK = Housekeeping BG
CC = Controller Communications Window
BPC = Backplane Communications Window
BG = Background Window
Figure 28: Typical Sweeps in Normal Sweep Mode

4.1.2.2 Constant Sweep Mode

In Constant Sweep mode, each sweep begins at a specified Constant Sweep time after the previous
sweep began. The Logic Window is executed in its entirety each sweep. If there is sufficient time at
the end of the sweep, the CPU alternates among the Controller Communications, Backplane
Communications, and Background Windows, allowing them to execute until it is time for the next
sweep to begin. Some or all of the Communications and Background Windows may not be executed.
The Communications and Background Windows terminate when the overall CPU sweep time has
reached the value specified as the Constant Sweep time.
One reason for using Constant Sweep mode is to ensure that I/O data are updated at constant
intervals.
The value of the Constant Sweep timer can be configured to be any value from 5 to 2550 ms. The
Constant Sweep timer value may also be set and Constant Sweep mode may be enabled or disabled
by the programming software or by the user program using Service Request function #1. The
Constant Sweep timer has no default value; a timer value must be set prior to or at the same time
Constant Sweep mode is enabled.
The Ethernet Global Data45 page, configured for either consumption or production, can add up to
1 ms to the sweep time. This sweep impact should be considered when configuring the CPU constant
sweep mode and setting the CPU watchdog timeout.
If the sweep exceeds the Constant Sweep time in a given sweep, the CPU places an oversweep alarm
in the CPU fault table and sets the OV_SWP (%SA0002) status reference at the beginning of the next
sweep. Additional sweep time due to an oversweep condition in a given sweep does not affect the
time given to the next sweep.
The following figure illustrates four successive sweeps in Constant Sweep mode with a Constant
Sweep time of 100 ms. Note that the total sweep time is constant, but an oversweep may occur due
to the Logic Window taking longer than normal.
SWEEP n SWEEP n+1 SWEEP n+2 SWEEP n+3
t = 0 ms t = 100 ms t = 220 ms t = 320 ms
HK HK HK HK
INPUT INPUT INPUT INPUT
LOGIC LOGIC LOGIC LOGIC
OUTPUT
Constant OUTPUT
CC
Sweep CC
Time OUTPUT
BPC
CC BPC
BPC BG
BG
SYS
SYS BG
BG
Abbreviations:
20 ms oversweep
HK = Housekeeping OUTPUT
PRG = Programmer Window.
BPC = Backplane Communications Window.
Figure 29: Typical Sweeps in Constant Sweep Mode
45 For EGD configured on Embedded Ethernet interface of CPE305/CPE310, refer to A.3.6 for Constant sweep impact.

4.1.2.3 Constant Window Mode

In Constant Window mode, each sweep can consume a variable amount of time. The Logic Window
is executed in its entirety each sweep. The CPU alternates among the three windows, allowing them
execute for a time equal to the value set for the Constant Window timer. The overall CPU sweep time
is equal to the time required to execute the Housekeeping, Input Scan, Logic Window, and Output
Scan phases of the sweep plus the value of the Constant Window timer. This time may vary due to
sweep-to-sweep variances in the execution time of the Logic Window.
An application that requires a certain amount of time between the Output Scan and the Input Scan,
permitting inputs to settle after receiving output data from the program, would be ideal for Constant
Window mode.
The value of the Constant Window timer can be configured to be any value from 3 to 255 ms. The
Constant Window timer value may also be set by the programming software or by the user program
using Service Request functions #3, #4, and #5.
The following figure illustrates three successive sweeps in Constant Window mode. Note that the
total sweep times may vary due to sweep-to-sweep variations in the Logic Window, but the time
given to the Communications and Background Windows is constant. Some of the Communications or
Background Windows may be skipped, suspended, or run multiple times based on the Constant
Window time.
SWEEP n SWEEP n+1 SWEEP n+2
HK HK HK
INPUT INPUT INPUT
LOGIC LOGIC LOGIC
OUTPUT
CC
OUTPUT
CC BPC
BPC OUTPUT
BG BG CC
CC CC
SYS Constant
Window
BG Time
Abbreviations: BPC
HK = Housekeeping
BPC = Backplane Communications Window
Figure 30: Typical Sweeps in Constant Window Mode

4.2 Program Scheduling Modes

The CPU supports one program scheduling mode: the Ordered mode. An ordered program is
executed in its entirety once per sweep in the Logic Window.
4.3 Window Modes
The previous section describes the phases of a typical CPU sweep. The Controller Communications,
Backplane Communications, and Background windows can be run in various modes, based on the
CPU sweep mode. (Refer to CPU Sweep Modes.) The following three window modes are available:
Run-to- In Run-to-Completion mode, all requests made when the window has started
Completion are serviced. When all pending requests in the given window have completed,
the CPU transitions to the next phase of the sweep. (This does not apply to the
Background window because it does not process requests.)
Constant In Constant Window mode, the total amount of time that the Controller
Communications window, Backplane Communications window, and
Background window run is fixed. If the time expires while in the middle of
servicing a request, these windows are closed, and communications will be
resumed the next sweep. If no requests are pending in this window, the CPU
cycles through these windows the specified amount of time polling for further
requests. If any window is put in constant window mode, all are in constant
window mode.
Limited In Limited mode, the maximum time is fixed for the execution of the window. If
time expires while in the middle of servicing a request, the window is closed,
and communications will be resumed the next time that the given window is
run. If no requests are pending in this window, the CPU proceeds to the next
phase of the sweep.
4.4 Data Coherency in Communications Windows
When running in Constant or Limited Window mode, the Controller and Backplane Communications
Windows may be terminated early in all CPU sweep modes. If an external device, such as CIMPLICITY
HMI, is transferring a block of data, the coherency of the data block may be disrupted if the
communications window is terminated prior to completing the request. The request will complete
during the next sweep; however, part of the data will have resulted from one sweep and the
remainder will be from the following sweep. When the CPU is in Normal Sweep mode and the
Communications Window is in Run-to-Completion mode, the data coherency problem described
above does not exist.
Note: External devices that communicate to the CPU while it is stopped will read information as it
was left in its last state. This may be misleading to operators viewing an HMI system that
does not indicate CPU Run/Stop state. Process graphics will often indicate everything is still
operating normally.
Also, note that non-retentive outputs do not clear until the CPU is changed from Stop to Run.

4.5 Run/Stop Operations

The PACSystems CPUs support four RUN/STOP Modes of operation. You can change these modes in
the following ways: the RUN/STOP Switch, configuration from the programming software, LD function
blocks, and system calls from C applications. Switching to and from various modes can be restricted
based on privilege levels, position of the RUN/STOP Switch, passwords, etc.
Mode Operation
Run/Outputs The CPU runs user programs and continually scans inputs and updates physical
Enabled outputs, including Genius and Ethernet outputs. The Controller and Backplane
Communications Windows are run in Limited, Run-to-Completion, or Constant
mode.
Run/Outputs The CPU runs user programs and continually scans inputs, but updates to physical
Disabled outputs, including Genius and Field Control, are not performed. Physical outputs are
held in their configured default state in this mode. The Controller and Backplane
Communications Windows are run in Limited, Run-to-Completion, or Constant
mode.
Stop/IO The CPU does not run user programs, but the inputs and outputs are scanned. The
Scan Controller and Backplane Communications Windows are run in Run-to-Completion
Enabled mode. The Background Window is limited to 10ms.
Stop/IO The CPU does not run user programs, and the inputs and outputs are not scanned.
Scan The Controller and Backplane Communications Windows are run in a Run-to-
Disabled Completion mode. The Background Window is limited to 10ms.
Note: STOP Mode I/O scanning is always disabled for redundancy CPUs.
Note: You cannot add to the size of %P and %L reference tables in RUN Mode unless the %P and
%L references are the first of their type in the block being stored or the block being stored is a
totally new block.

4.5.1 CPU STOP Modes

The CPU has four modes of operation while it is in STOP Mode. The two most common are:
4.5.1.1 STOP-I/O Enabled Mode
 I/O Scan Enabled - the Input and Output scans are performed each sweep.
4.5.1.2 STOP-I/O Disabled Mode
 I/O Scan Disabled - the Input and Output scans are skipped.
When the CPU is in STOP Mode, it does not execute the application program. You can configure
whether the I/O is scanned during STOP Mode. Communications with the programmer and intelligent
option modules continue in STOP Mode. Also, bus receiver module polling and rack reconfiguration
continue in STOP Mode.
In both STOP Modes, the Controller Communications and Backplane Communications windows run in
Run-to-Completion mode and the Background window runs in Limited mode with a 10 ms limit.
The number of last scans can be configured in the hardware configuration. Last scans are completed
after the CPU has received an indication that a transition from Run to Stop or Stop Faulted mode
should occur. The default is 0.
SVCREQ13 can be used in the application program to stop the CPU after a specified number of scans.
All I/O will go to their configured default states, and a diagnostic message will be placed in the CPU
Fault Table.
Start-of-Sweep
Housekeeping
Executes in
Input Scan Stop-I/O Scan Enabled
mode only
Executes in
Output Scan Stop-I/O Scan Enabled
mode only
Controller Runs
Communications to
Window completion
Backplane Runs
Communications to
Window Completion
Limited
Background Task
(10ms)
Window
Figure 31: CPU Sweep in Stop-I/O Disabled and Stop-I/O Enabled Modes

4.5.1.3 STOP-Halt Mode

Following an internal fault, such as a hardware watchdog timeout or an ECC Memory Check fault, the
CPU will automatically go into STOP-Halt mode. In this mode, logic execution and I/O scanning is
suspended.
Depending on the underlying cause, CPU rack backplane communications may also be suspended.
For example, following a hardware watchdog timeout, the CPU restarts in STOP-Halt mode with
backplane communications operational. In contrast, following an ECC Memory Check Fault, the CPU
immediately enters STOP-Halt mode with backplane communications suspended.
To recover from STOP-Halt mode, the CPU/CPE must be disconnected from its backup power source
(battery or Energy Pack), powered off, then powered back on, after which the backup power source
should be reconnected.
To enable backplane communications where they have been disabled in STOP-Halt mode, cycle
power with its backup power source attached (battery or Energy Pack), then powered back on.
While the CPU is in STOP-Halt mode, the PACS Analyzer tool may be employed to examine the CPU’s
fault tables. The PACS Analyzer software is a tool that is embedded in PME. It can also be downloaded
from the GE Automation and Controls support website www.geautomation.com.
If backplane communications have been suspended, the PACS Analyzer must be directly connected
to a serial or Ethernet port on the CPU. If backplane communications are operational, the PACS
Analyzer may be connected via a communications or Ethernet module in the backplane, or to a CPU-
embedded port.
CPE305/CPE310/CPE330/CPE400 CPU models only: The programmer can connect to these CPUs in
STOP-Halt mode through the embedded Ethernet port without a reset or power cycle.
4.5.1.4 STOP-Fault Mode

In STOP-Fault Mode, logic execution and I/O Scanning cease after the number of last scans
(configured by the user) has been exhausted. Client communications also cease at that time. Server
communications are available, but with PLC data which has become static.
Within PME, the user can configure each fault action to be either diagnostic or fatal.
 A diagnostic fault does not stop the Controller from executing logic. It sets a diagnostic
variable and is logged in a fault table.
 A fatal fault transitions the Controller to the STOP-Fault Mode. It also sets a diagnostic
variable and is logged in a fault table.
Within PME, the user can also configure the number of last scans to be executed in the event of a
fault (see PME Scans tab, Number of Last Scans parameter).
To recover from STOP-Fault Mode, resolve the underlying cause and clear the Controller Fault Table.
This allows the CPU to transition to STOP-I/O Disabled Mode.

4.5.2 STOP-to-RUN Mode Transition

The CPU performs the following operations on Stop-to-Run transition:
 Validation of sweep mode and program scheduling mode selections
 Validation of references used by programs with the actual configured sizes
 Re-initialization of data areas for external blocks and standalone C programs
 Clearing of non-retentive memory
4.5.3 RUN/STOP Switch Operation

The RUN/STOP Switch is a 3-position switch which operates as follows:
Switch Position CPU and Sweep Mode Memory Protection
RUN I/O or The CPU runs with I/O sweep enabled. User program memory is read only.
RUN I/O Enable
RUN or The CPU runs with outputs disabled. User program memory is read only.
RUN Output Disable
STOP The CPU is not allowed to go into RUN User program memory can be written.
Mode.
The RUN/STOP Switch can be disabled in the programming software HWC. The memory protection
function of the switch can be disabled separately in HWC. The RUN/STOP Switch is enabled by
default. The memory protection functionality is disabled by default.
The Read Switch Position (Switch_Pos) function allows the logic to read the current position of the
RUN/STOP Switch, as well as the mode for which the switch is configured. For details, refer to

4.6 Flash Memory Operation

The CPU stores the current configuration and application in user memory (either battery-backed RAM
or non-volatile user memory, depending on the CPU model). You can also store the Logic, Hardware
Configuration, and Reference Data into non-volatile flash memory. The PACSystems CPU provides
enough flash memory to hold all of user space, all reference tables that aren't counted against user
space, and any overhead required. For details on which items count against user memory space,
refer to Appendix B.
By default, the CPU reads program logic and configuration, and reference table data from user
memory at power-up. However, logic/configuration and reference tables can each be configured to
always read from flash or conditionally read from flash. To configure these parameters in the
programming software, select the CPU’s Settings tab in Hardware Configuration.
If logic/configuration and/or reference tables are configured for conditional power-up from flash,
these items are restored from flash to user memory when the user memory is corrupted or was not
preserved (for example, the memory backup battery or Energy Pack is not installed or not
operational). If logic/configuration and/or reference memory are configured for conditional power-up
from flash and user memory has been preserved, no flash operation will occur.
If logic/configuration and/or reference tables are configured to always power up from flash, these
items are restored from flash to user memory regardless of the state of the user memory.
Note: If any component (logic/configuration or reference tables) is read from flash, OEM-mode and
passwords are also read from flash.
In addition to configuring where the CPU obtains logic, configuration, and data during power-up, the
programming software provides the following flash operations:
 Write a copy of the current configuration, application program, and reference tables (excluding
overrides) to flash memory. Note that a write-to-flash operation causes all components to be
stored to flash.
 Read a previously stored configuration and application program, and/or reference table values
from flash into user memory.
 Verify that flash and user memory contain identical data.
 Clear flash contents.
Flash read and write operations copy the contents of flash memory or user memory as individual
files. The programming software displays the progress of the copy operation and allows you to
cancel a flash read or write operation during the copy process instead of waiting for the entire
transfer process to complete. The entire user memory image must be successfully transferred for the
flash copy to be considered successful. If an entire write-to-flash transfer is not completed due to
canceling, power cycle, or some other intervention, the CPU will clear flash memory. Similarly, if a
read-from-flash transfer is interrupted, user memory will be cleared.

4.7 Logic/Configuration Source and CPU Operating Mode at

Power-Up
Flash and user memory can contain different values for the Logic/Configuration Power-up Source
parameter. The following tables summarize how these settings determine the logic/configuration
source after a power cycle. CPU mode is affected by the Power-up Mode, the RUN/STOP Switch and
Stop-Mode I/O Scanning parameters, the physical RUN/STOP Mode Switch position, and the Power
Down Mode as shown in sections 4.7.1 and 4.7.2.
Before Power Cycle After Power Cycle
Logic/Configuration
Logic/Configuration Origin of
Power-up Source CPU Mode
Power-up Source in RAM Logic/Configuration
in Flash
Always Flash Memory not preserved Flash See CPU Mode when Memory Not
(i.e. no battery/Energy Pack, Preserved/Power-up Source is
or memory corrupted) Flash.
Always Flash No configuration in RAM, Flash See CPU Mode when Memory
memory Preserved.
preserved
Always Flash Always Flash Flash
Always Flash Conditional Flash Flash
Always Flash Always RAM Flash
Conditional Flash Memory not preserved Flash See CPU Mode when Memory Not
(i.e. no battery/Energy Pack Preserved/Power-up Source is
or memory corrupted) Flash.
Conditional Flash No configuration in RAM, Uses default Stop Disabled
memory logic/configuration
preserved
Conditional Flash Always Flash RAM See CPU Mode when Memory
Conditional Flash Conditional Flash RAM Preserved.
Conditional Flash Always RAM RAM
Always RAM Memory not preserved Uses default Stop Disabled
(i.e. no battery/Energy Pack, logic/configuration
or memory corrupted)
Always RAM No configuration in RAM, Uses default Stop Disabled
memory logic/configuration
preserved
Always RAM Always Flash Flash See CPU Mode when Memory
Always RAM Conditional Flash RAM Preserved.
Always RAM Always RAM RAM
No Configuration in Memory not preserved Uses default Stop Disabled
Flash (i.e. no battery/Energy Pack, logic/configuration
or memory corrupted)
No Configuration in No configuration in RAM, Uses default Stop Disabled
Flash memory preserved logic/configuration
No Configuration in Always Flash RAM See CPU Mode when Memory
Flash Preserved.
No Configuration in Conditional Flash RAM
Flash
No Configuration in Always RAM RAM
Flash

4.7.1 CPU Mode when Memory Not Preserved/Power-up Source is Flash

Configuration Parameters
Power-up Mode RUN/STOP Switch RUN/STOP Switch Position CPU Mode
Run Enabled Stop Stop Disabled
Run Enabled Run Disabled Run Disabled
Run Enabled Run Enabled Run Enabled
Run Disabled N/A Run Disabled
Stop N/A N/A Stop Disabled
Last Enabled Stop Stop Disabled
Last Enabled Run Disabled Run Disabled
Last Enabled Run Enabled Run Disabled
Last Disabled N/A Run Disabled
4.7.2 CPU Mode when Memory Preserved

Configuration Parameters
Power-up RUN/STOP Stop-Mode I/O Scanning RUN/STOP Power Down CPU Mode
Mode Switch Switch Position Mode
Run Enabled Enabled Stop N/A Stop Enabled
Run Enabled Disabled Stop N/A Stop Disabled
Run Enabled N/A Run Disabled N/A Run Disabled
Run Enabled N/A Run Enabled N/A Run Enabled
Run Disabled N/A N/A N/A Run Enabled
Stop N/A Enabled N/A N/A Stop Enabled
Stop N/A Disabled N/A N/A Stop Disabled
Last Enabled Enabled Stop Stop Disabled Stop Disabled
Last Enabled Enabled Stop Stop Enabled Stop Enabled
Last Enabled Enabled Stop Run Disabled Stop Enabled
Last Enabled Enabled Stop Run Enabled Stop Enabled
Last Enabled Disabled Stop N/A Stop Disabled
Last Enabled N/A Run Disabled Stop Disabled Stop Disabled
Last Enabled Enabled Run Disabled Stop Enabled Stop Enabled
Last Enabled Disabled Run Disabled Stop Enabled Stop Disabled
Last Enabled N/A Run Disabled Run Disabled Run Disabled
Last Enabled N/A Run Disabled Run Enabled Run Disabled
Last Enabled N/A Run Enabled Stop Disabled Stop Disabled
Last Enabled Enabled Run Enabled Stop Enabled Stop Enabled
Last Enabled Disabled Run Enabled Stop Enabled Stop Disabled
Last Enabled N/A Run Enabled Run Disabled Run Disabled
Last Enabled N/A Run Enabled Run Enabled Run Enabled
Last Disabled N/A N/A Stop Disabled Stop Disabled
Last Disabled Enabled N/A Stop Enabled Stop Enabled
Last Disabled Disabled N/A Stop Enabled Stop Disabled
Last Disabled N/A N/A Run Disabled Run Disabled
Last Disabled N/A N/A Run Enabled Run Enabled

4.8 Clocks and Timers

Clocks and timers provided by the CPU include an elapsed time clock, a time-of-day clock, and
software and hardware watchdog timers.
For information on timer functions and timed contacts provided by the CPU instruction set, refer to
Timers in PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 4.
4.8.1 Elapsed Time Clock
The elapsed time clock tracks the time elapsed since the CPU powered on. The clock is not retentive
across a power failure; it restarts on each power-up. This seconds count rolls over (seconds count
returns to zero) approximately 100 years after the clock begins timing.
Because the elapsed time clock provides the base for system software operations and timer function
blocks, it may not be reset from the user program or the programmer. However, the application
program can read the current value of the elapsed time clock by using Service Request #16 or
Service Request #50, which provides higher resolution.
4.8.2 Time-of-Day Clock
A hardware time-of-day clock maintains the time of day (TOD) in the CPU. The time-of-day clock
maintains the following time functions:
 Year (two digits)
 Month
 Day of month
 Hour
 Minute
 Second
 Day of week
The TOD clock is battery-backed and maintains its present state across a power failure. The time-of-
day clock handles month-to-month and year-to-year transitions and automatically compensates for
leap years through year 2036.
You can read and set the hardware TOD time and date through the application program using
Service Request function #7. For details, refer to PACSystems RX7i and RX3i CPU Programmer’s
Reference Manual, GFK-2950 Chapter 6.
4.8.2.1 High-Resolution Time of Day Software Clock
A high-resolution software TOD clock is implemented in firmware to provide nanoseconds resolution.
When the high-resolution software TOD clock is set, the hardware TOD clock is set with the YYYY:
Mon: Day: Hr: Min: Sec fields in the POSIX time, the RTC is read, and the delta between the POSIX time
and the value read from the RTC is computed and saved. Thus, if 1-second resolution is desired the
hardware TOD clock is read. Otherwise, the high-resolution software TOD clock is read to provide
greater resolution. When the latter occurs, the hardware RTC is read and the saved delta added to
the value read.
When the SNTP Time Transfer feature is implemented, all SNTP time updates received at the CPU will
cause the high-resolution software TOD clock to be updated.

4.8.2.2 Synchronizing the High-resolution Time of Day Clock to an SNTP Network Time
Server
In an SNTP system, a computer on the network (called an SNTP server) sends out a periodic timing
message to all SNTP-capable Ethernet Interfaces on the network, which synchronize their internal
clocks with this SNTP timing message. If SNTP is used to perform network time synchronization, the
time-stamp information typically has ±10ms accuracy between controllers on the same network.
Synchronizing the CPU TOD clock to an SNTP server allows you to set a consistent time across
multiple systems. Once the CPU TOD clock has been synchronized with the SNTP time, all produced
EGD exchanges will use the CPU TOD current value for the time-stamp.
The CPU TOD clock is set with accuracy within ±2ms of the SNTP time-stamp.
TOD clock synchronization is enabled on an Ethernet module by the advanced user parameter (AUP),
ncpu_sync. The CPU must also use a COMMREQ in user logic to select an Ethernet module as the time
master. For additional information, refer to Time-stamping of Ethernet Global Data Exchanges in
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224 Chapter 4.
4.8.3 Watchdog Timer
4.8.3.1 Software Watchdog Timer
A software watchdog timer in the CPU is designed to detect failure to complete sweep conditions. The
timer value for the software watchdog timer is set by using the programming software. The
allowable range for this timer is 10 ms to 2550 ms; the default value is 200 ms. The software
watchdog timer always starts from zero at the beginning of each sweep.
The software watchdog timer is useful in detecting abnormal operation of the application program
that prevents the CPU sweep from completing within the user-specified time. Examples of such
abnormal application program conditions are as follows:
 Excessive recursive calling of a block
 Excessive looping (large loop count or large amounts of execution time for each iteration)
 Infinite execution loop
When selecting a software watchdog value, always set the value higher than the longest expected
sweep time to prevent accidental expiration. For Constant Sweep mode, allowance for oversweep
conditions should be considered when selecting the software watchdog timer value.
Refer to the Appendix A-3.6 for EGD Sweep impact and EGD processor utilization for EGD exchanges
configured on Embedded Ethernet interface of the CPE305/310.
The watchdog timer continues during interrupt execution. Queuing of interrupts within a single
sweep may cause watchdog timer expiration.
If the software watchdog timeout value is exceeded, the OK LED blinks, and the CPU goes to STOP-
Halt mode. Certain functions, however, are still possible. A fault is placed in the CPU fault table, and
outputs go to their default state. The CPU will only communicate with the programmer; no other
communications or operations are possible. To recover, power must be cycled on the rack or
backplane containing the CPU.
To extend the current sweep beyond the software watchdog timer value, the application program
may restart the software watchdog timer using Service Request function #8. However, the software
watchdog timer value may only be changed from the configuration software.
Note that Service Request Function #8 does not reset the output scan timer implemented on the
Genius Bus Controller.

4.8.3.2 Hardware Watchdog Timer

A backup circuit provides additional protection for the CPU. If this backup circuit activates, the CPU is
immediately Reset. Outputs go to their default states, no communications of any kind are possible,
and the CPU halts. The recovery procedure is documented below.
There are two basic forms of hardware watchdog:
1) for CPE305, CPE310, CPE330 and CPE400, a watchdog reset results in an automatic restart into
STOP-Halt mode;
2) for RX3i CPU310, CPU315, CPU320 and all RX7i CPUs, the watchdog reset holds the CPU in reset
until the next power cycle. There is no automatic restart. If a charged battery is connected, the
power cycle will result in a restart into STOP-Halt mode.
For both watchdog reset types, the CPU is power cycled after the energy pack (for the CPE models), or
battery (for the other models listed) has been removed. This procedure gets the CPU out of STOP-Halt.
The backup power source should then be reconnected.
RX3i CPU Response to a Hardware Watchdog Timeout:
The following responses to a hardware watchdog timeout are common to all RX3i CPU and CPE
models:
 While the CPU/CPE is in STOP-Halt mode, you can connect the programmer software or PACs
Analyzer to view the fault tables, including any faults logged before the timeout. (See below for
distinctions between CPU and CPE behavior.) The PACS Analyzer software is a tool that is
embedded in PME. It can also be downloaded from GE’s Automation and Controls support
website www.geautomation.com/support.
 During startup following hardware watchdog reset, the CPU/CPE logs an informational fault with
Error Code 446, which indicates a watchdog auto-reset occurred.
The following responses to a hardware watchdog timeout are different between RX3i CPU and RX3i
CPE models:
 CPU310, CPU315, and CPU320 retain Controller and I/O Fault tables after a hardware watchdog
timeout.
 CPE305, CPE310, CPE330 and CPE400 do not retain Controller and I/O Fault tables following a
hardware watchdog timeout.
Note: PACSystems does not support Fatal Fault Retries.

4.9 System Security

The PACSystems CPU supports two types of system security:
 Passwords/privilege levels
 OEM protection
CPU versions 7.80 and later support Enhanced Security (including merged password tables). This
provides a more secure mechanism for setting and authenticating passwords and OEM keys versus
the Legacy Security Mode. Refer to the Important Product Information document for the CPU model
and firmware version that you are using.
For Enhanced Security operation, see Enhanced Security for Passwords and OEM Protection. A
summary of operational differences between Enhanced and Legacy Security modes is provided at
Legacy/Enhanced Security Comparison.
4.9.1 Passwords and Privilege Levels - Legacy Mode
Passwords are a configurable feature of the PACSystems CPU. Their use is optional and is set up
using the programming software. Passwords provide different levels of access privilege for the CPU
when the programmer is Online. Passwords are not used if the programmer is in Offline mode.
The default state is no password protection. Each privilege level in the CPU may have a unique
password; however, the same password can be used for more than one level. Passwords can be
changed only through the programming software.
Passwords are one to seven ASCII characters in length.
After passwords have been set up, access to the CPU via any communications path is restricted from
the levels at which the passwords are set, unless the proper password has been entered. Once a
password has successfully been accepted, access to the highest privilege level requested and below
is granted (for example, providing the password for level 3 allows access to functions at levels 1, 2,
and 3).
Note: The RUN/STOP Switch on the CPU overrides password protection. Even though the
programmer may not be able to switch between Run and STOP Mode, the switch on the CPU
can do so.
4.9.1.1 Privilege Levels
Level Password Access Description
4 Yes Write to configuration or logic. Configuration may only be written in STOP Mode; logic
may be written in STOP Mode or RUN Mode. Set or delete passwords for any level.
Note: This is the default privilege for a connection to the CPU if no passwords are defined.
3 Yes Write to configuration or logic when the CPU is in STOP Mode, including word-for-word
changes, addition/deletion of program logic, and the overriding of discrete I/O.
2 Yes Write to any data memory. This does not include overriding discrete I/O. The CPU can be
started or stopped. CPU and I/O Fault Tables can be cleared.
1 Yes Read any CPU data except for passwords. This includes reading fault tables, performing
datagrams, verifying logic/configuration, loading program and configuration, etc. from
the CPU. None of this data may be changed. At this level, RUN/STOP Mode transitions
from the programmer are not allowed.

4.9.1.2 Protection Level Request from Programmer

In Legacy mode, upon connection to the CPU, the programmer requests the CPU to move to the
highest non-protected level.
The programmer requests a privilege level change by supplying the new privilege level and the
password for that level. If the password sent by the programmer does not agree with the password
stored in the CPU’s password access table for the requested level, the privilege level change is denied
and a fault is logged in the CPU fault table. The current privilege level is maintained, and no change
occurs. A request to change to a privilege level that is not password protected is made by supplying
the new level and a null password. A privilege change may be to a lower level as well as to a higher
level.
4.9.1.3 Maintaining Passwords through a Power Cycle
Initial passwords are blank for a new controller or a controller that has its passwords cleared. For
passwords to be maintained through power cycles, the controller must either:
Store to RAM and use an Energy Pack or battery to maintain memory.
Store to User Flash with configuration set up to load from Flash at power up.
4.9.1.4 Disabling Passwords
The use of password protection is optional. Passwords can be disabled using the programming
software.
Note: To enable passwords after they have been disabled, the CPU must be power cycled with the
battery or Energy Pack removed.

4.9.2 OEM Protection – Legacy Mode

Original Equipment Manufacturer (OEM) protection provides a higher level of security than password
levels 1 through 4. This feature allows a third-party OEM to create control programs for the CPU and
then set the OEM-locked mode, which prevents the end user from reading or modifying the program.
The OEM protection feature is enabled/disabled using a 1- to 7-character password, known as the
OEM key. When OEM protection is enabled, all read and write access to the CPU program and
configuration is prohibited: any store, load, verify, or clear user program operation will fail.
4.9.2.1 OEM Protection in Systems that Load from Flash Memory
For OEM protection, it is recommended to store the program to User Flash and set configuration to
always load from Flash. When setting up OEM protection it is important to download the user
program to RAM and User Flash before enabling the OEM protection. For example, the following
steps can be used to set up OEM protection.
1. Set OEM Key password (Must be at Access Level 4 to set OEM Key)
2. Download program to both RAM and User Flash.
3. Set OEM Protection to the Locked state (see firmware note below).
If you are storing a non-blank OEM key to flash memory, you should be careful to record the OEM key
for future reference. If disabling OEM protection, be sure to clear the OEM key that is stored in flash
memory.
Note: In CPU firmware versions 7.80 or later which support Enhanced Security (with merged
password tables), OEM Protection Lock must be explicitly set.
In earlier versions, the OEM Protection could be enabled in User Flash without explicitly
setting the OEM Protection to Locked. With the earlier firmware, a non-blank OEM Key that is
loaded from User Flash at power-up would result in an automatic OEM Lock. In CPU firmware
versions 7.80 or later (i.e. with merged passwords), this is no longer supported.
In firmware versions earlier than 6.01, the OEM protection was not preserved unless a battery
was attached.

4.9.3 Enhanced Security for Passwords and OEM Protection

Enhanced Security passwords are supported by CPU firmware versions 7.80 or later. This feature
provides a cryptographically secure password protocol between an SRTP client (for example Proficy
Machine Edition) and a PACSystems controller. Enhanced Security passwords operate in a very
similar fashion to the Legacy security password operation that is supported by previous firmware
releases.
Enhanced Security passwords are enabled in Proficy Machine Edition46. PME requires a password in
order to enable/disable the Enhanced Security mode of a target. This PME password restricts
changes to the security mode used by a specific PME target and is independent of any passwords
later configured on the controller.
Enabling Enhanced Security on a target does not force the controller to use only Enhanced Security.
The controller supports both Legacy and Enhanced Security requests concurrently. For example, one
PME target could be used to set initial passwords with Legacy security and a different PME target
with Enhanced Security could connect and authenticate with the same controller.
Passwords set with one password mechanism (Legacy or Enhanced Security) can be authenticated
and changed using the other mechanism, as long as the password is 7 characters or less. Setting
passwords with Enhanced Security that are greater than 7 characters prevents access using the
Legacy mechanism. For example, you could use Enhanced Security to set a 10-character password
for Level 4 and Level 3, but set a 7-character password for Level 2. In this case, a Legacy target could
be used to obtain Level 2 access, but the Legacy target could never access Level 4 or Level 3
because of 7-character limit of the Legacy scheme.
4.9.3.1 Password and OEM Protection in Systems that Load from Flash Memory
Caution
Be careful when setting passwords and loading passwords
from User Flash on every power-up. In this situation, it is not
possible to clear passwords back to a default state if the
Level 4 password and OEM key are forgotten.
For a recommended procedure, see OEM Protection in Systems that Load from Flash Memory.
46 To determine the required Proficy Machine Edition version, refer to the Important Product Information (IPI) document
provided with the CPU firmware version you are using.

4.9.4 Legacy/Enhanced Security Comparison

Feature Legacy (less secure) Enhanced (more secure)
Level 2, 3 and 4 protection Levels 2, 3 and 4 must be set or Passwords can be set individually
modified simultaneously. (If you only or in a group. When changing
want to change one, you must enter passwords, the old password for
all three.) that level is required in order to
change it.
Maximum password 7 characters 31 characters
length
Clearing passwords Passwords can be cleared back to Once a password is set, the
initial blank password values. Enhanced Security mode in PME
will not allow it to be cleared back
to a blank password. To revert to a
blank password, the CPU memory
must be cleared and power cycled.
Passwords ≤7 characters, Password verification and password Password verification and
set with either mode changes allowed. password changes allowed.
Passwords >7 characters, Password verification and password Password verification and
set with Enhanced Security changes not allowed. password changes allowed.
mode
Maximum OEM key length 7 characters. 31 characters.
OEM keys ≤7 characters, Can change OEM Protection Lock Can change OEM Protection Lock
set with Enhanced Security state state and the OEM key.
Cannot change the OEM key.
OEM keys >7 characters, Cannot change OEM Protection Lock Can change OEM Protection Lock
set with Enhanced Security state or the OEM key. state and the OEM key.

4.10 PACSystems I/O System

The PACSystems I/O system provides the interface between the CPU and other devices. The
PACSystems I/O system supports:
 I/O and Intelligent option modules.
 Ethernet Interface
 Motion modules (RX3i)
 PROFINET: CPE400 and CPE330 both permit one of their LANs to be configured as an embedded
PROFINET Controller. Alternately, the RX3i PROFINET Controller IC695PNC001 installs in the RX3i
Main I/O Rack47. The embedded PROFINET Controller and the IC695PNC001 are used to control
remote I/O drops. Refer to PACSystems RX3i PROFINET IO-Controller Manual, GFK-2571F or later.
Some examples of remote drops are:
o Standard rack-mounted I/O modules in RX3i racks scanned by the PROFINET scanner
IC695PNS001. Refer to PACSystems RX3i PROFINET Scanner Manual, GFK-2737
o A mini-drop consisting of one or two I/O modules and supervised by the IC695CEP001. Refer
to PACSystems RX3i CEP PROFINET Scanner User Manual, GFK-2883.
o A Genius Bus supervised by a Genius Communications Gateway (IC695GCG001). Refer to
PACSystems RX3i Genius Communications Gateway User Manual, GFK-2892.
 The Genius I/O system
o RX7i: A Genius I/O Bus Controller (GBC) module provides the interface between the RX7i CPU
and a Genius I/O bus. Refer to Series 90-70 Genius Bus Controller User’s Manual, GFK-2017.
o RX3i: A Genius Communications Gateway (IC695GCG001) provides the interface between
devices on the Genius I/O bus and a PROFINET Controller (IC695PNC001) which is installed in
the RX3i Main I/O rack. Refer to PACSystems RX3i Genius Communications Gateway User
Manual, GFK-2892.
o For information on Genius I/O, refer to Genius I/O System User’s Manual, GEK-90486-1 and
Genius I/O Analog and Discrete Blocks User’s Manual, GEK-90486-2.
47 Note that CPE400 does not support IC695PNC001, since it is a Rackless CPU. Both may co-exist on a PROFINET LAN.

4.10.1 I/O Configuration

4.10.1.1 Module Identification
In addition to the catalog number, the programming software stores a Module ID for each configured
module in the hardware configuration that it delivers to the CPU. The CPU uses the Module ID to
determine how to communicate with a given module.
When the hardware configuration is downloaded to the CPU (and during subsequent power-ups), the
CPU compares the Module IDs stored by the programmer with the IDs of the modules physically
present in the system. If the Module IDs do not match, a System Configuration Mismatch fault will be
generated.
Because I/O modules of similar type may share the same Module ID, it is possible to download a
configuration containing a module catalog number that does not match the module that is physically
present in the slot without generating a System Configuration Mismatch.
Certain discrete modules with both reference memory inputs and reference memory outputs will
experience invalid I/O transfer if incorrect configuration is stored from a similar mixed I/O module. No
fault or error condition will be detected during configuration store and the module will be
operational, although not in the manner described by configuration.
For example, a configuration swap between the IC693MDL754 output module and IC693MDL660
input module will not be detected as a configuration mismatch, but I/O data transfer between the
module and the CPU reference memory will be invalid. If the input module (MDL660) is sent the
configuration of the output module (MDL754) with the following parameters:
Reference Address: %Q601
Module Status Reference: %I33
Hold Last State Enable
It will receive inputs at the module status reference %I33 and the status of the module will be
received at %Q601.
If the output module is sent the configuration of the input module with the following parameters:
Reference Address: %I601
Input Filter: Enable
Digital Filter Settings Reference: %I65
It will output values at the digital filter settings reference %I65 and the status of the module will be
received at %I601.

4.10.1.2 Default Conditions for I/O Modules

Interrupts
Some input modules can be configured to send an interrupt to the application program. By default,
this interrupt is disabled and the input filter is set to slow. If changed by the programming software,
the new settings are applied when the configuration is stored and during subsequent power-cycles.
Outputs
Some output modules have a configurable output default mode that can be specified as either Off or
Hold Last State. If a module does not have a configurable output default mode, its output default
mode is Off. The selected action applies when the CPU transitions from RUN/Enabled to
RUN/Disabled or STOP Mode, or experiences a fatal fault.
At power-up, Series 90-30 discrete output modules default to all outputs off. They will retain this
default condition until the first output scan from the PACSystems controller. Analog output modules
can be configured with a jumper located on the removable terminal block of the module. The jumper
may be set to cause outputs to either default to zero or retain last state.
Inputs
Input modules that have a configurable input default mode can be configured to Hold Last State or
to set inputs to 0. If a module does not have a configurable input default mode, its input default
mode is Off. The selected action applies when the CPU transitions from RUN/Enabled to
RUN/Disabled or STOP Mode, or experiences a fatal fault.
For details on the power-up and STOP Mode behavior of other modules, refer to the documentation
for that module.
4.10.1.3 Multiple I/O Scan Sets
Up to 32 I/O scan sets can be defined for a PACSystems CPU. A scan set is a group of I/O modules
that can be assigned a unique scan rate. A given I/O module can belong to one scan set. By default,
all I/O modules are assigned to scan set 1, which is scanned every sweep.
For some applications, the CPU logic does not need to have the I/O information every sweep. The I/O
scan set feature allows the scanning of I/O points to be more closely scheduled with their use in user
logic programs. If you have a large number of I/O modules, you may be able to significantly reduce
scan time by staggering the scanning of those modules.
A disadvantage of placing all modules into different scan sets appears when the CPU is transitioning
from Stop to Run. In that case, scan sets with a programmed delay are not scanned on the first
sweep. These modules' outputs are not enabled until the new data has been scanned to them,
perhaps many scans later. Therefore, there is a period of time during which the user logic is
executing and some modules' outputs are disabled. During that time, outputs of those modules are in
the module’s stop-mode state. Stop-mode behavior is module-dependent. Some modules zero their
outputs, some hold their last scanned state (if any), and some force their outputs to a configured
default value. When the module's outputs are enabled, the module uses the last scanned value,
which will either be zero or the contents of the register the module uses to hold the corresponding
output values from the reference tables.

4.10.2 Genius I/O

The Genius Bus Controller (GBC) controls a single Genius I/O bus. Any type of Genius I/O device may
be attached to the bus.
In the I/O Fault Table, the rack, slot, bus, module, and I/O point number are given for a fault. Refer to
PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 9 for decoding.
In non-redundant systems, bus #1 refers to the bus on the single-channel GBC. In redundant
systems, bus number is represented as either #1 or #2.
4.10.2.1 Genius I/O Configuration
The programming software can configure a subset of the parameters associated with Genius I/O
blocks.
Genius I/O blocks have a number of parameters that can be set using the Genius I/O Hand-Held
Monitor. These parameter values are stored in EEPROM in the block itself. The serial bus address (SBA)
and baud rate must be set using the Genius I/O Hand-Held Monitor. For specific information on
Genius I/O block types, configuration, and setup, refer to the Genius I/O System User’s Manuals,
GEK-90486-1 and GEK-90486-2.
Through the COMMREQ function block, the application program can request the GBC to change any
default condition on a specific block. However, the block only accepts this change if it is not in Config
Protect mode. If Config Protect mode is set, only the Hand-Held Monitor can be used to change the
defaults. The format of the COMMREQ function block for Genius I/O is described in the Series 90-70
Genius Bus Controller User’s Manual, GFK-2017 and the Series 90-30 Genius Bus Controller User’s
Manual, GFK-1034.
4.10.2.2 Genius I/O Data Mapping
Genius I/O discrete inputs and outputs are stored as bits in the CPU Bit Cache memory. Genius I/O
analog data is stored in the application RAM allocated for that purpose (%AI and %AQ). Analog data
is always stored one channel per one word (16 bit).
An analog grouped module consumes (in the input and output data memories) only the amount of
data space required for the actual inputs and outputs. For example, the Genius I/O 115 Vac Grouped
Analog Block, IC660CBA100, has four inputs and two outputs. It consumes four words of Analog Input
memory (%AI) and two words of Analog Output memory.
A discrete grouped module, each point of which is configurable with the Hand-Held Monitor (HHM) to
be input, output, or output with feedback, consumes an amount in both discrete input memory (%I)
and discrete output memory (%Q) equal to its physical size. Therefore, the eight-point Discrete
Grouped Block (IC660CBD100) requires eight bits in the %I memory and eight bits in the %Q memory,
regardless of how each point on the block is configured.
Analog Grouped Block
The six-channel Analog Grouped block contains four analog input channels and two analog output
channels. When this block gets its turn on the Genius I/O Bus, it broadcasts the data for all four input
channels in one broadcast control message. Then, when the GBC gets its turn, it sends the data for
both output channels to the block in a directed control message.
Low-Level Analog Blocks
Unlike the Analog Grouped block, the low-level analog blocks, such as the Thermocouple and RTD
blocks, are input-only blocks. All have six channels.

4.10.2.3 Genius Global Data Communications

The PACSystems RX7i supports the sharing of data among multiple control systems that share a
common Genius I/O bus. This mechanism provides a means for the automatic and repeated transfer
of %G, %I, %Q, %AI, %AQ, %R, and %W data. No special application programming is required to use
global data since it is integrated into the I/O scan. Controllers that have Genius I/O capability can
send global data to an RX7i and can receive data from an RX7i. The programming software is used to
configure the receiving and transmitting of global data on a Genius I/O bus.
Note: Genius global data communications do not continue to operate when the RX7i CPU is in Stop-
I/O Scan Disabled mode. However, if the CPU is in Stop-I/O Scan Enabled mode, Genius global
data communications continue to operate.

4.10.3 I/O System Diagnostic Data Collection

Diagnostic data in a PACSystems I/O system is obtained in either of the following two ways:
 If an I/O module has an associated bus controller, the bus controller provides the diagnostic data
from that module to the CPU. For details on GBC faults, see PACSystems Handling of GBC Faults.
 For I/O modules not interfaced through a bus controller, the CPU’s I/O Scanner subsystem
generates the diagnostic bits based on data provided by the module.
The diagnostic bits are derived from the diagnostic data sent from the I/O modules to their I/O
controllers (CPU or bus controller). Diagnostic bits indicate the current fault status of the associated
module. Bits are set when faults occur and are cleared when faults are cleared.
Diagnostic data is not maintained for modules from other manufacturers. The application program
must use the BUS Read function blocks to access diagnostic information provided by those boards.
Note: At least two sweeps must occur to clear the diagnostic bits: one scan to send the %Q data to
the module and one scan to return the %I data to the CPU. Because module processing is
asynchronous to the controller sweep, more than two sweeps may be needed to clear the
bits, depending on the sweep rate and the point at which the data is made available to the
module.
4.10.3.1 Discrete I/O Diagnostic Information
The CPU maintains diagnostic information for each discrete I/O point. Two memory blocks are
allocated in application RAM for discrete diagnostic data, one for %I memory and one for %Q
memory. One bit of diagnostic memory is associated with each I/O point. This bit indicates the
validity of the associated I/O data. Each discrete point has a fault reference that can be interrogated
using two special contacts: a fault contact (-[F]-) and a no-fault contact (-[NF]-). The CPU collects this
fault data if enabled to do so by the programming software. The following table shows the state of
the fault and no-fault contacts.
Condition [FAULT] [NOFLT]
Fault Present ON OFF
Fault Absent OFF ON
4.10.3.2 Analog I/O Diagnostic Data

Diagnostic information is made available by the CPU for each analog channel associated with analog
modules and Genius analog blocks. One byte of diagnostic memory is allocated to each analog I/O
channel. Since each analog I/O channel uses two bytes of %AI and %AQ memory, the diagnostic
memory is half the size of the data memory.
The analog diagnostic data contains both diagnostics and process data with the process data being
the High Alarm and Low Alarm bits. The diagnostic data is referenced with the -[F]- and -[NF]-
contacts. The process bits are referenced with the high alarm (-[HA]- and low alarm (-[LA]-) contacts.
The memory allocation for analog diagnostic data is one byte per word of analog input and analog
output allocated by programming software. When an analog fault contact is referenced in the
application program, the CPU does an Inclusive OR on all bits in the diagnostic byte, except the
process bits. The alarm contact is closed if any diagnostic bit is ON and OFF only if all bits are OFF.

4.10.3.3 PACSystems Handling of GBC Faults

Defaulting of input data associated with failed/lost GBCs
When a GBC is missing, mismatched, or otherwise failed, the CPU applies the Input Default setting for
each device on that Genius bus when defaulting the input data. If the device is configured for HOLD
LAST STATE, the data is left alone. If the device is configured for OFF, the input data is set to 0. If a
redundant GBC is operational, the input data is not affected.
Application of default input and diagnostic data for lost redundant blocks
When a GBC reports that a redundant block is lost, the CPU updates the input data tables and input
diagnostic tables with the default data during the very next input scan. The output diagnostic data
tables are updated during the very next output scan.

4.11 Power-Up and Power-Down Sequences

4.11.1 Power-Up Sequence
System power-up consists of the following parts:
 Power-up self-test
 CPU memory validation
 System configuration
 Intelligent option module self-test completion
 Intelligent option module dual port interface tests
 I/O system initialization
4.11.1.1 Power-Up Self-Test
On system power-up, many modules in the system perform a power-up diagnostic self-test. The CPU
module executes hardware checks and software validity checks. Intelligent option modules perform
setup and verification of on-board microprocessors, software checksum verification, local hardware
verification, and notification to the CPU of self-check completion. Any failed tests are queued for
reporting to the CPU during the system configuration portion of the cycle.
If a low or failed battery (or Energy Pack fault) indication is present, a fault is logged in the CPU fault
table.
4.11.1.2 CPU Memory Validation
The next phase of system power-up is the validation of the CPU memory. First, if the system verifies
that user memory areas are still valid. A known area of user memory is checked to determine if data
was preserved. Next, if a ladder diagram program exists, a checksum is calculated across the _MAIN
ladder block. If no ladder diagram program exists, a checksum is calculated across the smallest
standalone C program.
When the system is sure that the user memory is preserved, a known area of the bit cache area is
checked to determine if the bit cache data was preserved. If this test passes, the Bit Cache memory is
left containing its power-up values. (Non-retentive outputs are cleared on a transition from STOP
Mode to RUN Mode.) If the checksum is not valid or the retentive test on the user memory fails, the bit
cache memory is assumed to be in error and all areas are cleared. The CPU is now in a cleared state,
the same as if a new CPU module were installed. All logic and configuration files must be stored from
the programmer to the CPU.
4.11.1.3 System Configuration
After completing its self-test, the CPU performs the system configuration. It first clears all system
diagnostic bits in the bit cache memory. This prevents faults that were present before power-down
but are no longer present from accidentally remaining as faulted. Then it polls each module in the
system for completion of the corresponding self-test.
The CPU reads information from each module, comparing it with the stored (downloaded) rack/slot
configuration information. Any differences between actual configuration and the stored
configuration are logged in the fault tables.

4.11.1.4 Intelligent Option Module Self-Test Completion

Intelligent option modules may take a longer time to complete their self-tests than the CPU due to
the time required to test communications media or other interface devices. As an intelligent option
module completes its initial self-tests, it tells the CPU the time required to complete the remainder of
these self-tests. During this time, the CPU provides whatever additional information the module
needs to complete its self-configuration, and the module continues self-tests and configuration. If the
module does not report back in the time it specified, the CPU marks the module as faulted and makes
an entry in one of the fault tables. When all self-tests are complete, the CPU obtains reports from the
module as generated during that particular module’s power-up self-test and places fault information
(if any) in the fault tables.
4.11.1.5 Intelligent Option Module Dual Port Interface Tests
After completion of the intelligent option module self-test and results reporting, integrity tests are
jointly performed on the dual-port interface used by the CPU and intelligent option module for
communications. These tests validate that the two modules are able to pass information back and
forth, as well as verify the interrupt and semaphore capabilities needed by the communications
protocol. After dual port interface tests are complete, the communications messaging system is
initialized.
4.11.1.6 I/O System Initialization
If the module is an input module, no further configuration is required. If the module is an output
module, the module is commanded to go to its default state. The output modules default to all
outputs off at power-up and in failure mode, unless configured otherwise.
A bus transmitter module is interrogated about what expansion racks are present in the system.
Based on the bus transmitter module’s response, the CPU adds those racks and their associated slots
into the list of slots to be configured.
Finally, the I/O Scanner performs its initialization. The I/O Scanner initializes all the I/O controllers in
the system by establishing the I/O connections to each I/O bus on the I/O controller and obtaining all
I/O configuration data from that I/O controller. This configuration data is compared with the stored
I/O configuration and any differences reported in the I/O Fault Table. The I/O Scanner then sends
each I/O controller a list of the I/O modules to be configured on the I/O bus. After the I/O controllers
have been initialized, the I/O Scanner replaces the factory default settings in all I/O modules with any
application-specified settings.

4.11.2 Power-Down Sequence

System power-down occurs when the power supply detects that incoming power has dropped for
more than 15ms.
4.11.3 Power Cycle Operation with an Energy Pack
Energy Packs offer distinct advantages over batteries:
a) significantly longer life cycles
b) they are more reliable
c) flammability during shipment is not an issue
d) in their end-of-life phase, their decline is a lot more gradual.
The system design includes the ability of the CPU and the Energy Pack to monitor each other in real
time. This permits the user to monitor alarms and thereby determine when to replace a capacitor
pack. The capacitor pack is normally replaced while the CPU is powered on, giving it time to charge
up before any subsequent loss of power. Users should target periods which are expected to be free
from electrical events, such as thunderstorms, to carry out such work. Capacitor packs may also be
replaced while power is off.
When power is lost, the Energy Pack supplies current and maintains voltage levels for a period of
time sufficient to permit the connected CPU to save all dynamic memory to non-volatile memory.
When power is restored, the CPU will not start running its application until the Energy Pack signals
that it is fully charged. The CPU will then resume operation using the contents of memory retained at
the previous loss of power event. The Energy Pack charges continuously during normal operation.
The RX3i and RX7i product lines encompass several different Energy Packs, so it is important to use
compatible products:
CPU IC695CPE400 IC695CPE330 IC695CPE305 ICRXICTL000
IC695CPE310
Energy Pack IC695ACC403 IC695ACC402 IC695ACC400 ICRXIACCEPK01
Capacitor Pack IC695ACC413 IC695ACC412 IC695ACC400 ICRXIACCCPK01
Connecting Cable IC695CBL003 IC695CBL002 IC695CBL001 ICRXIACCCBL01
Documentation GFK-3000 GFK-2939 GFK-2724 GFK-2741
User memory is preserved only if the compatible Energy Pack is connected (and charged) at
power-down.
If the Energy Pack is connected at power-up, the CPU waits for it to charge up before beginning
normal operations. For CPE330/CPE400, this typically takes up to 90 seconds.
In the event the Energy Pack fails to charge up in a reasonable amount of time, or is absent, the CPU
will time out the wait period and will then commence operations without the Energy Pack. When this
occurs, the CPU is vulnerable to loss of memory, should another power failure occur. It is critical to
monitor the status bits shown in Energy Pack Status Bit Operation so that human intervention can be
summoned.
Removing or reconnecting the Energy Pack while the connected CPU is powered off has no effect on
the preservation of user memory.
Note: Because the Time of Day (TOD) clock is powered by a separate Real Time Clock battery in
CPE305/CPE310/CPE330/CPE400, the Energy Pack has no effect on the CPU TOD value.

4.11.3.1 Energy Pack Status Bit Operation

As shown in the table below, the CPU application program can monitor the status of the attached
Energy Pack via %S0014 (PLC_BAT) and %SA0011 (LOW_BAT). For more details, refer to the chapter
on Diagnostics in PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950.
PLC_BAT (%S0014) LOW_BAT (%SA0011) Energy Pack Status
0 0 Energy Pack connected and operational (may be charging)
1 1 Energy Pack not connected or has failed
0 1 Energy Pack is nearing its end-of-life and should be
replaced.
The LEDs on the Energy Pack also indicate its status. Refer to the documentation for each product for
corresponding LED status.
4.11.3.2 Energy Pack Replacement
If an Energy Pack fails, you can replace it while the CPU is in operation. Use a compatible new unit or
a compatible replacement Cap Pack. Whenever an Energy Pack is replaced, the newly installed Cap
Pack must build up its charge.
In the case of ACC402 attached to CPE330, the Energy Pack, when hot-swapped, draws minimal
current in order to recharge: it may therefore take up to 10 minutes for ACC402 to charge
completely. This is normal operation. Similarly for ACC403/CPE400.
If a loss of power occurs while the Energy Pack is disconnected, or before the capacitors are fully
charged, memory loss may occur.
4.11.3.3 CPE330/ACC402 Status Detection & Fault Reporting
Both the CPE330 and ACC402 contain intelligence, allowing each to determine the status of the
other. This permits the CPU to report various conditions to the user via the status bits discussed in
Energy Pack Status Bit Operation.
Whenever the CPE330 detects any kind of issue with the ACC402 Energy Pack, it resumes normal
operation and issues warnings or faults to the user. The table below details the various permutations
possible at power-up. If the Cap Pack is removed during normal operation, this fault will be reported
as a failed battery fault.
Energy Pack Base Cap Pack CPE330 power-up response
Not present Not present Detects missing ACC402 and boots up immediately but does not
(removed or (removed or use any stored memory when resuming operations. Issues fail
failed) failed) battery fault.
Detects missing ACC402 and boots up immediately but does not
Not present Present
use any stored memory when resuming operations. Issues fail
(bad base) (good cap pack)
battery fault.
Not present When the CPU does not see a fully charged status within 90
Present
(removed or seconds, it does not use any stored memory when resuming
(good base)
failed) operations. Issues fail battery fault.
The CPU will wait for fully charged status within timeout period
Present Present
and then resume operation using the contents of memory
(good base) (good cap pack)
retained at the previous loss of power event
If the CPU does not see a fully charged status within 90 seconds, it
Present Present
does not use any stored memory when resuming operations.
(suspicious) (suspicious)
Issues fail battery fault.

4.11.3.4 CPE400/ACC403 Status Detection & Fault Reporting

Both the CPE400 and ACC403 contain intelligence, allowing each to determine the status of the
other. This permits the CPU to report various conditions to the user via the status bits discussed in
Energy Pack Status Bit Operation.
Whenever the CPE400 detects any kind of issue with the ACC403 Energy Pack, it resumes normal
operation and issues warnings or faults to the user. The table below details the various permutations
possible at power-up. If the Cap Pack is removed during normal operation, this fault will be reported
as a failed battery fault.
Energy Pack Base Cap Pack CPE400 power-up response
Not present Not present Detects missing ACC403 and boots up immediately but does not
(removed or (removed or use any stored memory when resuming operations. Issues fail
failed) failed) battery fault.
Detects missing ACC403 and boots up immediately but does not
Not present Present
use any stored memory when resuming operations. Issues fail
(bad base) (good cap pack)
battery fault.
Not present When the CPU does not see a fully charged status within 45
Present
(removed or seconds, it does not use any stored memory when resuming
(good base)
failed) operations. Issues fail battery fault.
The CPU will wait for fully charged status within timeout period
Present Present
and then resume operation using the contents of memory
(good base) (good cap pack)
retained at the previous loss of power event
If the CPU does not see a fully charged status within 45 seconds, it
Present Present
does not use any stored memory when resuming operations.
(suspicious) (suspicious)
Issues fail battery fault.

4.11.4 Retention of Data Memory Across Power Failure

The following types of data are preserved across a power cycle with an operational battery (or for
CPE305, CPE310, CPE330, or CPE400 with an operational and attached Energy Pack):
 Application program
 Fault tables and other diagnostic data
 Checksums on programs and blocks
 Override data
 Data in register (%R), local register (%L), and program register (%P) memory
 Data in analog memory (%AI and %AQ)
 State of discrete inputs (%I)
 State of retentive discrete outputs (%Q)
 State of retentive discrete internals (%M)
The following types of data are not preserved across a power cycle:
 State of discrete temporary memory (%T)
 %M and %Q memories used on non-retentive -()- coils
 State of discrete system internals (system bits, fault bits, reserved bits).

Chapter 5 Communications
This chapter describes the Ethernet and Serial communications features of the PACSystems CPU.
Ethernet communications may be handled by the embedded CPU Ethernet port(s) or by an
IC695ETM001 module installed in an RX3i rack. Refer to PACSystems RX7i & RX3i TCP/IP Ethernet
Serial communications may be handled by the embedded CPU Serial port(s) or by an IC695CMM002
or IC695CMM004 module installed in an RX3i rack. Refer to PACSystems RX3i Serial Communications
Modules User’s Manual, GFK-2460.
This chapter contains the following information with respect to the embedded CPU ports:
■ Ethernet Communications
■ Serial Communications
■ Series 90-70 Communications and Intelligent Option Modules

Chapter 5. Communications
5.1 Ethernet Communications

For details on Ethernet communications for PACSystems, please refer to the following manuals:
PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224
PACSystems TCP/IP Ethernet Communications Station Manager User Manual, GFK-2225.
5.1.1 Embedded Ethernet Interface
5.1.1.1 RX3i
RX3i CPE305, CPE310, CPE330 and CPE400 CPUs provide one or more embedded Ethernet interfaces.
If used, each interface connects to a Local Area Network (LAN).
The corresponding RJ45 Ethernet port(s) automatically sense the data rate on the attached LAN
(1 Gbps, 100 Mbps or 10 Mbps), as well as the corresponding communication mode (half-duplex or
full-duplex), and the corresponding cabling arrangement (straight through or crossover). Automatic
detection greatly simplifies installation procedures.
See RX3i CPU Features and Specifications or RX7i CPU Features and Specifications to determine the
complete list of Internet protocols supported by each CPU.
Some important protocols supported by all RX3i CPUs are:
 TCP/IP, which provides basic Internet capabilities;
 SRTP, which is proprietary and which provides the interface with the PME programming and
configuration software and supports communications with certain control systems and
supervisory computer layers in the factory;
 Modbus/TCP, which supports the Modbus messaging structure over the Internet.
On the CPE305/CPE310 models, the same shared processor performs both Ethernet port processing
and Controller logic processing.
On the CPE330, the dual core CPU enables communication to be handled by one core while CPU logic
and I/O scanning is handled by the second core. Furthermore, each LAN interface is controlled by a
dedicated Network Interface Controller (NIC). In the CPE400, one of the four microprocessor cores is
dedicated to handling the communications function (LAN1, LAN2 and LAN3).
As a result of the hardware advances in the CPE330 and CPE400, a higher level of processing power
is provided in support of each LAN. This is especially important at higher data rates. It also offloads
the handling of Ethernet-level activity from the processor core tasked with performing CPU logic and
I/O scanning, permitting that core to run more efficiently.
Each interface on a LAN must have a unique IP Address and a non-overlapping IP subnet. This is
configured in PME. Care must be taken to survey the entire connected network architecture in order
to tabulate the IP addresses and IP subnets already in use, both on the local networks and on any of
its routed subnets connected with a gateway. Never assign a conflicting IP Address or configure
duplicate IP subnets.

The following examples would be problematic:

Problem example #1:
Figure 32: CPE330 Overlapping Local IP Subnet Example

The issue demonstrated in Figure 32 is that requests entering one CPE330 interface can be routed
out the other interface since both CPE330 Ethernet ports have been configured to be on the same
network (255.255.0.0) but are physically connected to separate networks. Avoid this by assigning
non-overlapping Subnets.
Problem example #2:
A user wishes to communicate through a routed network to an RX3i CPU with multiple network
interfaces (CPE330, in this example). This remote IP device is configured with the following IP
parameters:
IP 192.168.0.5
Subnet Mask 255.255.255.0
Gateway 192.168.0.250
LAN1 and LAN2 on the CPE330 are initially configured with following problematic IP parameters:
LAN1 LAN2
IP 10.10.0.1 192.168.0.1
Subnet Mask 255.255.255.0 255.255.255.0
Gateway 10.10.0.249 0.0.0.0
The user intends to communicate between the remote device and CPE330 LAN1 (Figure 33).
IP Address routing allows the CPE330 to receive the remote IP requests through the respective
gateways (192.168.0.250 for the remote node and 10.10.0.249 for CPE330 LAN1). However, since
CPE330 LAN2 shares the same IP subnet as the remote network (192.168.0.x), responses may be
routed to the local 192.168.0.x network rather than to the remote network (Figure 34).
The duplicate IP subnet in the example must be eliminated. One way to do this is simply change the
IP Address assigned to CPE330 LAN2 from 192.168.0.1 to 192.168.1.1 thereby creating a non-
overlapping 192.168.1.x network. In short, consider the totality of the network when assigning
IP subnets and IP Addresses.

Figure 33: Expected Response Path
Figure 34: Actual Response Path

5.1.1.2 RX7i
RX7i CPUs have an embedded Ethernet interface that provides TCP/IP communications with
programming software and other control systems. These communications use the proprietary SRTP
protocol and the standard Modbus/TCP protocol over a four-layer TCP/IP (Internet) stack. The
Ethernet interface also supports Ethernet Global Data protocol using UDP (User Datagram Protocol).
The embedded Ethernet interface has two RJ45 Ethernet ports. Either or both of these ports may be
attached to other Ethernet devices. Each port automatically senses the data rate (10 Mbps or
100 Mbps), communication mode (half-duplex or full-duplex), and cabling arrangement (straight
through or crossover) of the attached link.
Caution
The two ports on the Ethernet Interface must not be
connected, directly or indirectly to the same device. The hub
or switch connections in an Ethernet network must form a
tree; otherwise duplication of packets may result.

5.1.1.3 10Base-T/100Base-Tx Port Pin Assignments

Pin assignments are the same for the RX3i and RX7i embedded Ethernet ports.
Pin Number Signal Description
1 TD+ Transmit Data +
2 TD- Transmit Data -
3 RD+ Receive Data +
4 NC No connection
5 NC No connection
6 RD- Receive Data -
7 NC No connection
8 NC No connection
5.1.1.4 Recovering a Lost IP Address

See Establishing Initial Ethernet Communications, Section 3.4.1.
5.1.2 Ethernet Interface Modules
In addition to Ethernet interfaces embedded in certain CPUs (see RX3i CPU Features and
Specifications and RX7i CPU Features and Specifications), the RX7i and RX3i systems support rack-
based Ethernet Interface modules. These modules are not interchangeable.
For details about the capabilities, installation, and operation of these modules, refer to PACSystems
RX7i & RX3i TCP/IP Ethernet Communications User Manual GFK-2224 and PACSystems TCP/IP Ethernet
Communications Station Manager User Manual, GFK-2225.
Type Catalog Number Description
RX7i IC698ETM001 Ethernet peripheral VME module
RX3i IC695ETM001 Ethernet peripheral PCI module

5.2 Serial Communications

RX3i CPUs, except CPE330, support one or more serial ports (see Section 2.2). RX7i CPUs support three
serial ports (see Section 2.3). The independent on-board serial ports of the CPU are accessed via
connectors on the front of the module. COM1 and COM2 provide serial interfaces to external devices.
COM1 is also used for firmware upgrades. The third serial port (COM3) on RX7i CPUs is used as the
Ethernet Station Manager port.
5.2.1 Serial Port Communications Capabilities
COM1 and COM2 can each be configured for one of the following modes. For details on CPU
configuration, refer to Chapter 3.
 RTU Slave – The port can be used for the Modbus RTU slave protocol. This mode also permits
connection to the port by an SNP master, such as the WinLoader utility or the programming
software. For details, refer to Chapter 6, Serial I/O, SNP & RTU Protocols.
 Message Mode – The port is available for access by user logic. This enables C language blocks to
perform serial port I/O operations via C Runtime Library functions.
 Available – The port is not to be used by the CPU firmware.
 SNP Slave – The port can only be used for the SNP slave protocol. For details, refer to Chapter 6,
Serial I/O, SNP & RTU Protocols.
 Serial I/O – The port can be used for general-purpose serial communication through use of
COMMREQ functions. For details, refer to Chapter 6, Serial I/O, SNP & RTU Protocols.
5.2.1.1 Features Supported
Serial Port 3
Serial Port 1 Serial Port 2
Feature (Station Mgr)
(COM1) (COM2)
RX7i only
RTU Slave protocol Yes Yes No
SNP Slave Yes Yes No
Serial I/O – used with COMMREQs Yes Yes No
Firmware Upgrade PLC in
No No
(WinLoader utility) STOP/No IO mode
Message Mode –used only with C blocks
(C Runtime Library Functions: Yes Yes No
serial read, serial write, sscanf, sprintf)
Station Manager (RX7i only) No48 No48 Yes
RS-232 Yes No Yes
RS-485 No Yes No
48 RX3i CPE305, CPE310, CPE330, ETM001 & EDS001 support Station Manager using UDP over Ethernet, but not via serial
communications.

5.2.2 Configurable STOP Mode Protocols

You can configure the protocol to be used in STOP Mode, based upon the configured serial port (RUN
Mode) protocol. The Run/Stop protocol switching is independently configured for each serial port.
The RUN Mode protocol setting determines which choices are available for STOP Mode. If a STOP
Mode protocol is not selected, the default STOP Mode protocol is used. For details, refer to COM1 and
COM2 Parameters in Chapter 3.
5.2.3 Serial Port Pin Assignments
5.2.3.1 COM1 (RS-232, 9-pin Subminiature D Connector)
This port has a 9-pin, female, D-sub connector with a standard pin out. This is a DCE (data
communications equipment) port that allows a simple straight-through cable to connect with a
standard AT-style RS-232 port.
The CPE310 provides the DCD and RI signals to support point-to-point protocol (PPP).
COM1 RS-232 Signals
RX3i CPU, RX3i CRU,
RX3i CPE310 Model
and RX7i CPE Models
Pin No. 49 Signal Name Description Pin No.49 Signal Name Description
1 NC No Connection 1 DCD Data Carrier Detect
2 TXD Transmit Data 2 TXD Transmit Data
3 RXD Receive Data 3 RXD Receive Data
4 DSR Data Set Ready 4 DSR Data Set Ready
5 0V Signal Ground 5 COM Signal Ground
6 DTR Data Terminal Ready 6 DTR Data Terminal Ready
7 CTS Clear to Send 7 CTS Clear to Send
8 RTS Request to Send 8 RTS Request to Send
9 NC No Connection 9 RI Ring Indicator
5.2.3.2 COM1 (RS-232, RJ-25 Connector)

The CPE305 provides RS-232 communications via an RJ-25 connector and requires shielded cable
IC693CBL316.
CPE305 COM1 RS-232 Signals
Pin No. Signal Name Description
1 CTS Clear to Send
2 TXD Transmit Data
3 0V Signal Ground
4 0V Signal Ground
5 RXD Received Data
6 RTS Request to Send
49 Pin 1 is at the bottom right of the connector as viewed from the front of the module.

5.2.3.3 COM1 (RS232, RJ45 Connector)

The RJ45 Connector is provided for COM1 on CPE400 only. It has the following pinout.
Pin No.50 Signal Name Description
1 NC No Connection
2 NC No Connection
3 TX Transmit Data
4 RX Receive Data
5 0V Signal Ground
6 NC No Connection
7 NC No Connection
8 NC No Connection
Figure 35: COM1 Port CPE400
50 Pin 1 is the leftmost pin as shown in Figure 35.

5.2.3.4 COM2 (RS-485, 15-pin Female D-sub Connector) –RX7i CPU/CRU Models
This port does not supply +5Vdc volts, therefore RS-485 to RS-232 conversion requires a converter
that is self-powered. It does not support the RS-485 to RS-232 adapter IC690ACC901.
This is a DCE port that allows a simple straight-through cable to connect with a standard AT-style
RS-232 port.
COM2 RS-485 Signals
1 Shield Cable Shield
Located at the bottom right of the connector
as viewed from the front of the module.
2 NC No Connection
3 NC No Connection
4 NC No Connection
5 NC No Connection
6 RTS(A) Differential Request to Send A
7 0V Signal Ground
8 CTS(B‘) Differential Clear To Send
9 RT51 Resistor Termination
10 RD(A‘)51,52 Differential Receive Data A
11 RD(B‘)52 Differential Receive Data B
12 SD(A) Differential Send Data A
13 SD(B) Differential Send Data B
14 RTS(B’) Differential Request To Send B
15 CTS(A’) Differential Clear To Send A
51 To provide termination using the built-in 120Ω resistor, install a jumper between pins 9 and 10.
52 To provide termination using an external resistor, connect a user-supplied resistor across pins 10 and 11.

5.2.3.5 COM2 (RS-485, 15-pin Female D-sub Connector) – All RX3i CPU/CRU Models & RX3i
CPE310
This is a DCE port that allows a simple straight-through cable to connect with a standard AT-style
RS-232 port.
COM2 RS-485 Signals
1 Shield Cable Shield
Located at the bottom right of the connector as viewed from the front of
the module.
2 NC No Connection
3 NC No Connection
4 NC No Connection
5 +5Vdc Logic Power: Provides isolated +5Vdc power (300mA maximum) for
powering external options.
6 RTS(A) Differential Request to Send A
7 0V Signal Ground
8 CTS(B‘) Differential Clear To Send B
9 RT51 Resistor Termination
10 RD(A‘)51, 52 Differential Receive Data A
11 RD(B‘)52 Differential Receive Data B
12 SD(A) Differential Send Data A
13 SD(B) Differential Send Data B
14 RTS(B’) Differential Request To Send B
15 CTS(A’) Differential Clear To Send A

5.2.3.6 COM3 (RX7i only)

COM3, the Station Manager serial port used to support the embedded Ethernet Interface, is RS-232
compatible. COM3 has a 9-pin, female, D-connector. This is a DCE port that allows a simple straight-
through cable to connect with a standard AT-style RS-232 port. This port contains full use of the
standard RS-232 signals for future use with point-to-point protocol (PPP).
Station Manager RS-232 Signals
Pin No.49 Signal Name Description
1 DCD Data Carrier Detect
2 TXD Transmit Data
3 RXD Receive Data
4 DSR Data Set Ready
5 0V Signal Ground
6 DTR Data Terminal Ready
7 CTS Clear To Send
8 RTS Request To Send
9 RI Ring Indicator

5.2.4 Serial Port Electrical Isolation

Some serial communication ports are isolated, while others are not, as indicated in the following
table:
Family Model COM1 COM2 COM3
RX3i CPU310 Non-Isolated Non-Isolated N/A
CPU315 Non-Isolated Non-Isolated N/A
CPU320/CRU32 Non-Isolated Non-Isolated N/A
0
CPE305 Non-Isolated N/A N/A
CPE310 Non-Isolated Non-Isolated N/A
CPE330 N/A N/A N/A
CPE400 Non-Isolated N/A N/A
RX7i CPE010 Optocoupler Isolated Optocoupler Isolated Optocoupler Isolated
CPE020/CRE020 Optocoupler Isolated Optocoupler Isolated Optocoupler Isolated

5.2.5 Serial Cable Lengths and Shielding

The connection from a CPU serial port to the serial port on a computer or other serial device requires
a serial cable. Maximum cable lengths (the total distance from the CPU to the last device attached to
the serial cable) are:
Maximum Cable
Port Cable Type
Length
COM1 (RS-232) 15 m (50 ft.) Shielded cable required for
RX3i;
Shielded cable optional for RX7i
COM2 (RS-485) 1200 m (4000 ft.) Shielded cable required for all
models that support this port
STA MGR/COM3 (RS-232) 15 m (50 ft.) Shielded cable optional (RX7i
only)
Note: For details on conformance to radiated emissions standards, refer to Appendix A in the
following manuals:
PACSystems RX7i Installation Manual, GFK-2223
PACSystems RX3i System Manual, GFK-2314

5.2.6 Serial Port Baud Rates

COM1 COM2 Station Mgr (COM3)
Protocol
(RS-232) (RS-485) (RS-232)
RTU Slave 1200, 2400, 4800, 1200, 2400, not supported
9600, 19.2K, 38.4K, 4800, 9600,
57.6K, 115.2K 19.2K, 38.4K,
57.6K, 115.2K
Firmware 1200, 2400, 4800, Not supported not supported
Upgrade via 9600, 19.2K, 38.4K,
WinLoader 57.6K, 115.2K
Message Mode 1200, 2400, 4800, 1200, 2400, not supported
9600, 19.2K, 38.4K, 4800, 9600,
57.6K, 115.2K 19.2K, 38.4K,
57.6K, 115.2K
SNP Slave 1200, 2400, 4800, 1200, 2400, not supported
9600, 19.2K, 38.4K, 4800, 9600,
57.6K, 115.2K 19.2K, 38.4K,
57.6K, 115.2K
Serial I/O 1200, 2400, 4800, 1200, 2400, not supported
9600, 19.2K, 38.4K, 4800, 9600,
57.6K, 115.2K 19.2K, 38.4K,
57.6K, 115.2K

5.3 Series 90-70 Communications and Intelligent Option Modules

PACSystems RX7i supports the following Series 90-70 communications and intelligent option
modules:
 Communications Coprocessor Module (CMM), IC697CMM711
 Programmable Coprocessor Module (PCM), IC697PCM711
 DLAN Interface Module, IC697BEM763
5.3.1 Communications Coprocessor Module (CMM)
PACSystems RX7i CPUs with versions 1.50 and higher support IC697CMM711 modules with firmware
versions 4.20 and higher. You must ensure that you are using a valid version of the CMM firmware
because the CPU cannot check the CMM’s firmware version. (The module’s firmware version can be
found on a label attached to the EEPROM.)
PACSystems does not support the following with an IC697CMM711:
 Access to Symbolic variables
 WAIT mode COMMREQs.
 Connecting the programming software to the CPU through the CMM’s serial ports.
 Permanent datagrams.
The following restrictions apply when using the IC697CMM711 with PACSystems:
 Access to %W references is partially supported. Only offsets 0—65535 of %W can be accessed
via the CMM.
 The Program Name is currently always LDPROG1 for PACSystems.
 Reads and writes beyond currently configured reference table limits will report a minor code
error of 90 (REF_OUT_OF_RANGE) instead of F4 (INVALID_PARAMETER) as reported on the Series
90-70.
 In case of ERROR NACK, the Control Program number, privilege level and other piggyback status
data will be set to 0.
 PACSystems CPUs return the major/minor type of the 90-70 CPX935 (major type 12, minor type
35) to the CMM scratch pad memory when communicating with a CMM.
 Control Program Number will be returned as 01 in PACSystems instead of FF as reported on the
Series 90-70.
 If your RX7i application program needs to access the dual port memory of a CMM, use the BUS
READ and WRITE functions. When accessing the CMM, set the Region parameter on the function
block to 1. (For the CMM, region 1 is predefined to be the module's entire dual port memory.)
Note: For details on operation of the IC697CMM711, refer to the Series 90 PLC Serial
Communications User’s Manual, GFK-0582.

5.3.2 Programmable Coprocessor Module (PCM)

PACSystems RX7i CPUs with versions 1.50 and higher support IC697PCM711modules with firmware
versions 4.05 and higher. You must ensure that you are using a valid version of the PCM firmware
because the CPU cannot check the PCM’s firmware version. (The module’s firmware version can be
PACSystems does not support the following with an IC697PCM711:
 Connecting the programming software to the CPU through the serial ports on the PCM711.
 Access to Symbolic variables.
 WAIT mode COMMREQs.
 The following C functions are not supported:
- chk_genius_bus
- chk_genius_device
- get_cpu_type_rev
- get_memtype_sizes
- get_one_rackfault
- get_rack_slot_faults
 The C function write_dev will not write to read only references (%S references, transition bits, and
override bits). If this is attempted, the call will fail at run time and return an error code.
 The following restrictions apply when using the IC697PCM711 with PACSystems:
 Access to %W references is partially supported. Only offsets 0—65535 of %W can be accessed
via the PCM.
 The Program Name is currently always LDPROG1 for PACSystems.
 In case of ERROR NACK, the Control Program number, privilege level and other piggyback status
data will be set to 0.
 If an application program running on the PCM accesses the VME bus, the VME addresses being
used by that program must agree with the PACSystems RX7i VME address assignments. The
PACSystems RX7i VME address assignments are described in the PACSystems RX7i User’s Guide
to Integration of VME Modules, GFK-2235.
 PACSystems CPUs return the major/minor type of the Series 90-70 CPX935 (major type 12, minor
type 35) to the PCM scratch pad memory when communicating with a PCM.
 If your RX7i application program needs to access the PCM’s dual port memory, use the BUS READ
and WRITE functions. When accessing the PCM, set the Region parameter on the function block
to 1. (For the PCM, region 1 is predefined to be the module's entire dual port memory.)
Note: For details on operation of the IC697PCM711, refer to Series 90 Programmable Coprocessor
Module and Support Software, GFK-0255.

5.3.3 DLAN/DLAN+ (Drives Local Area Network) Interface

PACSystems RX7i CPUs with versions 1.50 and higher support IC697BEM763 modules with firmware
versions 3.00 and higher. You must ensure that you are using a valid version of the PCM firmware
because the CPU cannot check the DLAN’s firmware version. (The module’s firmware version can be
If your RX7i application program needs to access the DLAN’s dual port memory, use the BUS READ
and WRITE functions. When accessing a DLAN module, set the Region parameter on the function
block to 1. (For the DLAN module, region 1 is predefined to be the module's entire dual port memory.)
Note: The DLAN Interface module is a specialty module with limited availability. If you have a DLAN
system, refer to the Series 90-70 DLAN/DLAN+ Interface Module User’s Manual, GFK-0729, for
details.

Chapter 6 Serial I/O, SNP & RTU Protocols
This chapter discusses the following topics related to communications on CPU serial ports COM1 and
COM2:
 Configuring Serial Ports Using COMMREQ Function 65520
 Serial I/O Protocol
 RTU Slave Protocol
 SNP Slave Protocol
Details of the RTU and SNP protocol are described in the Series 90 PLC Serial Communications User’s
Manual, GFK-0582.

Chapter 6. Serial I/O, SNP & RTU Protocols
6.1 Configuring Serial Ports Using COMMREQ Function 65520

The Serial Port Setup COMMREQ function 65520 (FFF0 hex) may be used to activate a serial
communication protocol for a serial port, overriding the protocol that was specified in the port
settings of the CPU configuration. The COMMREQ installed protocol remains active as long as the CPU
is in RUN Mode. When the CPU is STOPped, the COMMREQ installed protocol is removed, and the
protocol settings from the CPU configuration are reactivated.
The COMMREQ requires that all its command data be placed in the correct order (in a command
block) in the CPU memory before it is executed. The COMMREQ should be executed by a contact of a
one-shot coil to prevent sending the data multiple times. For details on the operands and command
block format used by the COMMREQ function, refer to PACSystems RX7i and RX3i CPU Programmer’s
Reference Manual, GFK-2950 Chapter 4.
The COMMREQ uses the following TASKs to specify the port for which the operation is intended:
task 19 for COM1
task 20 for COM2
Note: Because address offsets are stored in a 16-bit word field, the full range of %W memory type
cannot be used with COMMREQs.
6.1.1 COMMREQ Function Example
In the example, when %M0021 is ON, a Command Block located starting at %R0032 is sent to COM2
(communications task 20) of the CPU (rack 0, slot 0). If an error occurs processing the COMMREQ,
%Q0110 is set.
6.1.2 Timing
If a port configuration COMMREQ is sent to a serial port that currently has an SNP master (for
example, the programmer) connected to it, the COMMREQ function returns an error code to the
COMMREQ status word.
6.1.3 Sending Another COMMREQ to the Same Port
After sending a COMMREQ to configure a serial port, the application program should monitor the
COMMREQ status word to determine when it can begin sending protocol specific COMMREQs to that
port. It is recommended that the application clear the COMMREQ status word prior to issuing the
configuration change. The status word will be set to a nonzero value when the request has been
processed.

6.1.4 Invalid Port Configuration Combinations

The Machine Edition programming software safeguards against the download of some hardware
configurations that would prevent the programmer from communicating serially with the CPU. In a
system that does not have an embedded Ethernet module, if a rack-based Ethernet is not present, a
serial connection is required for programmer communications.
For CPE305/CPE310 CPUs, which have an embedded Ethernet port that, when configured, is available
for programmer communications, the safeguards on serial port configurations are still enforced.
6.1.5 COMMREQ Command Block Parameter Values
The following table lists common parameter values that are used within the COMMREQ command
blocks for configuring a serial port. All values are in decimal.
Parameter Values
Protocol Selector 1 = SNP
3 = RTU
5 = Serial I/O
7 = Message Mode
Data Rate 0 = 300
1 = 600
2 = 1200
3 = 2400
4 = 4800
5 = 9600
6 = 19200
7 = 38400
8 = 57600
9 = 115200
Parity 0 = None
1 = Odd
2 = Even
Flow Control 0 = Hardware [RTS / CTS]
1 = None
2 = Software [XON / XOFF] (Serial I/O only)
Bits Per Character 0 = 7 bits
1 = 8 bits
Stop Bits 0 = 1 stop bit
1 = 2 stop bits
Duplex Mode 0 = 2-wire
1 = 4-wire
2 = 4-wire transmitter always on
Turnaround Delay (SNP only) 0 = none
1 = 10ms
2 = 100ms
3 = 500ms
Timeout (SNP only) 0 = Long (8 sec)
1 = Medium (2 sec)
2 = Short (500ms)
3 = None (200ms)

6.1.6 Example COMMREQ Command Blocks for Serial Port Setup function
The following COMMREQ command blocks provide examples for configuring the various protocols. All
values are in decimal unless followed by an H indicating hexadecimal.
Note that an example is not provided for Message Mode, but it can be setup with a command block
similar to the one for Serial I/O, with a value of 7 for the protocol selector.
Example COMMREQ Command Block for Configuring SNP Protocol
Values Meaning
Address 16 Data Block Length
Address + 1 0 = No Wait (WAIT mode not supported) WAIT/NOWAIT Flag
Address + 2 0008 = %R, register memory Status Word Pointer Memory
Type
Address + 3 Zero-based number that gives the address of the COMMREQ Status Word Pointer Offset
status word (for example, a value of 99 gives an address of
100 for the status word)
Address + 4 not used Idle Timeout Value
Address + 5 not used Maximum Communication
Time
Address + 6 FFF0H Command Word (serial port
setup)
Address + 7 1 = SNP Protocol
Address + 8 0 = Slave Port Mode
Address + 9 See COMMREQ Command Block Parameter Values. Data Rate
Address + 10 0 = None, 1 = Odd, 2 = Even Parity
Address + 11 not used (SNP always chooses NONE by default) Flow Control
Address + 12 0 = None, 1 = 10ms, 2 = 100ms, 3 = 500ms Turnaround Delay
Address + 13 0 = Long, 1 = Medium, 2 = Short, 3 = None Timeout
Address + 14 not used (SNP always chooses 8 bits by default) Bits Per Character
Address + 15 0 = 1 Stop Bit, 1 = 2 Stop bits Stop Bits
Address + 16 not used Interface
Address + 17 not used (SNP always chooses 4-wire mode by default) Duplex Mode
Address + 18 user-provided 53 Device identifier bytes 1 and 2
53 The device identifier for SNP Slave ports is packed into words with the least significant character in the least significant
byte of the word. For example, if the first two characters are “A” and “B,” the Address + 18 will contain the hex value 4241.

Example COMMREQ Data Block for Configuring RTU Protocol

Values Meaning
Address 13, or 17 Data Block Length
Type
Address + 3 Zero-based number that gives the address of the Status Word Pointer Offset
COMMREQ status word (for example, a value of 99 gives an
address of 100 for the status word)
Address + 5 not used Maximum Communication Time
setup)
Address + 7 3 = RTU Protocol
Address + 8 0 = Slave Port Mode
Address + 11 0 = Hardware, 1 = None Flow Control
Address + 12 not used Turnaround delay
Address + 13 not used Timeout
Address + 14 not used (RTU always chooses 8 bits by default) Bits per Character
Address + 15 not used (RTU always chooses 1 stop bit by default) Stop Bits
Address + 17 0 = 2-wire, 1 = 4-wire, 2 = 4-wire transmitter always on Duplex Mode
Address + 18 Station Address (1-247) Device Identifier
Address + 19 Count of 100 µs units (0 = 3.5 character times) End-of-frame timeout 54
Address + 20 not used
Address + 21 not used
Address + 22 Count of 10 ms units (range 0-255) Receive-to-transmit delay 54
54 The End-of-frame timeout and Receive-to-transmit delay values were added in Release 6.70 for the RX3i. They are
discussed in the RTU Slave Protocol section.

Example COMMREQ Data Block for Configuring Serial I/O Protocol

Values Meaning
Address 12 Data Block Length
Type
Address + 3 Zero-based number that gives the address of the COMMREQ Status Word Pointer Offset
status word (for example, a value of 99 gives an address of
100 for the status word)
Address + 5 not used Maximum Communication Time
setup)
Address + 7 5 = Serial I/O Protocol
Address + 8 not used Port Mode
Address + 11 0 = Hardware, 1 = None, 2 = Software Flow Control
Address + 12 not used Turnaround Delay
Address + 13 not used Timeout
Address + 14 0=7 bits, 1=8 bits Bits per Character
Address + 15 0 = 1 stop bit, 1 = 2 stop bits Stop Bits
Address + 17 0 = 2-wire, 1 = 4-wire, 2 = 4-wire transmitter always on Duplex Mode

6.2 Serial I/O Protocol

Serial I/O protocol is a communication protocol that is driven entirely by the application program.
Serial I/O protocol is active only when the CPU is in RUN Mode, since it is driven completely by
COMMREQ functions in the application program. Those COMMREQ functions are described in detail
within this section.
When the CPU is stopped, a port configured for Serial I/O protocol will revert to a STOP Mode protocol
as specified in the port settings of the CPU configuration. If a STOP Mode protocol was not specified,
RTU slave protocol is used by default.
6.2.1 Calling Serial I/O COMMREQs from the CPU Sweep
Implementing a serial protocol using Serial I/O COMMREQs may be restricted by the sweep time. For
example, if the protocol requires that a reply to a certain message from the remote device be
initiated within 5ms of receiving the message, this method may not be successful if the sweep time is
5ms or longer, since timely response is not guaranteed.
6.2.2 Compatibility
The COMMREQ function blocks supported by Serial I/O are not supported by other currently existing
protocols (such as SNP slave and RTU slave). Errors are returned if they are attempted for a port
configured for one of those protocols.
6.2.3 Status Word for Serial I/O COMMREQs
A value of 1 is returned in the COMMREQ status word upon successful completion of the COMMREQ.
Any other value returned is an error code where the low byte is a major error code and the high byte
is a minor error code.
Major Error Code Description
01 (01h) Successful Completion
(this is the expected completion value in the COMMREQ status word).
12 (0Ch) Local error —Error processing a local command.
The minor error code identifies the specific error.
02 (02h) COMMREQ command is not supported.
06 (06h) Invalid CPU memory type specified.
07 (07h) Invalid CPU memory offset specified.
08 (08h) Unable to access CPU memory.
12 (0Ch) COMMREQ data block length too small.
14 (0Eh) COMMREQ data is invalid.
15 (0Fh) Could not allocate system resources to complete COMMREQ.

Major Error Code Description

13 (0Dh) Remote error — Error processing a remote command. The minor error code identifies
the error.
2 (02h) Number of bytes requested to read is greater than input buffer size OR
number bytes requested to write is zero or greater than 250 bytes.
3 (03h) COMMREQ data block length is too small. String data is missing or
incomplete.
4 (04h) Receive timeout awaiting serial reception of data
6 (06h) Invalid CPU memory type specified.
7 (07h) Invalid CPU memory offset specified.
8 (08h) Unable to access CPU memory.
12 (0Ch) COMMREQ data block length too small.
16 (10h) Operating system service error. The operating system service used to
perform the request has returned an error.
17 (11h) Port device error. The port device used to perform the service has detected
an error. Either a break was received or a UART Error (parity, framing,
overrun) occurred.
18 (12h) Request cancelled. The request was terminated before it could complete.
48 (30h) Serial output timeout. The serial port was unable to transmit the string.
(Could be due to missing CTS signal when the serial port is configured to use
hardware flow control.)
14 (0Eh) Autodial Error — An error occurred while attempting to send a command string to an
attached external modem. The minor error code identifies the specific error.
2 (02h) The modem command string length exceeds end of reference memory type.
3 (03h) COMMREQ Data Block Length too small. Output command string data
missing or incomplete.
4 (04h) Serial output timeout. The serial port was unable to transmit the modem
autodial output.
5 (05h) Response was not received from modem. Check modem and cable.
6 (06h) Modem responded with BUSY. Modem is unable to complete the requested
connection. The remote modem is already in use; retry the connection
request later.
7 (07h) Modem responded with NO CARRIER. Modem is unable to complete the
requested connection. Check the local and remote modems and the
telephone line.
8 (08h) Modem responded with NO DIALTONE. Modem is unable to complete the
requested connection. Check the modem connections and the telephone
line.
9 (09h) Modem responded with ERROR. Modem is unable to complete the requested
command. Check the modem command string and modem.
10 (0Ah) Modem responded with RING, indicating that the modem is being called by
another modem. Modem is unable to complete the requested command.
Retry the modem command later.
11 (0Bh) Unknown response received from the modem. Modem unable to complete
the request. Check the modem command string and modem. Response
should be CONNECT or OK.

6.2.4 Serial I/O COMMREQ Commands

The following COMMREQs are used to implement Serial I/O:
■ Local COMMREQs - do not receive or transmit data through the serial port.
 Initialize Port (4300)
 Set Up Input Buffer (4301)
 Flush Input buffer (4302)
 Read port status (4303)
 Write port control (4304)
 Cancel Operation (4399)
■ Remote COMMREQs - receive and/or transmit data through the serial port.
 Autodial (4400)
 Write bytes (4401)
 Read bytes (4402)
 Read String (4403)

6.2.5 Overlapping COMMREQs

Some Serial I/O COMMREQs must complete execution before another COMMREQ can be processed.
Others can be left pending while others are executed.
6.2.5.1 COMMREQS that Must Complete Execution
■ Autodial (4400)
■ Initialize Port (4300)
■ Set Up Input Buffer (4301)
■ Flush Input buffer (4302)
■ Read port status (4303)
■ Write port control (4304)
■ Cancel Operation (4399)
■ Serial Port Setup (FFF0)
6.2.5.2 COMMREQs that can be Pending While Others Execute
The table below shows whether Write Bytes, Read Bytes and Read String COMMREQs can be pending
when other COMMREQs are executed.
NEW COMMREQ
Currently-Pending Autodial Write Initialize Set Up Flush Read Write Read Read Cancel Serial
COMMREQs (4400) Bytes Port Input Input Port Port Bytes String Operation Port
(4401) (4300) Buffer Buffer Status Control (4402) (4403) (4399) Setup
(4301) (4302) (4303) (4304 (FFF0)
Write Bytes (4401) No No Yes Yes Yes Yes Yes Yes Yes Yes No
Read Bytes (4402) No Yes Yes No No Yes Yes No No Yes No
Read String (4403) No Yes Yes No No Yes Yes No No Yes No

6.2.6 Initialize Port Function (4300)

This function causes a reset command to be sent to the specified port. It also cancels any COMMREQ
currently in progress and flushes the internal input buffer. RTS and DTR are set to inactive.
Example Command Block for the Initialize Port Function
Value Value Meaning
(decimal) (hexadecimal)
Address 0001 0001 Data block length
Address +1 0000 0000 NOWAIT mode
Address +2 0008 0008 Status word memory type (%R)
Address +3 0000 0000 Status word address minus 1 (%R0001)
Address +4 0000 0000 Not used
Address +6 4300 10CC Initialize port command
6.2.6.2 Operating Notes

Remote COMMREQs that are cancelled due to this command executing will return a COMMREQ
status word indicating request cancellation (minor code 12H).
Caution
If this COMMREQ is sent when a Write Bytes (4401) COMMREQ
is transmitting a string from a serial port, transmission is
halted. The position within the string where the transmission is
halted is indeterminate. In addition, the final character
received by the device to which the CPU is sending is also
indeterminate.

6.2.7 Set Up Input Buffer Function (4301)

This function is provided for compatibility with legacy Serial I/O applications. In PACSystems releases
5.70 and later, the internal input buffer is always set to 2097 bytes. In earlier PACSystems
implementations, the internal input buffer is set to 2K bytes.
The Set Up Input Buffer function returns a success status to the COMMREQ status word, regardless of
the buffer length specified in the command block.
As data is received from the serial port it is placed in the input buffer. If the buffer becomes full, any
additional data received from the serial port is discarded and the Overflow Error bit in the Port Status
word (See Read Port Status Function) is set.
6.2.7.1 Retrieving Data from the Buffer
Data can be retrieved from the buffer using the Read String or Read Bytes function. It is not directly
accessible from the application program.
If data is not retrieved from the buffer in a timely fashion, some characters may be lost.
Example Command Block for the Set Up Input Buffer Function
VALUE VALUE
(decimal) (hexadecimal) MEANING
Address +6 4301 10CD Setup input buffer command
Address +7 0064 0040 Buffer length (in words)

6.2.8 Flush Input Buffer Function (4302)

This operation empties the input buffer of any characters received through the serial port but not yet
retrieved using a read command. All such characters are lost.
Example Command Block for the Flush Input Buffer Function
VALUE VALUE MEANING
Address +6 4302 10CE Flush input buffer command

6.2.9 Read Port Status Function (4303)

This function returns the current status of the port. The following events can be detected:
1. A read request was initiated previously and the required number of characters has now been
received or the specified time-out has elapsed.
2. A write request was initiated previously and transmission of the specified number of characters is
complete or a time-out has elapsed.
The status returned by the function indicates the event or events that have completed. More than
one condition can occur simultaneously, if both a read and a write were initiated previously.
Example Command Block for the Read Port Status Function
VALUE VALUE MEANING
Address +6 4303 10CF Read port status command
Address +7 0076 004C Port status memory type (%M)
Address +8 0101 0065 Port status memory offset (%M101)
6.2.9.2 Port Status

The port status consists of a status word and the number of characters in the input buffer that have
not been retrieved by the application (characters which have been received and are available).
word 1 Port status word (see below)
word 2 Characters available in the input buffer

Port Status Word Meanings

Bit Name Definition Status Meaning
Read In Set Read Bytes or Read String invoked
15 RP
progress Cleared Previous Read bytes or String has timed out, been canceled, or finished
Read Set Read Bytes or Read String has successfully completed
14 RS
Success Cleared New Read Bytes or Read String invoked
Read Set Receive timeout occurred during Read Bytes or Read String
13 RT
Time-out Cleared New Read Bytes or Read String invoked
Set New Write Bytes invoked
Write In
12 WP Previously-invoked Write Bytes has timed out, been canceled, or
progress Cleared
finished
Write Set Previously-invoked Write Bytes has successfully completed
11 WS
Success Cleared New Write Bytes invoked
Write Set Transmit timeout occurred during Write Bytes
10 WT
Time-out Cleared New Write Bytes invoked
Character Set Unread characters are in the buffer
9 CA
Available Cleared No unread characters in the buffer
Overflow Set Overflow error occurred on the serial port or internal buffer
8 OF
error Cleared Read Port Status invoked
Framing Set Framing error occurred on the serial port
7 FE
Error Cleared Read Port Status invoked
Parity Set Parity error occurred on the serial port
6 PE
Error Cleared Read Port Status invoked
Clear to Set Clear to Send signal is active
5 CTS
Send Cleared Clear to Send signal is not active
Data Set Set Data Set Ready signal is active
4 DSR
Ready Cleared Data Set Ready signal is not active
Ring Set Ring Indicator signal is active
3 RI
Indicator Cleared Ring Indicator signal is not active
Data Set Data Carrier Detect signal is active
2 DCD Carrier Data Carrier Detect signal is not active
Detect Cleared
1-0 n/a Not used These bits are always set to 0

For reference, see the tables under Serial Port Pin Assignments in Chapter 5.
Support for the DSR status bit is provided for COM1 only, on all RX7i and RX3i models (except CPE305),
in Rel. 7.16 and later releases.
Support for the RP and DCD status bits is provided only for COM1 on the CPE310, in Rel. 7.16 and later
releases.

6.2.10 Write Port Control Function (4304)

This function controls output signals on the specified port:
Example Command Block for the Write Port Control Function
VALUE VALUE MEANING
Address +6 4304 10D0 Write port control command
Address +7 xxxx xxxx Port control word
6.2.10.2 Port Control Word

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTS DTR -- -- -- -- -- -- -- -- -- -- -- -- -- --
Port Control Word Meanings:

Commanded state of Request to Send signal
15 RTS 1 = Activates RTS
0 = Deactivates RTS
Commanded state of Data Terminal Ready signal
14 DTR 1 = Activates DTR
0 = Deactivates DTR
13-0 n/a Unused (should be zero)
For reference, see the tables under Serial Port Pin Assignments in Chapter 5.
Support for the DTR output signal is provided for COM1 only, on all RX7i and RX3i models (except
CPE305 and CPE330), in Rel 7.16 and later releases.
For CPU COM2 (RS-485), the RTS signal is also controlled by the transmit driver. Therefore, control of
RTS is dependent on the current state of the transmit driver. If the transmit driver is not enabled,
asserting RTS with the Write Port Control COMMREQ will not cause RTS to be asserted on the serial
line. The state of the transmit driver is controlled by the protocol and is dependent on the current
Duplex Mode of the port. For 2-wire and 4-wire Duplex Mode, the transmit driver is only enabled
during transmitting. Therefore, RTS on the serial line will only be seen active on COM2 (configured for
2-wire or 4-wire Duplex Mode) when data is being transmitted. For point-to-point Duplex Mode, the
transmit driver is always enabled. Therefore, in point-to-point Duplex Mode, RTS on the serial line will
always reflect what is chosen with the Write Port Control COMMREQ.

6.2.11 Cancel COMMREQ Function (4399)

This function cancels the current operations in progress. It can be used to cancel both read
operations and write operations.
If a read operation is in progress and there are unprocessed characters in the input buffer, those
characters are left in the input buffer and available for future reads. The serial port is not reset.
Example Command Block for the Cancel Operation Function
Value Value Meaning
Address 0002 0002 Data block length (2)
Address +6 4399 112F Cancel operation command
Address +7 0001 0001 Transaction type to cancel
1 - All operations
2 - Read operations
3 - Write operations

Remote COMMREQs that are cancelled due to this command executing will return a COMMREQ
status word indicating request cancellation (minor code 12H).
Caution
If this COMMREQ is sent in either Cancel All or Cancel Write
mode when a Write Bytes (4401) COMMREQ is transmitting a
string from a serial port, transmission is halted. The position
within the string where the transmission is halted is
indeterminate. In addition, the final character received by
the device to which the CPU is sending is also indeterminate.

6.2.12 Autodial Function (4400)

This feature allows the CPU to automatically dial a modem and send a specified byte string.
To implement this feature, the port must be configured for Serial I/O. After the autodial function is
executed and the modem has established a connection, other serial I/O functions (Write bytes, Set
Up Input Buffer, Flush Input buffer, Read port status, Write port control, Read bytes, Read String, and
Cancel Operation) can be used.
Example
Pager enunciation can be implemented by three commands, requiring three COMMREQ command
blocks:
Autodial: Dials the modem.
04400 (1130h)
Write Bytes: Specifies an ASCII string, from 1 to 250 bytes in length, to send from the serial port.
04401 (1131h)
Autodial: It is the responsibility of the application program to hang up the phone
04400 (1130h) connection. This is accomplished by reissuing the autodial command and sending
the hang up command string.
6.2.12.2 Autodial Command Block

The Autodial command automatically transmits an Escape sequence that follows the Hayes
convention. If you are using a modem that does not support the Hayes convention, you may be able
to use the Write Bytes command to dial the modem.
Examples of commonly used command strings for Hayes-compatible modems are listed below:
Command String Length Function
ATDP15035559999<CR> 16 (10h) Pulse dial the number 1-503-555-9999
ATDT15035559999<CR> 16 (10h) Tone dial the number 1-503-555-9999
ATDT9,15035559999<CR> 18 (12h) Tone dial using outside line with pause
ATH0<CR> 5 (05h) Hang up the phone
ATZ <CR> 4 (04h) Restore modem configuration to internally saved values

Sample Autodial Command Block

This COMMREQ command block dials the number 234-5678 using a Hayes-compatible modem.
Word Definition Values
1 0009h CUSTOM data block length (includes command string)
2 0000h NOWAIT mode
3 0008h Status word memory type (%R)
4 0000h Status word address minus 1 (Register 1)
5 0000h not used
6 0000h not used
7 04400 (1130h) Autodial command number
8 00030 (001Eh) Modem response timeout (30 seconds)
9 0012 (000Ch) Number of bytes in command string
10 5441h A (41h), T (54h)
11 5444h D (44h), T (54h)
12 3332h Phone number: 2 (32h), 3 (33h)
13 3534h 4 (34h), 5 (35h)
14 3736h 6 (36h), 7 (37h)
15 0D38h 8 (38h) <CR> (0Dh)

6.2.13 Write Bytes Function (4401)

This operation can be used to transmit one or more characters to the remote device through the
specified serial port. The character(s) to be transmitted must be in a word reference memory. They
should not be changed until the operation is complete.
Up to 250 characters can be transmitted with a single invocation of this operation. The status of the
operation is not complete until all the characters have been transmitted or until a timeout occurs (for
example, if hardware flow control is being used and the remote device never enables the
transmission).
Example Command Block for the Write Bytes Function
Value Value Meaning
Address 0006 0006 Data block length (includes characters to send)
Address +6 4401 1131 Write bytes command
Address +7 0030 001E Transmit time-out (30 seconds). See note below.
Address +8 0005 0005 Number of bytes to write
Address +9 25960 6568 ‘h’ (68h), ‘e’ (65h)
Address +10 27756 6C6C ‘l’ (6Ch), ‘l’ (6Ch)
Address +11 0111 006F ‘o’ (6Fh)
Although printable ASCII characters are used in this example, there is no restriction on the values of
the characters that can be transmitted.
Specifying zero as the Transmit time-out sets the time-out value to the amount of time actually
needed to transmit the data, plus 4 seconds.
Caution
If an Initialize Port (4300) COMMEQ is sent or a Cancel
Operation (4399) COMMREQ is sent in either Cancel All or
Cancel Write mode while this COMMREQ is transmitting a
string from a serial port, transmission is halted. The position
within the string where the transmission is halted is
indeterminate. In addition, the final character received by
the device the CPU is sending to is also indeterminate.

6.2.14 Read Bytes Function (4402)

This function causes one or more characters to be read from the specified port. The characters are
read from the internal input buffer and placed in the specified input data area. The function returns
both the number of characters retrieved and the number of unprocessed characters still in the input
buffer. If zero characters of input are requested, only the number of unprocessed characters in the
input buffer is returned.
If insufficient characters are available to satisfy the request and a non-zero value is specified for the
number of characters to read, the status of the operation is not complete until either sufficient
characters have been received or the time-out interval expires. In either of those conditions, the port
status indicates the reason for completion of the read operation. The status word is not updated until
the read operation is complete (either due to timeout or when all the data has been received).
If the time-out interval is set to zero, the COMMREQ remains pending until it has received the
requested amount of data, or until it is cancelled.
If this COMMREQ fails for any reason, no data is returned to the input data area. Any data that has
not been read from the internal input buffer remains and it can be retrieved with a subsequent read
request.
Example Command Block for the Read Bytes Function
Value Value Meaning
Address +6 4402 1132 Read bytes command
Address +7 0030 001E Read time-out (30 seconds)
Address +8 0005 0005 Number of bytes to read
Address +9 0008 0008 Input data memory type (%R).
Address +10 0100 0064 Input data memory address (%R0100)

6.2.14.2 Return Data Format for the Read Bytes Function

The return data consists of the number of characters actually read, the number of characters still
available in the input buffer after the read is complete (if any), and the actual input characters.
Address Number of characters actually read
Address + 1 Number of characters still available in the input buffer, if any
Address + 2 first two characters (first character is in the low byte)
Address + 3 third and fourth characters (third character is in the low byte)
Address + n subsequent characters
6.2.14.3 Operating Notes for Read Bytes

If the input data memory type parameter is specified to be a word memory type, and if an odd
number of bytes is actually received, then the high byte of the last word to be written with the
received data is left unchanged.
As data is received from the serial port it is placed in the internal input buffer. If the buffer becomes
full, then any additional data received from the serial port is discarded and the Overflow Error bit in
the Port Status word (See Read Port Status Function) is set.

6.2.15 Read String Function (4403)

This function causes characters to be read from the specified port until a specified terminating
character is received. The characters are read from the internal input buffer and placed in the
specified input data area.
The function returns both the number of characters retrieved and the number of unprocessed
characters still in the input buffer. If zero characters of input are requested, only the number of
unprocessed characters in the input buffer is returned.
If the terminating character is not in the input buffer, the status of the operation is not complete until
either the terminating character has been received or the time-out interval expires. In either of those
conditions, the port status indicates the reason for completion of the read operation.
If the time-out interval is set to zero, the COMMREQ remains pending until it has received the
requested string, terminated by the specified end character.
If this COMMREQ fails for any reason, no data is returned to the input data area. Any data that has
not been read from the internal input buffer remains, and it can be retrieved with a subsequent read
request.
Example Command Block for the Read String Function
Value Value
Meaning
Address +6 4403 1133 Read string command
Address +7 0030 001E Read time-out (30 seconds)
Terminating character (carriage return): must be
Address +8 0013 000D
between 0 and 255 (0xFF), inclusive
Address +9 0008 0008 Input data memory type (%R)
Address +10 0100 0064 Input data memory address (%R0100)

6.2.15.2 Return Data Format for the Read String Function

The return data consists of the number of characters actually read, the number of characters still
available in the input buffer after the read is complete (if any), and the actual input characters:
Address Number of characters actually read
Address + 1 Number of characters still available in the input buffer, if any
Address + 2 first two characters (first character is in the low byte)
Address + 3 third and fourth characters (third character is in the low byte)
Address + n subsequent characters
6.2.15.3 Operating Notes for Read String

If the input data memory type parameter is specified to be a word memory type, and if an odd
number of bytes is actually received, then the high byte of the last word to be written with the
received data is left unchanged.
As data is received from the serial port it is placed in the internal input buffer. If the buffer becomes
full, then any additional data received from the serial port is discarded and the Overflow Error bit in
the Port Status word (See Read Port Status Function) is set.

6.3 RTU Slave Protocol

RTU protocol is a query-response protocol used for communication between the RTU device and a
host computer, which is capable of communicating using RTU protocol. The host computer is the
master device and it transmits a query to a RTU slave, which responds to the master. The RTU slave
device cannot query; it can only respond to the master. A PACSystems CPU can only function as an
RTU slave.
The RTU data transferred consists of 8-bit binary characters with an optional parity bit. No control
characters are added to the data block; however, an error check (Cyclic Redundancy Check) is
included as the final field of each query and response to ensure accurate transmission of data.
Note: You should avoid using station address 1 for any other Modbus slave in a PACSystems control
system because the default station address for the PACSystems CPU is 1. The CPU uses the
default address in two situations:
1. If you power up without a configuration, the default station address of 1 is used.
2. When the Port Mode parameter is set to Message Mode, and Modbus becomes the
protocol in STOP Mode, the station address defaults to 1, unless you specify a STOP Mode
for the serial port in the CPU configuration, and then change the station address to be
used for STOP Mode.
In either of these situations, if you have a slave configured with a station address of 1,
confusion may result when the PACSystems CPU responds to requests intended for that
slave.

6.3.1 Message Format

The general formats for RTU message transfers are shown below:
6.3.1.1 RTU Message Transfers
Slave Turn-around Time
Master Query Message
Slave Response
Query Transaction
Master Broadcast Message
Slave (No Response)
Broadcast Transaction
Figure 36: RTU Message Transactions
The master device begins a data transfer by sending a query or broadcast request message. A slave
completes that data transfer by sending a response message if the master sent a query message
addressed to it. No response message is sent when the master sends a broadcast request.
6.3.1.2 RTU Slave Turnaround Time
The time between the end of a query and the beginning of the response to that query is called the
slave turnaround time. The turnaround time of a PACSystems slave depends on the Controller
Communications Window time and the sweep time of the PACSystems. RTU requests are processed
only in the Controller Communications Window. In Normal sweep mode, the Controller
Communications Window occurs once per sweep. Because the sweep time on PACSystems can be
up to 2.5 seconds, the time to process an RTU request could be up to 2.5 seconds. Another factor is
the Controller Communications Window time allowed in Hardware Configuration. If you configure a
very small Controller Communications Window, the RTU request may not be completed in one sweep,
causing RTU processing to require multiple sweeps. For details on CPU window modes, refer to
Window Modes in Chapter 4.
6.3.1.3 Receive-to-Transmit Delay
Part of the RTU Slave Turnaround time is the receive-to-transmit delay. The RTU driver inserts this
delay after a request from the master has been received, and before the response to the master is
sent. Starting with Release 6.70 for the RX3i, the receive-to-transmit delay can be configured with the
Serial Port Setup COMMREQ function 65520. The timeout is specified in units of 10 ms, with a range of
0–255 units (maximum delay is 2.55 seconds). If the specified time is less than 3.5 character times,
then the delay is set to 3.5 character times.

6.3.1.4 Message Types

The RTU protocol has four message types: query, normal response, error response, and broadcast.
Query
The master sends a message addressed to a single slave.
Normal Response
After the slave performs the function requested by the query, it sends back a normal response for
that function. This indicates that the request was successful.
Error Response
The slave receives the query, but cannot perform the requested function. The slave sends back an
error response that indicates the reason the request could not be processed. (No error message will
be sent for certain types of errors. For more information, refer to Communication Errors below.)
Broadcast
The master sends a message addressed to all the slaves by using address 0. All slaves that receive
the broadcast message perform the requested function. This transaction is ended by a time-out
within the master.

6.3.1.5 Message Fields

The message fields for a typical message are shown in the figure below, and are explained in the
following sections.
FRAME
Station Address Function Code Information Error Check
Station Address
The Station Address is the address of the slave station selected for this data transfer. It is one byte in
length and has a value from 0 to 247 inclusive. An address of 0 selects all slave stations, and
indicates that this is a broadcast message. An address from 1 to 247 selects a slave station with that
station address.
Function Code
The Function Code identifies the command being issued to the station. It is one byte in length and is
defined for the values 0 to 255 as follows:
Function Code Description
0 Illegal Function
1 Read Output Table
2 Read Input Table
3 Read Registers
4 Read Analog Input
5 Force Single Output
6 Preset Single Register
7 Read Exception Status
8 Loopback Maintenance
9-14 Unsupported Function
15 Force Multiple Outputs
16 Preset Multiple Registers
17 Report Device Type
18–21 Unsupported Function
22 Mask Write 4x Register
23 Read/Write 4x Registers
24–66 Unsupported Function
67 Read Scratch Pad Memory
68-127 Unsupported Function
128-255 Reserved for Exception Responses

Information Fields
All message fields, other than the Station Address field, Function Code field, and Error Check field are
called, generically, information fields. Information fields contain additional information required to
specify or respond to a requested function. Different types of messages have different types or
numbers of information fields. (Details on information fields for each message type and function code
are found in RTU Message Descriptions. Some messages (Message 07 Query and Message 17 Query)
do not have information fields.
Examples
As shown in the following figure, the information fields for message READ OUTPUT TABLE (01) Query
consist of the Starting Point No. field and Number of Points field. The information fields for message
READ OUTPUT TABLE (01) Response consist of the Byte Count field and Data field.
Message (01)
Read Output Table
Information Fields
Address Func Starting Number of Error

01 Point No. Points Check
Hi Lo Hi Lo
Query
Information Fields
Address Func Byte Data Error

01 Count Check
Normal Response
Figure 37: RTU Read Output Table Example
Some information fields include entries for the range of data to be accessed in the RTU slave.
Note: Data addresses are 0-based. This means you will need to subtract 1 from the actual address
when specifying it in the RTU message. For message (01) READ OUTPUT TABLE Query, used in
the example above, you would specify a starting data address in the Starting Point No. field.
To specify %Q0001 as the starting address, you would place the address %Q0000 in this field.
Also, the value placed in the Number of Points field determines how many %Q bits are read,
starting with address %Q0001. For example:
 Starting Point No. field = %Q0007, so the starting address is %Q0008.
 Number of Points field = 16 (0010h), so addresses %Q0008 through %Q0023 will be read.
Error Check Field
The Error Check field is two bytes in length and contains a cyclic redundancy check (CRC-16) code. Its
value is a function of the contents of the station Address, Function code, and Information field. The
details of generating the CRC-16 code are described in Cyclic Redundancy Check (CRC). Note that the
Information field is variable in length. To properly generate the CRC-16 code, the length of frame
must be determined. To calculate the length of a frame for each of the defined function codes, see
Calculating the Length of Frame.

Message Length
Message length varies with the type of message and amount of data to be sent. Information for
determining message length for individual messages is found in RTU Message Descriptions.
Character Format
A message is sent as a series of characters. Each byte in a message is transmitted as a character.
The illustration below shows the character format. A character consists of a start bit (0), eight data
bits, an optional parity bit, and one stop bit (1). Between characters the line is held in the 1 state.
MSB Data Bits LSB
10 9 8 7 6 5 4 3 2 1 0
Parity
Stop Start
(optional)
Message Termination
Each station monitors the time between characters. When a period of three character times elapses
without the reception of a character, the end of a message is assumed. The reception of the next
character is assumed to be the beginning of a new message. The end of a frame occurs when the
first of the following two events occurs:
1) The number of characters received for the frame is equal to the calculated length of the frame.
2) A length of 4 character times elapses without the reception of a character.
Timeout Usage
Timeouts are used on the serial link for error detection, error recovery, and to prevent the missing of
the end of messages and message sequences. Note that although the module allows up to three
character transmission times between each character in a message that it receives, there is no more
than half a character time between each character in a message that the module transmits. After
sending a query message, the master should wait an appropriate amount of time for slave
turnaround before assuming that the slave did not respond to the request. Slave turnaround time is
affected by the Controller Communications Window time and the CPU sweep time, as described in
RTU Slave Turnaround Time.
End-of-Frame Timeout
The End-of-frame timeout is a feature that compensates for message gaps that can occur due to the
use of radio modems. The timeout is added to the amount of time allowed for receiving a message
from the master. The timeout should be sized according to the maximum gap time that could be
introduced by the master’s transmitting equipment. Starting with Release 6.70 for the RX3i, the end-
of-frame timeout can be configured with the Serial Port Setup COMMREQ function 65520. The
timeout is specified in units of 100 µs. If the specified time is less than 3.5 character times, then the
RTU driver sets the timeout to 3.5 character times.

6.3.2 Cyclic Redundancy Check (CRC)

The CRC is one of the most effective systems for checking errors. The CRC consists of two check
characters generated at the transmitter and added at the end of the transmitted data characters.
Using the same method, the receiver generates its own CRC for the incoming data and compares it
to the CRC sent by the transmitter to ensure proper transmission. A complete mathematic derivation
for the CRC is not given in this section. This information can be found in a number of texts on data
communications. The essential steps that should be understood in calculating the CRC are as follows:
■ The number of bits in the CRC multiplies the data bits that make up the message.
■ The resulting product is then divided by the generating polynomial (using modulo 2 with no
carries). The CRC is the remainder of this division.
■ Disregard the quotient and add the remainder (CRC) to the data bits and transmit the message
with CRC.
■ The receiver then divides the message plus CRC by the generating polynomial and if the
remainder is 0, the transmission was transmitted without error.
A generating polynomial is expressed algebraically as a string of terms in powers of X such as
X3 + X2 + X0 (or 1)
which, in turn, can be expressed as the binary number 1101.
A generating polynomial could be any length and contain any pattern of 1s and 0s as long as both
the transmitter and receiver use the same value. For optimum error detection, however, certain
standard generating polynomials have been developed. RTU protocol uses the polynomial
X16 + X15 + X2 + 1
which in binary is 1 1000 0000 0000 0101. The CRC this polynomial generates is known as CRC-16.
The discussion above can be implemented in hardware or software. One hardware implementation
involves constructing a multi-section shift register based on the generating polynomial.
6.3.2.1 Cyclic Redundancy Check Register
2 15 16
X X X
CRC Register
15 14 + 13 12 11 10 9 8 7 6 5 4 3 2 1 + 0 +
Data
+ = Exclusive Or
Input
Figure 38: CRC Register Operation

To generate the CRC, the message data bits are fed to the shift register one at a time. The CRC
register contains a preset value. As each data bit is presented to the shift register, the bits are shifted
to the right. The LSB is XORed with the data bit and the result is: XORed with the old contents of bit 1
(the result placed in bit 0), XORed with the old contents of bit 14 (and the result placed in bit 13), and
finally, it is shifted into bit 15. This process is repeated until all data bits in a message have been
processed. Software implementation of the CRC-16 is explained in the section below.

6.3.2.2 Calculating the CRC-16

The pseudo code for calculation of the CRC-16 is given below.
Preset byte count for data to be sent.
Initialize the 16-bit remainder (CRC) register to all ones.
XOR the first 8-bit data byte with the high order byte of the 16-bit CRC register. The
result is the current CRC.
INIT SHIFT: Initialize the shift counter to 0.
SHIFT: Shift the current CRC register 1 bit to the right.
Increment shift count.
Is the bit shifted out to the right (flag) a 1 or a 0?
If it is a 1, XOR the generating polynomial with the current CRC.
If it is a 0, continue.
Is shift counter equal to 8?
If NO, return to SHIFT.
If YES, increment byte count.
Is byte count greater than the data length?
If NO, XOR the next 8-bit data byte with the current CRC and go to INIT SHIFT.
If YES, add current CRC to end of data message for transmission and exit.
When the message is transmitted, the receiver performs the same CRC operation on all the data bits
and the transmitted CRC. If the information is received correctly the resulting remainder (receiver
CRC) is 0.
Sample CRC-16 Calculation
The RTU device transmits the rightmost byte (of registers or discrete data) first. The first bit of the
CRC-16 transmitted is the MSB. Therefore, in the example the MSB of the CRC polynomial is to the
extreme right. The X16 term is dropped because it affects only the quotient (which is discarded) and
not the remainder (the CRC characters). The generating polynomial is therefore 1010 0000 0000
0001. The remainder is initialized to all 1s.
In this example, the CRC-16 is calculated for RTU message, Read Exception Status 07. The message
format is as follows:
Address Function CRC-16
01 07
In this example, device number 1 (address 01) is queried. You need to know the amount of data to be
transmitted and this information can be found for every message type in Calculating the Length of
Frame. For this message the data length is 2 bytes.

Transmitter CRC-16 Algorithm Receiver55 CRC-16 Algorithm

MSB56 LSB56 Flag MSB56 LSB56 Flag
Initial Remainder 1111 1111 1111 1111 Rcvr CRC after data 1110 0010 0100 0001
XOR 1st data byte 0000 0000 0000 0001 XOR 1st byte Trns CRC 0000 0000 0100 0001
Current CRC 1111 1111 1111 1111 Current CRC 1110 0010 0000 0000
Shift 1 0111 1111 1111 1111 0 Shift 1 0111 0001 0000 0000 0
Shift 2 0011 1111 1111 1111 1 Shift 2 0011 1000 1000 0000 0
XOR Gen. 1010 0000 0000 0001 Shift 3 0001 1100 0100 0000 0
Polynomial
Current CRC 1001 1111 1111 1110 Shift 4 0000 1110 0010 0000 0
Shift 3 0100 1111 1111 1111 0 Shift 5 0000 0111 0001 0000 0
Shift 4 0010 0111 1111 1111 1 Shift 6 0000 0011 1000 1000 0
XOR Gen. 1010 0000 0000 0001 Shift 7 0000 0001 1100 0100 0
Polynomial
Current CRC 1000 0111 1111 1110 Shift 8 0000 0000 1110 0010 0
Shift 5 0100 0011 1111 1111 0 XOR 2nd byte Trns CRC 0000 0000 1110 0010
Shift 6 0010 0001 1111 1111 1 Current CRC 0000 0000 0000 0000
XOR Gen. 1010 0000 0000 0001 Shift 1-8 yields 0000 0000 0000 0000
Polynomial
Current CRC 1000 0001 1111 1110 All errors for receiver final CRC-16 indicates transmission correct.
Shift 7 0100 0000 1111 1111 0
Shift 8 0010 0000 0111 1111 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Current CRC 1000 0000 0111 1110
XOR 2nd data byte 0000 0000 0000 0111
Current CRC 1000 0000 0111 1001
Shift 1 0100 0000 0011 1100 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Current CRC 1110 0000 0011 1101
Shift 2 0111 0000 0001 1110 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Current CRC 1101 0000 0001 1111
Shift 3 0110 1000 0000 1111 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Current CRC 1100 1000 0000 1110
Shift 4 0110 0100 0000 0111 0
Shift 5 0011 0010 0000 0011 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Current CRC 1001 0010 0000 0010
Shift 6 0100 1001 0000 0001 0
Shift 7 0010 0100 1000 0000 1
55 The receiver processes incoming data through the same CRC algorithm as the transmitter. The example for the receiver
starts at the point after all the data bits but not the transmitted CRC have been received correctly. Therefore, the receiver
CRC should be equal to the transmitted CRC at this point. When this occurs, the output of the CRC algorithm will be zero
indicating that the transmission is correct.
The transmitted message with CRC would then be:
Address Function CRC–16
01 07 41 E2
56 The MSB and LSB references are to the data bytes only, not to the CRC bytes. The CRC MSB and LSB order are the reverse
of the data byte order.

XOR Gen. 1010 0000 0000 0001

Polynomial
Current CRC 1000 0100 1000 0001
Shift 8 0100 0010 0100 0000 1
XOR Gen. 1010 0000 0000 0001
Polynomial
Transmitted CRC 1110 0010 0100 0001
E 2 4 1
6.3.2.3 Calculating the Length of Frame

To generate the CRC-16 for any message, the message length must be known. The length for all
types of messages can be determined from the table below.
6.3.2.4 RTU Message Length
Functio Name Query or Broadcast Message Response Message Length
n Code Length Less CRC Code Less CRC Code
0 Not Defined Not Defined
1 Read Output Table 6 3 + 3rd byte57
2 Read Input Table 6 3 + 3rd byte57
3 Read Registers 6 3 + 3rd byte57
4 Read Analog Input 6 3 + 3rd byte57
5 Force Single Output 6 6
6 Preset Single Register 6 6
7 Read Exception Status 2 3
8 Loopback/Maintenance 6 6
9-14 Not Defined Not Defined
15 Force Multiple Outputs 7 + 7th byte57 6
16 Preset Multiple Registers 7 + 7th byte57 6
17 Report Device Type 2 8
22 Mask Write 4x Registers 8 8
23 Read/Write 4x Registers 13+byte 1157 5+byte 357
24–66 Not Defined Not Defined
67 Read Scratch Pad 6 3 + 3rd byte57
128-255 Not Defined 3
57 The value of this byte is the number of bytes contained in the data being transmitted.

6.3.3 RTU Message Descriptions

This section presents the format and fields for each RTU message.
6.3.3.1 Message (01): Read Output Table
Format:

Hi Lo Hi Lo
Query

01 Count Check
Normal Response
Figure 39: RTU Read Output Table Message Format
Query:
 An address of 0 is not allowed because this cannot be a broadcast request.
 The function code is 01.
 The starting point number is two bytes in length and may be any value less than the highest
output point number available in the attached CPU. The starting point number is equal to one
less than the number of the first output point returned in the normal response to this request.
 The number of points value is two bytes in length. It specifies the number of output points
returned in the normal response. The sum of the starting point value and the number of points
value must be less than or equal to the highest output point number available in the attached
CPU. The high order byte of the Starting Point Number and Number of Points fields is sent as the
first byte. The low order byte is the second byte in each of these fields.
Response:
 The byte count is a binary number from 1 to 256 (0 = 256). It is the number of bytes in the normal
response following the byte count and preceding the error check.
 The Data field of the normal response is packed output status data. Each byte contains eight
output point values. The least significant bit (LSB) of the first byte contains the value of the output
point whose number is equal to the starting point number plus one. The values of the output
points are ordered by number starting with the LSB of the first byte of the Data field and ending
with the most significant bit (MSB) of the last byte of the Data field. If the number of points is not a
multiple of 8, the last data byte contains zeroes in one to seven of its highest order bits.

6.3.3.2 Message (02): Read Input Table

Format:

Hi Lo Hi Lo
Query

02 Count Check
Normal Response
Figure 40: RTU Read Input Table Message Format
Query:
 An address of 0 is not allowed as this cannot be a broadcast request.
 The function code is 02.
 The starting point number is two bytes in length and may be any value less than the highest
input point number available in the attached CPU. The starting point number is equal to one less
than the number of the first input point returned in the normal response to this request.
 The number of points value is two bytes in length. It specifies the number of input points returned
in the normal response. The sum of the starting point value and the number of points value must
be less than or equal to the highest input point number available in the attached CPU. The high
order byte of the Starting Point Number and Number Of Bytes fields is sent as the first byte. The
low order byte is the second byte in each of these fields.
Response:
 The byte count is a binary number from 1 to 256 (0 = 256). It is the number of bytes in the normal
response following the byte count and preceding the error check.
 The Data field of the normal response is packed input status data. Each byte contains eight input
point values. The least significant bit (LSB) of the first byte contains the value of the input point
whose number is equal to the starting point number plus one. The values of the input points are
ordered by number starting with the LSB of the first byte of the Data field and ending with the
most significant bit (MSB) of the last byte of the Data field. If the number of points is not a multiple
of 8, then the last data byte contains zeroes in one to seven of its highest order bits.

6.3.3.3 Message (03): Read Registers

Format:
03 Register No. Registers Check
s
Hi Lo Hi Lo
Query

03 Count Check
First Register
Hi Lo Hi Lo
Normal Response
Figure 41: RTU Read Registers Message Format
Query:
 An address of 0 is not allowed as this request cannot be a broadcast request.
 The function code is equal to 3.
 The starting register number is two bytes in length. The starting register number may be any
value less than the highest register number available in the attached CPU. It is equal to one less
than the number of the first register returned in the normal response to this request.
 The number of registers value is two bytes in length. It must contain a value from 1 to 125
inclusive. The sum of the starting register value and the number of registers value must be less
than or equal to the highest register number available in the attached CPU. The high order byte
of the Starting Register Number and Number of Registers fields is sent as the first byte in each of
these fields. The low order byte is the second byte in each of these fields.
Response:
 The byte count is a binary number from 2 to 250 inclusive. It is the number of bytes in the normal
response following the byte count and preceding the error check. Note that the byte count is
equal to two times the number of registers returned in the response. A maximum of 250 bytes
(125) registers is set so that the entire response can fit into one 256-byte data block.
 The registers are returned in the Data field in order of number with the lowest number register in
the first two bytes and the highest number register in the last two bytes of the Data field. The
number of the first register in the Data field is equal to the Starting Register Number plus one.
The high order byte is sent before the low order byte of each register.

6.3.3.4 Message (04): Read Analog Inputs

Format:
04 Analog Input Analog Check
No. No. Inputs
Hi Lo Hi Lo
Query
Address Func Byte First Data Error

04 Count Analog Check
Input
Hi Lo Hi Lo
Normal Response
Figure 42: RTU Read Analog Inputs Message Format
Query:
 An Address of 0 is not allowed as this request cannot be a broadcast request.
 The Starting Analog Input Number is two bytes in length. The Starting Analog Input Number may
be any value less than the highest analog input number available in the attached CPU. It is equal
to one less than the number of the first analog input returned in the normal response to this
request.
 The Number Of Analog Inputs value is two bytes in length. It must contain a value from 1 to 125
inclusive. The sum of the Starting Analog Input value and the Number Of Analog Inputs value
must be less than or equal to the highest analog input number available in the at-attached CPU.
The high order byte of the Starting Analog Input Number and Number of Analog Inputs fields is
sent as the first byte in each of these fields. The low order byte is the second byte in each of these
fields.
Response:
 The Byte Count is a binary number from 2 to 250 inclusive. It is the number of bytes in the normal
response following the byte count and preceding the error check. Note that the Byte Count is
equal to two times the number of analog inputs returned in the response. A maximum of 250
bytes (125) analog inputs is set so that the entire response can fit into one 256-byte data block.
 The analog inputs are returned in the Data field in order of number with the lowest number
analog input in the first two bytes and the highest number analog input in the last two bytes of
the Data field. The number of the First Analog Input in the Data field is equal to the Starting
analog input number plus one. The high order byte is sent before the low order byte of each
analog input.

6.3.3.5 Message (05): Force Single Output

Format:
Address Func Point Data Error Check
05 Number
00H
Hi Lo Hi Lo
Query
Address Func Point Data Error Check

05 Number
00H
Hi Lo Hi Lo
Normal Response
Figure 43: RTU Force Single Output Message Format
Query:
 An Address of 0 indicates a broadcast request. All slave stations process a broadcast re-quest
and no response is sent.
 The Point Number field is two bytes in length. It may be any value less than the highest output
point number available in the attached CPU. It is equal to one less than the number of the output
point to be forced on or off.
 The first byte of the Data field is equal to either 0 or 255 (FFH). The output point specified in the
Point Number field is to be forced off if the first Data field byte is equal to 0. It is to be forced on if
the first Data field byte is equal to 255 (FFH). The second byte of the Data field is always equal to
zero.
Response:
 The normal response to a force single output query is identical to the query.
Note: The force single output request is not an output override command. The output specified in
this request is ensured to be forced to the value specified only at the beginning of one sweep
of the user logic.

6.3.3.6 Message (06): Preset Single Register

Format:
Address Func Register Data Error Check
06 Number
Hi Lo Hi Lo
Query
Address Func Register Data Error Check

06 Number
Hi Lo Hi Lo
Normal Response
Figure 44: RTU Preset Single Register Message Format
Query:
 An Address 0 indicates a broadcast request. All slave stations process a broadcast request and
no response is sent.
 The Register Number field is two bytes in length. It may be any value less than the highest
register available in the attached CPU. It is equal to one less than the number of the register to be
preset.
 The Data field is two bytes in length and contains the value that the register specified by the
Register Number Field is to be preset to. The first byte in the Data field contains the high order
byte of the preset value. The second byte in the Data field contains the low order byte.
Response:
 The normal response to a preset single register query is identical to the query.

6.3.3.7 Message (07): Read Exception Status

Format:
Address Func Error Check
07
Query
Address Func Data Error Check

07
Normal Response
Figure 45: RTU Read Exception Status Message Format

Query:
This query is a short form of request for the purpose of reading the first eight output points.
 An Address of zero is not allowed as this cannot be a broadcast request.
Response:
 The Data field of the normal response is one byte in length and contains the states of output
points one through eight. The output states are packed in order of number with output point
one’s state in the least significant bit and output point eight’s state in the most significant bit.

6.3.3.8 Message (08): Loopback/Maintenance (General)

Format:
Address Func Diagnostic Data Error Check
08 c Code
0, 1, or 4
DATA 1 DATA 1
Query
Address Func Diagnostic Data Error Check

08 c Code
0, 1, or 4
DATA 1 DATA 1
Normal Response
Figure 46: RTU Loopback/Maintenance Message Format
Query:
 The Function code is equal to 8.
 The Diagnostic Code is two bytes in length. The high order byte of the Diagnostic Code is the first
byte sent in the Diagnostic Code field. The low order byte is the second byte sent. The
loopback/maintenance command is defined only for Diagnostic Codes equal to 0, 1, or 4. All
other Diagnostic Codes are reserved.
 The Data field is two bytes in length. The contents of the two Data bytes are defined by the value
of the Diagnostic Code.

Response:
 See descriptions for individual Diagnostic Codes.
Diagnostic Return Query Data Request (Loopback/Maintenance Code 00):
 An address of 0 is not allowed for the return query data request.
 The values of the two Data field bytes in the query are arbitrary.
 The normal response is identical to the query.
 The values of the Data bytes in the response are equal to the values sent in the query.
Diagnostic Initiate Communication Restart Request (Loopback/Maintenance Code 01):
 An Address of 0 indicates a broadcast request. All slave stations process a broadcast request and
 This request disables the listen-only mode (enables responses to be sent when queries are
received so that communications can be restarted).
 The value of the first byte of the Data field (DATA1) must be 0 or FF. Any other value will cause an
error response to be sent. The value of the second byte of the Data field (DATA2) is always equal
to 0.
 The normal response to an Initiate Communication Restart query is identical to the query.
Diagnostic Force Listen-Only Mode Request (Loopback/Maintenance code 04):
 An Address of 0 indicates a broadcast request. All slave stations process a broadcast request.
 After receiving a Force Listen-Only mode request, the RTU device will go into the listen-only
mode, will not perform a requested function, and will not send either normal or error responses
to any queries. The listen-only mode is disabled when the RTU device receives an Initiate
Communication Restart request or when the RTU device is powered up.
 Both bytes in the Data field of a Force Listen-Only Mode request are equal to 0. The RTU device
never sends a response to a Force Listen-Only Mode request.
Note: Upon power-up, the RTU device disables the listen-only mode and is enabled to continue
sending responses to queries.

6.3.3.9 Message (15): Force Multiple Outputs

Format:
Address Func Starting Number Byte Data Error Check
15 Point
Point No. of Points Count
Query
Address Func Starting Number Error Check

15 Point
Point No. of Points
Normal Response
Figure 47: RTU Force Multiple Outputs Message Format
Query:
 An Address of 0 indicates a broadcast request. All slave stations process a broadcast request and
 The value of the Function code is 15.
 The Starting Point Number is two bytes in length and may be any value less than the highest
output point number available in the attached CPU. The Starting Point Number is equal to one
less than the number of the first output point forced by this request.
 The Number of Points value is two bytes in length. The sum of the Starting Point Number and the
Number of Points value must be less than or equal to the highest output point number available
in the attached CPU. The high order byte of the Starting Point Number and Number of Bytes fields
is sent as the first byte in each of these fields. The low order byte is the second byte in each of
these fields.
 The Byte Count is a binary number from 1 to 256 (0 = 256). It is the number of bytes in the Data
field of the force multiple outputs request.
 The Data field is packed data containing the values that the outputs specified by the Starting
Point Number and the Number of Points fields are to be forced to. Each byte in the Data field
contains the values that eight output points are to be forced to. The least significant bit (LSB) of
the first byte contains the value that the output point whose number is equal to the starting point
number plus one is to be forced to. The values for the output points are ordered by number
starting with the LSB of the first byte of the Data field and ending with the most significant bit
(MSB) of the last byte of the Data field. If the number of points is not a multiple of 8, then the last
data byte contains zeroes in one to seven of its highest order bits.
Response:
 The descriptions of the fields in the response are covered in the query description.
Note: The force multiple outputs request is not an output override command. The outputs specified
in this request are ensured to be forced to the values specified only at the beginning of one
sweep of the user logic.

6.3.3.10 Message (16): Preset Multiple Registers

Format:
Address Func Starting Number of Byte Data Error Check
16 Point Registers Count
Query
Address Func Starting Number of Error Check

16 Register No. Registers
Normal Response
Figure 48: RTU Preset Multiple Registers Message Format

Query:
 An Address of 0 indicates a broadcast request. All slave stations process a broadcast re-quest
and no response is sent.
 The value of the Function code is 16.
 The Starting Register Number is two bytes in length. The Starting Register Number may be any
value less than the highest register number available in the attached CPU. It is equal to one less
than the number of the first register preset by this request.
 The Number of Registers value is two bytes in length. It must contain a value from 1 to 125
inclusive. The sum of the Starting Register Number and the Number of Registers value must be
less than or equal to the highest register number available in the attached CPU. The high order
byte of the Starting Register Number and Number of Registers fields is sent as the first byte in
each of these fields. The low order byte is the second byte in each of these fields.
 The Byte Count field is one byte in length. It is a binary number from 2 to 250 inclusive. It is equal
to the number of bytes in the data field of the preset multiple registers request. Note that the
Byte Count is equal to twice the value of the Number of Registers.
 The registers are returned in the Data field in order of number with the lowest number register in
the first two bytes and the highest number register in the last two bytes of the Data field. The
number of the first register in the Data field is equal to the starting register number plus one. The
high order byte is sent before the low order byte of each register.
Response:
 The descriptions of the fields in the response are covered in the query description.

6.3.3.11 Message (17): Report Device Type

Format:
Address Func 17 Error Check
Query
Address Func 17 Byte Device Slave Run Data Error Check

Count Type 43 Light
Normal Response
Figure 49: RTU Report Device Type Message Format

Query:
The Report Device Type query is sent by the master to a slave in order to learn what type of
programmable control or other computer it is.
 An Address of zero is not allowed as this cannot be a broadcast request.
 The Function code is 17.
Response:
 The Byte Count field is one byte in length and is equal to 5.
 The Device Type field is one byte in length and is equal to 43 (hexadecimal) for PACSystems
 The Slave Run Light field is one byte in length. The Slave Run Light byte is equal to OFFH if the
CPU is in RUN Mode. It is equal to 0 if the CPU is not in RUN Mode.
 The Data field contains three bytes. For PACSystems CPUs, the first byte is the Minor Type, and
the remaining bytes are zeroes. The following table lists minor types.
Response Data
CPU Model58
(Minor Type)
02 hex IC698CPE010
04 hex IC698CPE020
05 hex IC698CRE020
06 hex IC698CPE030
08 hex IC698CPE040
IC695CPE305
0A hex
IC695CPU310
0C hex IC695NIU001
10 hex IC695CPU320
11 hex IC695CRU320
12 hex IC695CPE305
18 hex IC695CPU315
58 Does not apply to CPE330, which has no serial ports.

6.3.3.12 Message (22): Mask Write 4x Memory

Modifies the contents of a specified 4x register using a combination of an AND mask, an OR mask,
and the register's current contents. The function can be used to set or clear individual bits in the
register. Broadcast is not supported.
Query:
The query specifies the 4x reference to be written, the data to be used as the AND mask, and the
data to be used as the OR mask.
The function's algorithm is:
Result = (Current Contents AND And_Mask) OR (Or_Mask AND And_Mask)
For example:
Hex Binary
Current Contents 12 0001 0010
And_Mask F2 1111 0010
Or_Mask 25 0010 0101
And_Mask 0D 0000 1101
Result 17 0001 0111
Note: If the Or_Mask value is zero, the result is simply the logical ANDing of the current contents
and And_Mask. If the And_Mask value is zero, the result is equal to the Or_Mask value.
Note: The contents of the register can be read with the Read Holding Registers function (function
code 03). They could, however, be changed subsequently as the controller scans its user logic
program.
Example of a Mask Write to register 5 in slave device 17, using the above mask values:
Field Name Example (Hex)
Slave Address 11
Function 16
Reference Address Hi 00
Reference Address Lo 04
And_Mask Hi 00
And_Mask Lo F2
Or_Mask Hi 00
Or_Mask Lo 25
Error Check (LRC or CRC) --
Response:
The normal response is an echo of the query. The response is returned after the register has been
written.

6.3.3.13 Message (23): Read Write 4x Memory

Performs a combination of one read and one write operation in a single Modbus transaction. The
function can write new contents to a group of 4x registers, and then return the contents of another
group of 4x registers. Broadcast is not supported.
Query:
The query specifies the starting address and quantity of registers of the group to be read. It also
specifies the starting address, quantity of registers, and data for the group to be written. The Byte
Count field specifies the quantity of bytes to follow in the Write Data field.
Here is an example of a query to read six registers starting at register 5, and to write three registers
starting at register 16, in slave device 17:
Slave address 11
Function 17
Read Reference Address Hi 00
Read Reference Address Lo 04
Quantity to Read Hi 00
Quantity to Read Lo 06
Write Reference Address Hi 00
Write Reference Address Lo 0F
Quantity to Write Hi 00
Quantity to Write Lo 03
Byte Count 06
Write Data 1 Hi 00
Write Data 1 Lo FF
Write Data 2 Hi 00
Write Data 2 Lo FF
Write Data 3 Hi 00
Write Data 3 Lo FF

Response:
The normal response contains the data from the group of registers that were read. The Byte Count
field specifies the quantity of bytes to follow in the Read Data field.
Here is an example of a response to the query:
Slave Address 11
Function 17
Byte Count 0C
Read Data 1 Hi 00
Read Data 1 Lo FE
Read Data 2 Hi 0A
Read Data 2 Lo CD
Read Data 3 Hi 00
Read Data 3 Lo 01
Read Data 4 Hi 00
Read Data 4 Lo 03
Read Data 5 Hi 00
Read Data 5 Lo 0D
Read Data 6 Hi 00
Read Data 6 Lo FF

6.3.3.14 Message (67): Read Scratch Pad Memory

Format:
67 Byte No. Bytes Check
Query

67 Count Check
Normal Response
Figure 50: RTU Read Scratch Pad Memory Message Format
Query:
 An Address of 0 is not allowed as this cannot be a broadcast request.
 The Function Code is equal to 67.
 The Starting Byte Number is two bytes in length and may be any value less than or equal to the
highest scratch pad memory address available in the attached CPU as indicated in the table
below. The Starting Byte Number is equal to the address of the first scratch pad memory byte
returned in the normal response to this request.
 The Number of Bytes value is two bytes in length. It specifies the number of scratch pad memory
locations (bytes) returned in the normal response. The sum of the Starting Byte Number and the
Number of Bytes values must be less than two plus the highest scratch pad memory address
available in the attached CPU. The high order byte of the Starting Byte Number and Number of
Bytes fields is sent as the first byte in each of these fields. The low order byte is the second byte in
each of the fields.
Response:
 The Byte Count is a binary number from 1 to 256 (0 = 256). It is the number of bytes in the Data
field of the normal response.
 The Data field contains the contents of the scratch pad memory requested by the query. The
scratch pad memory bytes are sent in order of address. The contents of the scratch pad memory
byte whose address is equal to the Starting Byte Number is sent in the first byte of the Data field.
The contents of the scratch pad memory byte whose address is equal to one less than the sum of
the starting byte number and number of bytes values is sent in the last byte of the Data field.

6.3.4 RTU Scratch Pad

The entire scratch pad is updated every time an external READ request is received by the
PACSystems RTU slave. All scratch pad locations are read only. The scratch pad is a byte-oriented
memory type.
6.3.4.1 RTU Scratch Pad Memory Allocation
Bits
SP Address Field Identifier
7 6 5 4 3 2 1 0
00 CPU Run Status 0 0 0 0 See note.59
01 CPU Command Status Bit pattern same as SP(00)
02 Major60 (in hexadecimal)
CPU Type
03 Minor61 (in hexadecimal)
04 – 0B CPU SNP ID 7 ASCII characters + termination character (00h)
0C Major (in BCD)
CPU Firmware Revision No.
0D Minor (in BCD)
0E Communications Management Module Major
0F (CMM) Firmware Revision No. Minor
10—11 Reserved 00h
12 Node Type Identifier PACSystems 43 (hexadecimal)
13—15 Reserved 00h
16 RTU Station Address 1—247 (decimal)
17 Reserved 00h
18—3362 Sizes of Memory Types
18—1B Register Memory %R size (words)
1C—1F Analog Input Table %AI size (words)
20—23 Analog Output Table %AO size (words)
24—27 Input Table %I size (bits)
28—2B Output Table %O size (bits)
2C—2F Internal Discrete Memory %M size (bits)
The amount of program memory occupied by the logic
30—33 User Program Code
program.
34—FF Reserved 00h
59 0000 = Run_Enabled 0100 = Halted 0001 = Run_Disabled

0101 = Suspended 0010 = Stopped 0110 = Stopped_IO_Enabled
60 CPU Major Type Codes: PACSystems 0x43
61 PACSystems Minor Types for CPU: refer to Message (17): Report Device Type
62 Four bytes hold the hexadecimal length of each memory type with the most significant word reserved for future
expansion. For example, the default register memory size of 1024 words (0400h) would be returned in the following
format:
Word Least Significant Most Significant
SP Byte 18 19 1A 1B
Contains 00 04 00 00

6.3.5 Communication Errors

Serial link communication errors are divided into three groups:
 Invalid Query Message
 Serial Link Time Outs
 Invalid Transaction
6.3.5.1 Invalid Query Message
When the communications module receives a query addressed to itself, but cannot process the
query, it sends one of the following error responses:
Subcode
Invalid Function Code 1
Invalid Address Field 2
Invalid Data Field 3
Query Processing Failure 4
The format for an error response to a query is as follows:
Address Exception Error Error
Func Subcode Check
Figure 51: RTU Error Response Format

The address reflects the address provided on the original request. The exception function code is
equal to the sum of the function code of the query plus 128. The error subcode is equal to 1, 2, 3, or 4.
The value of the subcode indicates the reason the query could not be processed.
Invalid Function Code Error Response (1)

An error response with a subcode of 1 is called an invalid function code error response. This response
is sent by a slave if it receives a query whose function code is not equal to 1- 8, 15, 16, 17, or 67.
Note: Starting with Release 6.70 for the RX3i, the invalid function code error response is not used.
Instead, undefined and unsupported function codes are ignored, and no response is
generated.

Invalid Address Error Response (2)

An error response with a subcode of 2 is called an invalid address error response. This error response
is sent in the following cases:
1. The Starting Point Number and Number of Points fields specify output points or input points that
are not available in the attached CPU (returned for function codes 1, 2, 15).
2. The Starting Register Number and Number of Registers fields specify registers that are not
available in the attached CPU (returned for function codes 4, 16).
3. The Starting Analog Input Number and Analog Input Number fields specify analog inputs that are
not available in the attached CPU (returned for function code 3).
4. The Point Number field specifies an output point not available in the attached CPU (returned for
function code 5).
5. The Register Number field specifies a register not available in the attached CPU (returned for
function code 6).
6. The Analog Input Number field specifies an analog input number not available in the at-attached
CPU (returned for function code 3).
7. The Diagnostic Code is not equal to 0, 1, or 4 (returned for function code 8).
8. The starting Byte Number and Number of Bytes fields specify a scratch pad memory address that
is not available in the attached CPU (returned for function code 67).
Invalid Data Value Error Response (3)
An error response with a subcode of 3 is called an invalid data value error response. This response is
sent in the following cases:
The first byte of the Data field is not equal to 0 or 255 (FFh) or the second byte of the Data field is not
equal to 0 for the Force Single Output Request (Function Code 5) or the initiate communication
restart request (function code 8, diagnostic code 1). The two bytes of the Data field are not both
equal to 0 for the Force Listen-Only request (Function Code 8, Diagnostic Code 4). This response is
also sent when the data length specified by the Memory Address field is longer than the data
received.
Query Processing Failure Error Response (4)
An error response with a subcode of 4 is called a query processing failure response. This error
response is sent by a RTU device if it properly receives a query but communication between the
associated CPU and the CMM fails.

6.3.5.2 Serial Link Timeout

The only cause for a RTU device to timeout is if an interruption to a data stream of 4 character times
occurs while a message is being received. If this occurs the message is considered to have
terminated and no response will be sent to the master. There are certain timing considerations due
to the characteristics of the slave that should be taken into account by the master. After sending a
query message, the master should wait an appropriate amount of time for slave turnaround before
assuming that the slave did not respond to the request. Slave turnaround time is affected by the
Controller Communications Window time and the CPU sweep time, as described in RTU Slave
Turnaround Time.
6.3.5.3 Invalid Transactions
If an error occurs during transmission that does not fall into the category of an invalid query
message or a serial link time-out, it is known as an invalid transaction. Types of errors causing an
invalid transaction include:
 Bad CRC.
 The data length specified by the Memory Address field is longer than the data received.
 Framing or overrun errors.
 Parity errors.
If an error in this category occurs when a message is received by the slave serial port, the slave does
not return an error message; rather the slave ignores the incoming message, treating the message
as though it was not intended for it.

6.3.6 RTU Slave/SNP Slave Operation with Programmer Attached

A port that has been configured for RTU Slave protocol can switch to SNP protocol if an SNP master
such as a programmer begins communicating to the port. The programmer must use the same serial
communications parameters (baud rate, parity, stop bits, etc.) as the currently active RTU Slave
protocol for it to be recognized. When the CPU recognizes the SNP master, the CPU removes the RTU
Slave protocol from the port and installs SNP Slave as the active protocol.
The SNP protocol that is installed in this case has the following fixed characteristics:
 The SNP ID is set to blank. Therefore, the SNP master must use a blank ID in the SNP attach
message. This also means that this capability is only useful for point-to-point connections.
 The turnaround time is set to 0ms.
 The idle timeout is set to 10 seconds.
After the programmer is removed, there is a slight delay (equal to the idle timeout) before the CPU
recognizes its absence. During this time, no messages are processed on the port. The CPU detects
removal of the programmer as an SNP Slave protocol timeout. Therefore, it is important to be careful
when disabling timeouts used by the SNP Slave protocol.
When the CPU recognizes the programmer disconnect, it reinstalls RTU Slave protocol unless a new
protocol has been configured in the meantime. In that case, the CPU installs the new protocol
instead.
Example
1. COM1 is running RTU Slave protocol at 9600 baud.
2. A programmer is attached to COM1. The programmer is using 9600 baud.
3. The CPU installs SNP Slave on COM1 and the programmer communicates normally.
4. The programmer stores a new configuration to COM1. The new configuration sets the port for
SNP Slave at 4800 baud (it will not take effect until the port loses communications with the
programmer).
5. When the CPU loses communications with the programmer, the new configuration takes effect.

6.4 SNP Slave Protocol

PACSystems CPUs can communicate with Machine Edition software through either COM1 or COM2
using SNP slave protocol.
CPU COM1 is wired as an RS-232 Data Communications Equipment (DCE) port, and can be connected
directly using straight-through cable to one of the serial ports of a PC running Machine Edition or
other SNP master software.
CPU COM2 is wired for RS-485. If the SNP master does not have an RS-485 port, an RS-485/RS-232
converter is required. The RX3i can use converter IC690ACC901, which uses +5Vdc from the serial
port. The RX7i CPU COM2 does not support IC690ACC901 and requires an externally powered
converter.
PACSystems provides the break free version of SNP, so that the SNP master does not need to issue a
break signal as part of the SNP attach sequence. However, the CPU responds appropriately if a break
signal is detected, by resetting the protocol to wait for another attach sequence from the master.
PACSystems supports both point-to-point connections (single master/single slave) and multi-drop
connections (single master/multiple slaves).
For details on SNP protocol, refer to the Series 90 PLC Serial Communications User’s Manual,
GFK-0582.
6.4.1 Permanent Datagrams
Permanent datagrams survive after the SNP session that created them has been terminated. This
allows an SNP master device to periodically retrieve datagram data from a number of different
controllers on a multi-drop link, without the master having to establish and write the datagram each
time it reconnects to the controller.
The maximum number of permanent datagrams that can be established is 32. When this limit is
reached, additional requests to establish datagrams are denied. One or more of the permanent
datagrams will need to be cancelled before others can be established. Since the permanent
datagrams are not automatically deleted when the SNP session is terminated, this limit prevents an
inordinate amount of these datagrams from being established.
Permanent datagrams do not survive a power-cycle.
6.4.2 Communication Requests (COMMREQs) for SNP
The PACSystems serial ports COM1 and COM2 currently do not provide SNP Master service, nor do
they support COMMREQ functions for SNP commands. However, those COMMREQ functions can be
used with PCM/CMM modules that are configured to provide SNP service. For more information, refer
to the Series 90 PLC Serial Communications User’s Manual, GFK-0582.

Appendix A Performance Data
This appendix contains instruction and overhead timing collected for each PACSystems CPU module.
This timing information can be used to predict CPU sweep times. The information in this appendix is
organized as follows:
 Boolean Execution Times
 Instruction Timing
 Overhead Sweep Impact Times

Appendix A. Performance Data
A-1 Boolean Execution Times

Boolean execution times for contacts and coils depend on several factors, including the CPU model,
the type of reference address associated with the contact/coil, and whether the address is used
directly or passed as a parameter. To help compare Boolean performance across PACSystems CPUs,
average time measurements are presented below for each CPU model.
The measurements are for these three categories:
 Simple address: Boolean with a simple reference address that is known at compile/validation
time. For example, a symbolic variable, or a mapped variable, such as %I00001, or a Boolean
from an array that is indexed by a constant, such as BoolArray[3].
 Complex address: Boolean with a complex address that requires run-time computation to
resolve. For example, a Boolean from an array that is indexed by a variable, such as
BoolArray[j].
 Passed as parameter: Boolean within a parameterized block or UDFB, where the reference
address of the Boolean is passed as a parameter to the block. The measurement covers the
Boolean execution time within the block, but does not include the time to compute the
reference address before passing it to the block.
A-1.1 Boolean Execution Measurements (ms per 1000 Boolean executions)63

Boolean Category
CPU Model
Simple Address Complex Address Passed as Parameter
CPE400
CPE330
CPU310 0.253 1.371 0.467
CPE310 0.103 0.512 0.203
CPE305 0.102 0.513 0.203
CPU320 / CPU315 0.053 0.272 0.113
CRU320 0.055 0.272 0.111
CPE010 0.244 1.329 0.469
CPE020 0.095 0.543 0.198
CRE020 0.096 0.556 0.194
CPE030 0.087 0.450 0.183
CRE030 0.090 0.451 0.184
CPE040 0.029 0.150 0.061
CRE040 0.029 0.149 0.061
63 Measured with CPU firmware version 7.18.

A-2 Instruction Timing

A-2.1 Overview
The tables in this section list the execution and incremental times in microseconds (µs) for each
function supported by the PACSystems CPUs. Two execution times are shown for each instruction.
Execution Time Description
Enabled Time in µs required to execute the function or function block when power flows
into the function with valid inputs.
Disabled Time in µs required to execute the function when it is not enabled.
Notes:
 All times represent typical execution time. Times may vary with input and error conditions.
 Enabled time is for single length units of word-oriented memory.
 COMMREQ time was measured between CPU and Ethernet module with NOWAIT option.
 DOIO time was measured using a discrete output module.
 Timers are updated each time they are encountered in the logic by the amount of time
consumed by the last sweep.
 Performance times for the BUS_ functions were measured on the RX7i using a Series 90-70
Genius Bus Controller, and on the RX3i using an RMX128 Redundancy Memory Xchange Module.
 Performance times for all redundancy (CRE and CRU) CPUs were measured with ECC enabled.
 Due to a change in caching, measured times for some instructions changed for release 6.0 as
compared to releases 5.0/5.1. It was found that increases in some instructions were offset by
decreases in other instructions, so that no effective net change was observed.

A-2.2 PLC Version Information

The instruction execution and incremental times were obtained by testing the following CPU versions:
Model PLC Firmware Version
All instructions IC695CPE400 9.00
except as listed below
IC695CPE305/CPE310/CPE330 7.10
IC695CPU310/CPU315 6.0
IC695CPU320/IC695CRU32064 7.18
IC698CPE010/CPE020 6.0
IC698CRE020 6.0 (with ECC enabled)
IC698CPE030/CPE040 6.0
IC698CRE030/CRE040 6.0 (with ECC enabled)
MOVE_UINT CPE010/020 3.5

CRE02064 2.04 (with ECC enabled)
SVC_REQs for Redundancy IC695CRU32064 6.0 (with ECC enabled)
TON, TOF, TP Instructions CPU310/CPU315/CPU320, CRU320 5.7

CPE010/CPE030/CPE040 3.6
CRE030/CRE04064 3.6 (with ECC enabled)
Instructions for PACMotion CPU315/CPU320 5.6

CPU310 6.0
64 Due to Error Checking and Correction (ECC), Redundant CPU times are approximately 5% slower, on average, than the
equivalent Non-Redundant CPU.

A-2.3 RX3i Instruction Times

CPE305 /CPE310 CPU310 CPU315/ CPU320/ CRU32065
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Bit Operation
AND_WORD 1.47 0.51 3.40 1.45 0.84 0.46 0.911 0.382
AND_DWORD 1.433 0.44 3.50 1.46 0.84 0.46 0.968 0.378
OR_WORD 1.332 0.44 3.40 1.50 0.84 0.47 0.891 0.437
OR_DWORD 1.387 0.45 3.63 1.51 0.89 0.47 0.919 0.375
XOR_WORD 1.347 0.46 3.37 1.44 0.86 0.46 0.908 0.375
XOR_DWORD 1.391 0.47 3.46 1.45 0.83 0.46 0.866 0.388
NOT_WORD 1.089 0.40 2.97 1.29 0.64 0.42 0.659 0.274
NOT_DWORD 1.03 0.37 2.93 1.32 0.67 0.40 0.662 0.282
MCMP_WORD 2.477 0.80 5.58 2.29 1.51 0.61 1.668 0.605
MCMP_DWORD 2.385 0.74 5.61 2.20 1.50 0.63 1.682 0.636
SHL_WORD 1.921 0.84 4.52 2.39 1.15 0.56 1.275 0.633
SHL_DWORD 1.903 0.77 4.54 2.44 1.12 0.56 1.321 0.665
SHR_WORD 1.875 0.76 5.15 2.43 1.18 0.57 1.26 0.614
SHR_DWORD 1.864 0.78 4.69 2.45 1.14 0.57 1.24 0.616
ROL_WORD 1.176 0.48 2.99 1.50 0.68 0.46 0.735 0.431
ROL_DWORD 1.125 0.42 3.22 1.53 0.64 0.46 0.773 0.402
ROR_WORD 1.105 0.41 2.91 1.43 0.66 0.46 0.704 0.431
ROR_DWORD 1.116 0.43 2.87 1.44 0.71 0.46 0.711 0.384
BTST_WORD 1.333 0.45 3.22 1.27 0.71 0.35 0.693 0.314
BTST_DWORD 1.265 0.39 3.09 1.26 0.71 0.34 0.73 0.321
BSET_WORD 0.897 0.35 2.38 1.17 0.59 0.30 0.635 0.293
BSET_DWORD 0.88 0.37 2.36 1.14 0.58 0.30 0.635 0.293
BCLR_WORD 0.849 0.35 2.39 1.14 0.59 0.30 0.659 0.316
BCLR_DWORD 0.86 0.33 2.45 1.19 0.59 0.30 0.623 0.291
BPOS_WORD 1.719 0.47 4.03 1.33 0.80 0.23 1.024 0.309
BPOS_DWORD 1.941 0.40 4.83 1.31 0.96 0.22 1.302 0.324
Relational
CMP_INT 1.623 0.41 3.52 1.16 0.89 0.33 1.11 0.363
CMP_DINT 1.552 0.38 3.54 1.19 0.91 0.34 1.143 0.393
CMP_REAL 1.619 0.39 3.63 1.20 0.94 0.35 1.146 0.362
CMP_LREAL 1.835 0.44 3.92 1.13 1.08 0.34 1.227 0.361
CMP_UINT 1.485 0.39 3.50 1.17 0.93 0.33 1.097 0.361
EQ_DATA - - 10.63 7.98 2.37 1.29
EQ_DATA_INPUTREF 2.247 0.12 -- -- -- -- 1.55 0.448
EQ_DATA_AXISREF 2.377 0.32 -- -- -- -- 1.616 0.491
EQ_DINT 1.074 0.29 2.32 0.96 0.65 0.24 0.737 0.277

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
EQ_INT 1.123 0.36 2.45 0.96 0.66 0.24 0.69 0.276
EQ_LREAL 1.174 0.37 2.88 1.07 0.78 0.26 0.832 0.282
EQ_REAL 1.05 0.30 2.38 0.96 0.66 0.26 0.677 0.328
EQ_UINT 1.01 0.31 2.37 0.96 0.65 0.25 0.659 0.269
NE_INT 1.03 0.32 2.29 0.98 0.64 0.24 0.715 0.292
NE_DINT 1.074 0.33 2.37 1.00 0.66 0.24 0.718 0.269
NE_UINT 1.14 0.34 2.39 0.96 0.66 0.24 1.029 0.583
NE_REAL 1.076 0.32 2.35 0.95 0.67 0.25 0.863 0.408
NE_LREAL 1.142 0.35 2.87 1.04 0.79 0.26 0.926 0.279
GT_INT 1.035 0.31 2.49 0.98 0.66 0.25 0.703 0.269
GT_DINT 1.018 0.31 2.34 1.01 0.65 0.24 0.714 0.268
GT_REAL 1.057 0.31 2.36 0.94 0.65 0.24 0.714 0.269
GT_LREAL 1.146 0.36 2.82 1.02 0.77 0.27 0.893 0.324
GT_UINT 1.048 0.31 2.37 0.95 0.66 0.24 0.714 0.27
GE_INT 1.017 0.31 2.44 0.93 0.68 0.24 0.682 0.269
GE_DINT 1.082 0.32 2.43 1.01 0.66 0.24 0.675 0.284
GE_REAL 1.075 0.32 2.35 0.94 0.66 0.26 0.678 0.266
GE_LREAL 1.154 0.34 2.85 1.04 0.77 0.26 0.817 0.282
GE_UINT 1.03 0.32 2.44 1.03 0.67 0.24. 0.677 0.272
LT_INT 1.049 0.32 2.53 1.02 0.64 0.24 0.712 0.281
LT_DINT 1.08 0.33 2.37 1.05 0.65 0.25 0.72 0.269
LT_REAL 1.044 0.32 2.37 0.97 0.64 0.25 0.873 0.409
LT_LREAL 1.139 0.35 2.81 1.01 0.77 0.26 0.882 0.299
LT_UINT 1.087 0.31 2.41 0.95 0.65 0.24 0.71 0.271
LE_INT 1.123 0.32 2.46 0.99 0.69 0.25 0.678 0.269
LE_DINT 1.014 0.31 2.33 1.03 0.65 0.25 0.665 0.27
LE_UINT 1.045 0.32 2.44 1.02 0.64 0.24 0.683 0.283
LE_REAL 1.03 0.31 2.34 1.00 0.65 0.25 0.676 0.27
LE_LREAL 1.136 0.35 2.78 0.98 0.77 0.26 0.818 0.291
Conversion
BCD-4 to INT 0.933 0.30 2.17 1.00 0.55 0.23 0.544 0.25
DINT to INT 0.694 0.30 1.90 0.98 0.55 0.21 0.507 0.247
UINT to INT 0.736 0.30 2.04 0.94 0.49 0.20 0.583 0.234
BCD-8 to DINT 0.889 0.28 2.58 0.97 0.62 0.21 0.612 0.235
INT to DINT 0.672 0.29 1.88 0.2 0.51 0.21 0.567 0.232
UINT to DINT 0.771 0.32 1.90 0.96 0.63 0.21 0.591 0.227
INT to UINT 0.724 0.30 1.93 0.93 0.62 0.21 0.551 0.251
DINT to UINT 0.674 0.30 1.92 1.06 0.50 0.21 0.517 0.248
BCD-4 to UINT 0.792 0.35 2.18 1.04 0.55 0.22 0.603 0.247
INT to BCD-4 0.922 0.30 2.19 0.93 0.61 0.22 0.596 0.239
UINT to BCD-4 0.853 0.30 2.17 0.94 0.67 0.22 0.644 0.229
DINT to BCD-8 0.849 0.30 2.35 1.03 0.62 0.21 0.63 0.235

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
REAL_TO_INT 0.922 0.31 2.43 1.00 0.66 0.21 0.665 0.23
REAL_TO_UINT 0.882 0.30 2.37 0.99 0.63 0.21 0.637 0.239
REAL_TO_LREAL 0.697 0.31 2.10 0.95 0.52 0.21 0.555 0.224
REAL_TO_DINT 0.877 0.30 2.42 0.99 0.64 0.21 0.638 0.24
INT_TO_REAL 0.707 0.31 2.00 0.98 0.49 0.22 0.521 0.255
UINT_TO_REAL 0.724 0.31 1.87 0.95 0.55 0.23 0.595 0.239
DINT_TO_REAL 0.773 0.30 1.95 1.02 0.56 0.21 0.516 0.231
DINT_TO_LREAL 0.741 0.36 2.06 1.02 0.50 0.20 0.584 0.248
REAL_TRUN_INT 0.757 0.34 1.77 0.73 0.45 0.19 0.515 0.16
REAL_TRUN_DINT 0.776 0.35 1.84 0.83 0.52 0.19 0.516 0.167
DEG_TO_RAD_REAL 0.749 0.28 1.90 1.01 0.55 0.21 0.515 0.24
DEG_TO_RAD_LREAL 0.901 0.34 2.33 0.94 0.64 0.23 0.63 0.249
RAD_TO_DEG_REAL 0.703 0.28 1.91 0.97 0.59 0.21 0.515 0.25
RAD_TO_DEG_LREAL 0.789 0.32 2.33 0.94 0.64 0.23 0.636 0.256
BCD-4 to REAL 0.852 0.30 2.30 1.03 0.56 0.20 0.692 0.301
BCD-8 to REAL 0.996 0.30 2.62 0.94 0.66 0.20 0.661 0.25
LREAL_TO_DINT 0.869 0.33 2.67 1.03 0.63 0.20 0.673 0.23
LREAL_TO_REAL 0.666 0.30 2.25 1.01 0.54 0.21 0.549 0.224
Data Move
BLKCLR 0.796 0.29 1.96 0.96 0.45 0.19 0.528 0.223
BITSEQ 0.175 0.15 1.14 4.14 0.90 0.89
MOVE_BIT 1.162 0.41 3.00 1.37 0.67 0.25 0.861 0.245
MOVE_DINT 0.864 0.37 2.21 1.32 0.47 0.43 0.533 0.292
MOVE_INT 0.857 0.38 2.21 1.33 0.48 0.44
MOVE_UINT - - - - - - 0.523 0.305
MOVE_WORD 0.919 0.44 2.15 1.25 0.48 0.41 0.551 0.298
MOVE_DWORD 0.884 0.36 2.15 1.24 0.48 0.42 0.548 0.293
MOVE_REAL 0.844 0.35 2.15 1.24 0.47 0.41 0.594 0.354
MOVE_LREAL 1.136 0.41 2.63 1.27 0.57 0.41 0.604 0.297
MOVE_DATA - - 8.36 2.36 2.16 1.20 - -
MOVE_DATA_INPUTREF 2.094 0.34 10.63 2.60 - - 2.077 0.384
MOVE_DATA_AXISREF 2.437 0.39 10.63 2.60 - - 2.172 0.376
MOVE_DATA_EX 2.094 0.34 9.28 1.98 2.60 1.66 2.23 0.544
MOVE_DATA_EX_INPUTREF 2.437 0.39 9.28 1.98 - - 2.509 0.587
MOVE_TO_FLAT 2.094 0.34 9.28 1.98 2.60 1.66 2.23 0.544
MOVE_FROM_FLAT 2.094 0.34 9.28 1.98 2.60 1.66 2.23 0.544
BLKMOV_WORD 1.009 0.72 2.89 2.17 0.68 0.60 0.788 0.511
BLKMOV_DWORD 1.019 0.65 3.03 2.17 0.71 0.54 0.862 0.517
BLKMOV_DINT 1.133 0.68 3.04 2.22 0.71 0.55 0.842 0.541
BLKMOV_INT 0.938 0.69 2.78 2.13 0.69 0.60 0.8 0.511
BLKMOV_REAL 1.004 0.66 2.98 2.14 0.70 0.53 0.853 0.528
BLKMOV_UINT 0.91 0.65 2.79 2.09 0.67 0.60 0.785 0.531

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
DATA_INIT_ASCII 0.432 0.45 0.89 1.25 0.20 0.35 0.176 0.236
DATA_INIT_COMM 0.37 0.36 1.03 1.20 0.22 0.34 0.196 0.221
DATA_INIT_DLAN 0.433 0.39 1.33 1.32 0.33 0.35 0.254 0.238
DATA_INIT_DINT 0.313 0.37 0.89 1.21 0.21 0.33 0.169 0.24
DATA_INIT_DWORD 0.313 0.36 0.97 1.26 0.21 0.34 0.172 0.221
DATA_INIT_INT 0.343 0.38 0.94 1.27 0.20 0.33 0.178 0.231
DATA_INIT_REAL 0.344 0.38 0.91 1.22 0.21 0.35 0.172 0.248
DATA_INIT_LREAL 0.468 0.41 0.96 1.18 0.18 0.34 0.183 0.248
DATA_INIT_WORD 0.342 0.36 0.97 1.27 0.20 0.34 0.179 0.219
DATA_INIT_UINT 0.419 0.37 0.93 0.9 0.21 0.35 0.16 0.254
SWAP_WORD 0.976 0.36 2.67 1.24 0.58 0.41 0.616 0.291
SWAP_DWORD 1.008 0.38 2.75 1.29 0.59 0.41 0.62 0.308
SHFR_BIT 2.461 1.11 6.52 2.88 1.45 0.64 1.621 0.705
SHFR_WORD 2.441 1.49 7.13 4.94 1.94 1.40 2.072 1.51
SHFR_DWORD 2.403 1.48 7.16 4.91 2.00 1.42 2.127 1.493
Data Table
SORT_INT 15.58 0.40 36.56 1.25 9.89 0.42 9.743 0.295
SORT_UINT 15.436 0.35 36.49 1.24 9.86 0.42 9.628 0.296
SORT_WORD 15.516 0.36 36.46 1.26 9.87 0.42 9.613 0.332
TBLRD_INT 1.299 0.47 3.49 1.23 0.88 0.33 0.968 0.402
TBLRD_DINT 1.21 0.44 3.58 1.27 0.90 0.33 0.887 0.345
TBLWRT_INT 1.71 0.53 4.02 1.53 1.03 0.41 1.06 0.388
TBLWRT_DINT 1.599 0.48 3.94 1.52 1.03 0.42 1.113 0.391
FIFORD_INT 1.67 0.54 4.04 1.68 0.92 0.41 0.931 0.405
FIFORD_DINT 1.627 0.55 4.00 1.69 0.92 0.41 0.927 0.408
FIFOWRT_INT 1.189 0.32 3.06 1.21 0.83 0.30 0.838 0.358
FIFOWRT_DINT 1.197 0.31 3.05 1.19 0.84 0.30 0.836 0.278
LIFORD_INT 1.563 0.54 3.83 1.69 0.87 0.41 0.887 0.403
LIFORD_DINT 1.508 0.54 3.81 1.64 0.87 0.41 0.886 0.403
LIFOWRT_INT 1.211 0.33 3.06 1.18 0.83 0.30 0.836 0.278
LIFOWRT_DINT 1.194 0.35 3.05 1.19 0.83 0.32 0.837 0.284
LIFOWRT_DWORD 1.2 0.34 3.06 1.18 0.83 0.30 0.838 0.293
Array
ARRAY_MOVE_BIT 1.787 0.69 4.62 2.03 0.91 0.51 0.984 0.504
ARRAY_MOVE_BYTE 1.385 0.57 3.62 1.84 0.78 0.57 0.927 0.49
ARRAY_MOVE_WORD 1.335 0.59 3.67 1.92 0.80 0.57 0.858 0.556
ARRAY_MOVE_DWORD 1.346 0.59 3.61 1.85 0.80 0.58 0.86 0.49
ARRAY_MOVE_DINT 1.368 0.59 3.62 1.94 0.80 0.57 0.856 0.491
ARRAY_MOVE_INT 1.357 0.61 3.72 1.99 0.80 0.57 0.868 0.496
ARRAY_MOVE_UINT 1.408 0.61 3.61 1.87 0.79 0.58 0.88 0.491
SRCH_BYTE 1.8 0.63 4.35 1.86 1.04 0.46 1.254 0.487
SRCH_WORD 1.666 0.57 4.05 1.81 1.02 0.46 1.306 0.508

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
SRCH_DWORD 1.721 0.57 4.17 1.82 1.12 0.46 1.245 0.531
ARRAY_RANGE_WORD 1.715 0.59 4.16 1.77 1.00 0.42 1.159 0.419
ARRAY_RANGE_DWORD 1.714 0.53 4.43 1.78 1.21 0.42 1.209 0.417
ARRAY_RANGE_DINT 1.724 0.54 4.47 1.83 1.16 0.43 1.171 0.419
ARRAY_RANGE_INT 1.647 0.53 4.69 1.85 1.16 0.41 1.185 0.404
ARRAY_RANGE_UINT 1.706 0.55 4.17 1.84 1.11 0.41 1.162 0.406
Math
ADD_INT 0.932 0.41 2.08 1.19 0.70 0.30 0.796 0.28
ADD_DINT 0.841 0.35 2.22 1.17 0.63 0.31 0.825 0.272
ADD_REAL 0.819 0.34 2.12 1.13 0.61 0.32 0.751 0.327
ADD_LREAL 0.962 0.38 3.09 1.20 0.75 0.31 0.94 0.299
ADD_UINT 0.801 0.34 2.08 1.14 0.64 0.30 0.717 0.259
SUB_INT 0.805 0.34 2.08 1.15 0.66 0.30 0.729 0.258
SUB_DINT 0.846 0.33 2.17 1.13 0.64 0.30 0.75 0.258
SUB_REAL 0.826 0.34 2.17 1.18 0.62 0.31 0.743 0.26
SUB_LREAL 0.998 0.40 2.81 1.27 0.81 0.31 0.958 0.3
MUL_INT 0.822 0.34 2.21 1.13 0.64 0.30 0.727 0.258
MUL_DINT 0.883 0.35 2.20 1.20 0.63 0.31 0.765 0.255
MUL_REAL 0.86 0.35 2.13 1.14 0.57 0.31 0.752 0.265
MUL_LREAL 0.97 0.39 3.03 1.44 0.75 0.33 0.94 0.29
MUL_MIXED 0.913 0.37 2.06 1.19 0.64 0.31 0.823 0.275
MUL_UINT 0.8 0.34 2.42 1.18 0.65 0.30 0.728 0.259
DIV_INT 0.913 0.35 2.35 1.19 0.64 0.30 0.74 0.268
DIV_DINT 0.904 0.36 2.45 1.21 0.64 0.31 0.77 0.281
DIV_REAL 0.894 0.34 2.39 1.13 0.69 0.30 0.761 0.258
DIV_LREAL 1.012 0.39 2.93 1.20 0.79 0.31 0.962 0.279
DIV_MIXED 1.00 0.34 2.45 1.15 0.67 0.30 0.788 0.259
MOD_INT 0.903 0.35 2.36 1.23 0.69 0.31 0.762 0.278
MOD_DINT 0.904 0.35 2.30 1.18 0.64 0.31 0.742 0.277
MOD_UINT 0.82 0.35 2.23 1.19 0.71 0.31 0.83 0.261
ABS_INT 0.728 0.29 1.96 0.91 0.51 0.23 0.555 0.241
ABS_DINT 0.717 0.29 1.99 0.91 0.56 0.23 0.528 0.241
ABS_REAL 0.751 0.28 2.12 0.96 0.56 0.21 0.521 0.239
ABS_LREAL 0.875 0.38 2.54 1.01 0.62 0.22 0.678 0.24
SCALE_INT 1.12 0.58 3.07 1.54 0.85 0.44 0.931 0.437
SCALE_DINT 1.263 0.56 2.65 1.51 0.71 0.51 0.991 0.429
SCALE_UINT 1.067 0.55 2.70 1.50 0.71 0.49 0.9 0.404
SQRT_INT 0.905 0.26 2.36 0.93 0.63 0.21 0.618 0.24
SQRT_DINT 0.906 0.33 2.86 0.93 0.69 0.21 0.742 0.24
SQRT_REAL 0.812 0.28 2.15 0.92 0.55 0.23 0.592 0.293
SQRT_LREAL 0.897 0.30 2.60 1.02 0.65 0.22 0.644 0.244

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Trigonometric
SIN_REAL 1.031 0.28 2.48 0.92 0.61 0.22 0.628 0.239
SIN_LREAL 1.063 0.35 2.97 1.02 0.74 0.22 0.74 0.294
COS_REAL 0.988 0.28 2.41 0.93 0.67 0.21 0.616 0.239
COS_LREAL 1.04 0.28 2.93 1.02 0.75 0.21 0.736 0.235
TAN_REAL 1.156 0.28 2.53 0.92 0.63 0.21 0.635 0.24
TAN_LREAL 1.086 0.32 3.03 1.02 0.83 0.22 0.776 0.236
ASIN_REAL 1.096 0.28 2.80 0.98 0.73 0.21 0.743 0.24
ASIN_LREAL 1.127 0.49 3.23 1.00 0.88 0.21 0.835 0.223
ACOS_REAL 1.096 0.28 2.80 0.98 0.73 0.21 0.743 0.24
ACOS_LREAL 1.221 0.33 3.27 0.99 0.88 0.21 0.845 0.239
ATAN_REAL 1.013 0.29 2.56 1.03 0.67 0.23 0.63 0.256
ATAN_LREAL 0.992 0.31 2.88 1.00 0.76 0.21 0.719 0.24
Logarithmic
LOG_REAL 0.977 0.29 2.46 0.99 0.65 0.21 0.641 0.241
LOG_LREAL 1.052 0.30 3.25 0.95 0.73 0.21 0.733 0.223
LN_REAL 1 0.30 2.46 0.97 0.65 0.22 0.66 0.287
LN_LREAL 1.05 0.33 3.14 1.01 0.75 0.22 0.744 0.239
EXPT_REAL 1.568 0.36 3.75 1.29 0.88 0.31 0.988 0.246
EXPT_LREAL 1.114 0.39 3.35 1.31 0.72 0.30 0.727 0.277
EXP_REAL 0.91 0.29 2.26 0.97 0.61 0.23 0.612 0.254
EXP_LREAL 0.966 0.34 2.85 1.1 0.76 0.23 0.698 0.232
PID
PIDISA 2.862 2.54 6.80 6.14 1.52 1.43 1.74 1.468
PIDIND 2.701 2.46 6.83 6.16 1.51 1.39 1.784 1.495
Range
RANGE_INT 1.424 0.62 3.57 2.09 0.85 0.47 1.055 0.615
RANGE_DINT 1.341 0.57 3.28 1.85 0.85 0.47 0.952 0.463
RANGE_DWORD 1.363 0.59 3.39 1.84 0.85 0.47 0.911 0.482
Timers
ONDTR 1.918 1.52 4.91 3.81 1.11 0.83 1.104 0.807
OFDT 1.756 1.56 4.70 4.22 1.03 0.87 1.027 0.838
TMR 1.797 1.58 4.69 4.21 1.04 0.88 1.031 0.838
TOF 2.986 1.951 7.8 4.7 1.8 1.2 1.803 1.107
TON 2.262 1.912 7.4 4.5 1.8 1.1 1.357 1.108
TP 2.312 1.909 7.5 4.5 1.8 1.2 1.422 1.11
Counters
UPCTR 1.851 1.69 4.24 4.28 0.96 0.92 0.899 0.907
DNCTR 1.668 1.68 4.20 4.23 0.94 0.93 0.903 0.896

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Control
JUMPN 0.021 0.06 0.29 0.13 0.02 0.01 0.134 0.01
FOR/NEXT 0.482 0.22 1.40 0.70 0.23 0.18 0.256 0.167
MCRN/ENDMCRN
0.212 0.21 0.64 0.65 0.06 007 0.1 0.146
Combined
SWITCH_POS 0.787 0.28 1.96 0.91 0.57 0.21 0.549 0.185
DOIO 78.972 0.41 58.32 1.32 38.72 0.30 16.97 0.29
DOIO with ALT 79.187 0.41 58.17 1.28 38.67 0.33 16.947 0.305
DRUM_SEQ 2.68 2.20 6.74 5.42 1.63 1.30 1.71 1.266
SCAN_SET_IO 138.471 0.797 155.02 1.87 111.81 0.50 39.488 0.394
SUSIO 0.797 0.14 1.93 0.38 0.49 0.11 0.514 0.094
COMM_REQ 221.447 0.39 219.48 1.51 133.87 0.36 136.466 0.362
CALL/RETURN
2.907 0.17 7.23 0.44 1.83 0.09 1.853 0.088
(C Block)
CALL/RETURN (LD) 2.859 0.13 7.50 0.42 1.73 0.10 1.853 0.106
CALL/RETURN
1.85 0.12 4.92 0.41 1.22 0.11 1.288 0.087
(Parameterized Block)
Bus66
BUS_RD_BYTE 16.228 0.75 20.16 2.35 7.41 0.68 1.02 0.589
BUS_RD_WORD 16.189 0.73 20.67 2.46 7.48 0.71 1.07 0.64
BUS_RD_DWORD 16.383 0.72 20.80 2.43 7.55 0.70 1.032 0.613
BUS_WRT_BYTE 12.34 0.70 20.94 2.59 6.19 0.70 1.944 0.589
BUS_WRT_WORD 12.478 0.71 20.76 2.49 6.17 0.69 1.956 0.593
BUS_WRT_DWORD 12.489 0.73 21.09 2.49 6.24 0.69 1.957 0.601
BUS_RMW_BYTE 17.5 0.83 21.72 2.67 7.96 0.78 1.385 0.682
BUS_RMW_WORD 17.647 0.83 21.01 2.69 7.95 0.79 1.358 0.659
BUS_RMW_DWORD 17.484 0.79 21.20 2.71 7.96 0.78 1.429 0.665
BUS_TS_BYTE 17.284 0.61 19.07 2.05 7.80 0.50 1.309 0.511
BUS_TS_WORD 17.378 0.59 20.16 2.09 7.66 0.51 1.254 0.512
66 Results will vary with how quickly the module responds to bus cycles. Because of this, incremental times do not appear in
the RX3i Incremental Times tables.

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
SVC_REQ
#1 2.179 0.26 6.57 1.02 1.34 0.18 1.54 0.217
#2 2.523 0.27 6.35 1.01 1.57 0.21 1.809 0.176
#3 1.746 0.25 4.80 0.92 0.98 0.18 1.15 0.142
#4 1.735 0.24 4.83 0.98 0.99 0.19 1.14 0.158
#5 1.697 0.24 4.90 0.92 0.97 0.17 1.158 0.153
#6 1.688 0.25 4.58 0.97 0.99 0.19 1.099 0.18
#7 3.661 0.32 8.64 1.12 1.95 0.20 2.022 0.182
#8 10.343 0.28 6.82 1.01 3.14 0.20 3.306 0.192
#9 1.76 0.28 4.53 1.03 1.06 0.20 1.192 0.195
#10 2.487 0.28 7.09 1.04 1.72 0.20 1.586 0.205
#11 1.751 0.28 4.25 1.03 1.07 0.20 1.166 0.195
#12 0.931 0.28 2.37 1.03 0.60 0.20 0.708 0.187
#13 1.438 0.25 4.56 1.09 0.89 0.18 0.903 0.177
#14 178.204 0.23 436.25 1.11 124.34 0.19 117.072 0.161
#15 1.13 0.36 2.72 1.10 0.60 0.34 0.712 0.308
#16 1.739 0.33 4.39 1.01 1.04 0.21 1.058 0.202
#17 1.235 0.32 2.95 0.90 0.85 0.19 0.732 0.196
#18 31.168 0.33 112.51 1.05 41.61 0.21 25.369 0.181
#19 1.618 0.32 4.30 1.05 0.88 0.20 0.929 0.173
#20 4.997 0.33 17.78 1.05 4.59 0.21 4.614 0.173
#21 16.058 0.34 35.02 1.00 9.48 0.21 9.344 0.173
#22 1.07 0.29 2.82 1.00 0.65 0.20 0.735 0.175
#23 36.224 0.29 118.94 1.03 32.49 0.21 24.019 0.188
#24 2.003 0.30 4.66 0.98 1.05 0.20 0.665 0.173
#25 1.181 0.29 3.00 0.98 0.74 0.20 0.746 0.167
NA NA
#26 NA NA NA NA NA NA
1.73 1.28
NA NA
1.75 1.29
NA NA
1.96 1.30
#32 9.788 0.30 12.88 1.31 5.03 0.20 4.824 0.178
NA NA
1.77 1.27
#50 1.655 0.29 4.48 1.05 1.00 0.21 1.116 0.157
#51 1.67 0.29 4.54 0.99 1.05 0.20 1.154 0.157
563.14367 84.1667
#56 0.39 0.97 22.73 0.21 1396.47 0.159
17.41368 84.1668
9167.40367 17558.3367
#57 0.39 0.97 13970.00 0.21 6131.71 0.159
8.7968 17558.3368
67 Initial execution.
68 Subsequent executions.

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
PACMotion
MC_AbortTrigger 167.406 5.322 150.954 12.762 50.35 3.01 50.35 3.01
MC_CamFileRead 22.997 14.603 63.861 44.001 13.84 7.05 13.84 7.05
MC_CamFileWrite 25.499 15.152 52.938 27.52 12.02 4.7 12.02 4.7
MC_CamIn 185.117 10.867 169.563 30.988 102.8 4.86 102.8 4.86
MC_CamOut 134.517 4.580 99.325 10.812 47.49 2.8 47.49 2.8
MC_CamTableDeselect 104.051 8.023 116.468 18.343 60.09 3.56 60.09 3.56
MC_CamTableSelect 126.359 7.399 138.508 21.01 75.97 3.77 75.97 3.77
MC_DelayedStart 122.332 7.167 141.552 20.164 76.77 3.22 76.77 3.22
MC_DigitalCamSwitch 229.067 39.904 227.174 70.804 152.59 4.32 152.59 4.32
MC_DL_Activate 102.622 19.693 101.982 26.656 50.63 3.39 50.63 3.39
MC_DL_Configure 182.666 8.776 200.857 23.556 130 3.72 130 3.72
MC_DL_Delete 92.780 10.230 116.745 21.212 49.57 3.14 49.57 3.14
MC_DL_Get 102.580 9.065 109.414 35.919 61.29 3.16 61.29 3.16
MC_GearIn 170.551 7.611 165.344 23.176 91.03 4.34 91.03 4.34
MC_GearInPos 115.852 7.790 134.393 21.776 70.31 4.43 70.31 4.43
MC_GearOut 89.184 4.646 100.441 10.64 46.91 3.2 46.91 3.2
MC_Halt 152.450 7.622 155.891 19.243 82.5 4.11 82.5 4.11
MC_Home 117.432 7.715 134.787 19.626 71.45 3.77 71.45 3.77
MC_JogAxis 114.385 11.529 128.661 32.746 65.18 3.38 65.18 3.38
MC_LibraryStatus 91.545 8.275 105.757 16.573 48.78 3.33 48.78 3.33
MC_ModuleReset 95.198 6.322 103.803 17.462 83.73 3.15 83.73 3.15
MC_MoveAbsolute 175.661 7.095 174.49 18.321 99.53 3.95 99.53 3.95
MC_MoveAdditive 159.697 7.495 168.611 19.947 89.47 4.14 89.47 4.14
MC_MoveRelative 159.920 7.440 158.805 19.89 90.54 3.83 90.54 3.83
MC_MoveVelocity 162.556 7.650 159.625 22.839 65.66 3.98 65.66 3.98
MC_Phasing 170.154 7.646 167.904 21.544 95.11 4.6 95.11 4.6
MC_Power 37.423 37.284 130.954 130.871 24.49 20.06 24.49 20.06
MC_ReadActualPosition 39.528 1.656 36.643 4.216 18.61 0.73 18.61 0.73
MC_ReadActualVelocity 39.183 1.644 36.072 4.262 18.36 0.74 18.36 0.74
MC_ReadAnalogInput 45.623 1.988 51.211 4.74 22.38 1.17 22.38 1.17
MC_ReadAnalogOutput 59.744 3.318 47.314 7.89 22.16 1.67 22.16 1.67
MC_ReadAxisError 36.524 2.813 38.94 6.712 17.17 1.32 17.17 1.32
MC_ReadBoolParameter 32.953 2.761 37.485 6.408 14.85 1.57 14.85 1.57
MC_ReadBoolParameters 31.974 3.435 37.936 7.479 15 1.64 15 1.64
MC_ReadDigitalInput 38.895 3.226 36.186 7.043 14.63 1.67 14.63 1.67
MC_ReadDigitalOutput 44.757 2.485 47.597 6.216 17.07 1.58 17.07 1.58
MC_ReadDwordParameters 31.176 3.467 36.61 7.079 14.54 1.58 14.54 1.58
MC_ReadEventQueue 108.594 9.296 123.594 22.352 60.86 4.33 60.86 4.33
MC_ReadParameter 45.460 3.075 58.045 9.839 22.87 1.58 22.87 1.58
MC_ReadParameters 43.504 4.021 47.405 8.012 20.72 1.61 20.72 1.61
MC_ReadStatus 32.917 3.436 41.05 7.167 16.01 4.12 16.01 4.12

Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
MC_ReadTorqueCommand 39.639 1.720 36.657 4.36 18.51 0.73 18.51 0.73
MC_Reset 93.936 5.851 103.623 16.885 48.37 2.99 48.37 2.99
MC_SetOverride 107.928 11.412 116.23 36.465 62.21 3.81 62.21 3.81
MC_SetPosition 98.519 7.638 116.732 23.002 54 3.97 54 3.97
MC_Stop 99.332 6.130 112.185 16.24 56.38 3.6 56.38 3.6
MC_Superimposed 105.975 5.892 122.646 16.499 63.24 3.75 63.24 3.75
MC_SyncStart 103.035 6.320 122.121 17.198 60.23 3.1 60.23 3.1
MC_TouchProbe 173.373 7.268 160.243 18.934 56.11 3.32 56.11 3.32
MC_WriteAnalogOutput 134.439 8.041 112.994 21.111 53.53 3.36 53.53 3.36
MC_WriteBoolParameter 104.890 7.287 95.696 20.303 48.29 3.21 48.29 3.21
MC_WriteBoolParameters 131.228 8.106 106.974 22.215 57.41 3.23 57.41 3.23
MC_WriteDigitalOutput 96.338 8.259 116.644 23.822 52.99 4.27 52.99 4.27
MC_WriteDwordParameters 160.433 7.661 125.168 19.661 73.23 3.25 73.23 3.25
MC_WriteParameter 98.558 8.231 122.482 27.394 55.3 4.03 55.3 4.03
MC_WriteParameters 192.054 6.859 161.002 18.911 94.77 4.84 94.77 4.84

RX3i Incremental Times

An Increment time is shown for functions that can have variable length inputs.
Incremental time is added to the base function time for each addition to the length of an input
parameter. This time applies only to functions that can have varying input lengths (Search, Array
Moves, etc.)
Units:
 For table functions, increment is in units of length specified.
 For bit operation functions, increment is µs per bit.
 For data move functions, increment is in µs per unit.
CPE305 CPU320/
Instruction CPU310 CPU315
CPE310 CRU32069
Bit Operation
AND_WORD 0.04 0.12 0.02826 0.02463
AND_DWORD 0.06 0.16 0.3088 0.03789
OR_WORD 0.04 0.12 0.03 0.02472
OR_DWORD 0.06 0.16 0.03444 0.03798
XOR_WORD 0.04 0.12 0.02818 0.02478
XOR_DWORD 0.06 0.16 0.03424 0.03762
NOT_WORD 0.02 0.08 0.02011 0.01888
NOT_DWORD 0.04 0.12 0.02839 0.02799
MCMP_WORD 0.08 0.26 0.05934 0.055
MCMP_DWORD 0.09 0.29 0.06407 0.05919
SHL_WORD 0.07 0.17 0.0468 0.05032
SHL_DWORD 0.07 0.18 0.04381 0.04681
SHR_WORD 0.07 0.18 0.04883 0.03557
SHR_DWORD 0.09 0.19 0.0455 0.04718
BTST_WORD 0.00 0 0.00011 0.04332
BTST_DWORD 0.00 0 0.00046 0.03983
ROL_WORD 0.06 0.19 0.05071 0.03634
ROL_DWORD 0.07 0.17 0.03929 0.04152
ROR_WORD 0.06 0.16 0.0428 0.00012
ROR_DWORD 0.07 0.17 0.03992 0.00033
BPOS_WORD 0.32 0.76 0.17369 0.19574
BPOS_DWORD 0.72 1.69 0.38279 0.43922
Relational
EQ_DATA 0.0001 0.00019 0
Conversion
REAL_TO_UINT 0 0.00421 0
REAL_TO_DINT 0 0.00936 0
LReal_To_Real - - - 0

CPE305 CPU320/
CPE310 CRU32069
Data Move
MOVE_BIT 0.01 0.02 0.00412 0.00488
MOVE_DINT 0.02 0.04 0 0.0089
MOVE_INT 0.01 0.02 0 0
MOVE_UINT - - - 0.00439
MOVE_WORD 0.01 0.02 0.00968 0.0041
MOVE_DWORD 0.02 0.04 0.04613 0.00913
MOVE_REAL 0.02 0.04 0.0372 0.00951
MOVE_LREAL 0.03 0.09 0.01952 0.01928
MOVE_DATA 0.0002 0.00022 0
MOVE_DATA_EX 0.0002 0.00028 0
DATA_INIT_ASCII 0.00 0.01 0.00217 0.00304
DATA_INIT_COMM 0.01 0.02 0.00408 0.00398
DATA_INIT_DLAN - 0 0 0
DATA_INIT_DINT 0.01 0.04 0.00811 0.00812
DATA_INIT_DWORD 0.01 0.04 0.00817 0.00807
DATA_INIT_INT 0.01 0.02 0.00447 0.00432
DATA_INIT_REAL 0.01 0.04 0.00796 0.00822
DATA_INIT_LREAL 0.03 0.08 0.01584 0.01639
DATA_INIT_WORD 0.01 0.02 0.00439 0.00469
DATA_INIT_UINT 0.01 0.02 0.00391 0.00422
SWAP_WORD 0.04 0.19 0.00498 0.02921
SWAP_DWORD 0.06 0.16 0.00942 0.03614
BLKCLR_WORD 0.01 0.02 0.00568 0.00627
SHFR_BIT 0.02 0.04 0.01174 0.01241
SHFR_WORD 0.06 0.18 0.04529 0.03804
SHFR_DWORD 0.07 0.20 0.04751 0.04277
Data Table
SORT_INT 0.33 0.74 0.22253 0.2179
SORT_UINT 0.33 0.74 0.22237 0.21686
SORT_WORD 0.32 0.74 0.22243 0.21704
TBLRD_INT 0.00 0 -1E-05 0.00016
TBLRD_DINT 0.00 0 0.00012 0.00014
TBLWRT_INT 0.00 0 -0.0002 0.00003
TBLWRT_DINT 0.00 0 -0.0002 0.0002
FIFORD_INT 0.01 0.02 0.00432 0.00417
FIFORD_DINT 0.02 0.04 0.00927 0.0093
FIFOWRT_INT 0.00 -0.1333333 0.00011 0.00009
FIFOWRT_DINT 0.00 -1.1777778 -0.001 0.00001
LIFORD_INT 0.00 0.01111111 0.00021 0.00001
LIFORD_DINT 0.00 0.64444444 0.00021 0.00011
LIFOWRT_INT 0.00 -0.8666667 0.0001 0.00004
LIFOWRT_DINT 0.00 -0.8777778 4.4E-05 0.00001
LIFOWRT_DWORD 0.00 0.11111111 -0.0002 0.00001

CPE305 CPU320/
CPE310 CRU32069
Array
ARRAY_MOVE_BIT 0.01 0.02 0.00558 0.00538
ARRAY_MOVE_BYTE 0.00 0.01 0.0024 0.00207
ARRAY_MOVE_INT 0.01 0.02 0.00424 0.00407
ARRAY_MOVE_DINT 0.02 0.05 0.00961 0.00986
ARRAY_MOVE_WORD 0.01 0.02 0.0041 0.00442
ARRAY_MOVE_DWORD 0.02 0.04 0.00974 0.009
ARRAY_MOVE_UINT 0.01 0.02 0.00413 0.0038
SRCH_BYTE 0.02 0.07 0.01796 0.0173
SRCH_WORD 0.03 0.07 0.01828 0.01946
SRCH_DWORD 0.02 0.07 0.01507 0.01407
ARRAY_RANGE_DINT 0.19 0.54 0.13903 0.13582
ARRAY_RANGE_INT 0.18 0.52 0.13471 0.13199
ARRAY_RANGE_UINT 0.18 0.52 0.13647 0.13241
ARRAY_RANGE_WORD 0.18 0.52 0.13578 0.13282
ARRAY_RANGE_DWORD 0.19 0.56 0.14221 0.13928
PACMotion
MC_ReadBoolParameters 16.000 14.000 7.62 –
MC_ReadDwordParameters 30.000 28.000 12.34 –
MC_ReadParameters 40.000 38.000 19.42 –
MC_WriteBoolParameters 22.000 10.000 0.48 –
MC_WriteDwordParameters 40.000 34.000 1.4 –
MC_WriteParameters 45.000 42.000 1.34 –

A-2.4 RX7i Instruction Times

CPE030 CPE040
CPE010 CPE020 CRE02070
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Bit Operation
AND_WORD 3.42 1.58 1.49 0.69 1.71 0.81 1.29 0.58 0.43 0.20
AND_DWORD 3.64 1.58 1.58 0.70 1.67 0.81 1.31 0.58 0.44 0.20
OR_WORD 3.58 1.71 1.56 0.76 1.72 0.90 1.28 0.59 0.43 0.20
OR_DWORD 3.55 1.66 1.54 0.73 1.71 0.83 1.44 0.60 0.48 0.20
XOR_WORD 3.42 1.57 1.48 0.69 1.73 0.80 1.29 0.61 0.48 0.25
XOR_DWORD 3.55 1.58 1.54 0.70 1.66 0.81 1.32 0.58 0.44 0.25
NOT_WORD 2.73 1.38 1.17 0.59 1.39 0.72 1.02 0.40 0.34 0.13
NOT_DWORD 2.81 1.44 1.21 0.62 1.44 0.75 1.07 0.41 0.35 0.14
MCMP_WORD 5.69 2.43 2.44 1.04 2.64 1.14 2.51 1.08 0.85 0.36
MCMP_DWORD 5.69 2.32 2.50 1.00 2.63 1.11 2.48 1.03 0.82 0.34
SHL_WORD 4.46 2.62 1.89 1.11 2.31 1.25 1.92 1.00 0.64 0.34
SHL_DWORD 4.53 2.73 1.92 1.56 2.31 1.28 1.90 0.98 0.63 0.32
SHR_WORD 4.64 2.59 1.96 1.09 2.45 1.24 1.98 0.98 0.66 0.32
SHR_DWORD 4.51 2.65 1.91 1.12 2.11 1.29 1.90 1.01 0.63 0.34
ROL_WORD 2.95 1.61 1.27 0.69 1.43 0.82 1.17 0.61 0.39 0.20
ROL_DWORD 3.27 1.61 1.39 0.70 1.46 0.84 1.07 0.59 0.36 0.20
ROR_WORD 2.93 1.52 1.25 0.66 1.45 0.82 1.11 0.57 0.39 0.19
ROR_DWORD 2.92 1.58 0.68 0.68 1.41 0.81 1.20 0.57 0.40 0.19
BTST_WORD 3.23 1.45 0.58 0.5 1.49 0.75 1.16 0.63 0.39 0.21
BTST_DWORD 3.29 1.37 1.41 0.5 1.48 0.72 1.19 0.63 0.40 0.19
BSET_WORD 2.62 1.43 1.12 0.61 1.17 0.72 0.97 0.48 0.31 0.16
BSET_DWORD 2.59 1.40 1.13 0.60 1.16 0.71 0.97 0.48 0.32 0.16
BCLR_WORD 2.51 1.36 1.08 0.59 1.20 0.72 0.97 0.48 0.31 0.16
BCLR_DWORD 2.49 1.33 1.07 0.57 1.16 0.70 0.97 0.47 0.32 0.16
BPOS_WORD 3.63 1.24 1.66 0.64 1.84 0.76 1.51 0.56 0.50 0.19
BPOS_DWORD 3.29 1.18 1.97 0.62 2.18 0.75 1.78 0.48 0.59 0.18
Relational
CMP_INT 3.51 1.25 1.50 0.54 1.45 0.60 1.58 0.52 0.53 0.17
CMP_DINT 3.86 1.32 1.66 0.57 1.51 0.66 1.61 0.52 0.53 0.17
CMP_REAL 3.65 1.30 1.57 0.56 1.52 0.62 0.53 0.53 0.54 0.1
CMP_LREAL 4.08 1.25 1.75 0.53 1.64 0.59 1.84 0.52 0.61 0.18
CMP_UINT 4.15 1.35 1.78 0.58 1.48 0.63 1.62 0.53 0.54 0.17
EQ_DATA 10.13 2.02 2.91 1.05 2.81 0.94 2.82 1.08 1.27 0.66
EQ_DINT 2.45 1.15 1.06 0.50 1.08 0.60 1.05 0.41 0.35 0.13
EQ_INT 2.49 1.14 1.07 0.50 1.04 0.58 1.04 0.47 0.35 0.16

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
EQ_LREAL 3.00 1.27 1.28 0.54 1.25 0.64 1.27 0.47 0.43 0.17
EQ_REAL 2.61 1.12 1.12 0.49 1.03 0.60 1.15 0.43 0.37 0.14
EQ_UINT 2.33 1.11 1.00 0.48 1.01 0.59 1.04 0.40 0.35 0.13
NE_INT 2.34 1.13 1.01 0.49 0.97 0.60 1.03 0.42 0.34 0.14
NE_DINT 2.56 1.34 1.10 0.55 1.10 0.66 1.08 0.43 0.36 0.14
NE_UINT 2.43 1.18 1.04 0.51 1.00 0.62 1.08 043 0.36 0.14
NE_REAL 2.65 1.18 1.14 0.51 1.05 0.61 1.13 0.40 0.38 0.13
NE_LREAL 2.93 1.17 1.26 0.51 1.24 0.60 1.29 0.42 0.44 0.15
GT_INT 2.50 1.14 1.08 0.49 1.05 0.60 1.05 0.40 0.35 0.13
GT_DINT 2.42 1.15 1.04 0.50 1.04 0.59 1.05 0.40 0.35 0.13
GT_REAL 2.60 1.11 1.11 0.48 1.02 0.58 1.13 0.40 0.38 0.13
GT_LREAL 2.90 1.15 1.27 0.50 1.21 0.60 1.28 0.43 0.43 0.15
GT_UINT 2.39 1.10 1.02 0.48 0.99 0.59 1.06 0.40 0.35 0.13
GE_INT 2.48 1.13 1.07 0.50 1.04 0.59 1.08 0.40 0.36 0.13
GE_DINT 2.57 1.19 1.08 0.51 1.08 0.62 1.07 0.41 0.36 0.14
GE_REAL 2.59 1.10 1.11 0.48 1.02 0.58 1.13 0.43 0.38 0.14
GE_LREAL 2.92 1.17 0.51 0.6 1.25 0.62 1.24 0.41 0.43 0.14
GE_UINT 2.42 1.19 1.04 0.51 1.01 0.63 1.06 0.41 0.35 0.13
LT_INT 2.54 1.22 1.09 0.50 1.06 0.61 1.05 0.42 0.35 0.14
LT_DINT 2.58 1.27 1.11 0.54 1.09 0.66 1.08 0.43 0.36 0.14
LT_REAL 2.66 1.18 1.14 0.51 1.04 0.72 1.13 0.39 0.38 0.13
LT_LREAL 2.90 1.15 1.24 0.50 1.22 0.59 1.29 0.43 0.43 0.14
LT_UINT 2.48 1.15 1.03 0.49 1.02 0.60 1.04 0.0 0.35 0.13
LE_INT 2.48 1.14 1.07 0.49 1.03 0.60 1.08 0.40 0.36 0.13
LE_DINT 2.46 1.15 1.05 0.50 1.04 0.59 1.05 0.40 0.35 0.13
LE_UINT 2.41 1.17 1.03 0.50 1.04 0.61 1.02 0.41 0.34 0.13
LE_REAL 2.68 1.14 1.16 0.49 1.02 0.60 1.10 0.40 0.37 0.13
LE_LREAL 2.89 1.15 1.24 0.49 12.1 0.58 1.26 0.39 0.43 0.14
Conversion
BCD-4 to INT 2.11 1.11 0.90 0.48 0.95 0.62 0.83 0.34 0.27 0.14
DINT to INT 2.18 1.15 0.94 0.48 0.81 0.56 0.85 0.33 0.28 0.14
UINT to INT 1.95 1.14 0.84 0.49 0.81 0.55 0.77 0.31 0.25 0.14
BCD-8 to DINT 3.00 1.10 1.29 0.47 1.02 0.58 0.94 0.32 0.30 0.14
INT to DINT 2.19 1.13 0.94 0.49 0.78 0.55 0.75 0.33 0.23 0.15
UINT to DINT 2.17 1.18 0.94 0.51 0.92 0.57 0.79 0.32 0.27 0.13
INT to UINT 1.88 1.12 0.81 0.48 0.76 0.56 0.80 0.35 0.27 0.14
DINT to UINT 2.15 1.11 0.93 0.48 0.83 0.58 0.72 0.33 0.24 0.14
BCD-4 to UINT 2.13 1.08 0.93 0.48 0.94 0.65 0.81 0.35 0.27 0.14
INT to BCD-4 2.24 1.12 0.94 0.48 0.92 0.56 0.95 0.35 0.27 0.15
UINT to BCD-4 2.26 1.17 0.97 0.50 0.93 0.56 1.07 0.36 0.33 0.15
DINT to BCD-8 3.15 1.08 1.35 0.47 1.00 0.60 0.91 0.34 0.31 0.14

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
REAL_TO_INT 2.75 1.20 1.18 0.52 1.02 0.58 0.99 0.34 0.33 0.14
REAL_TO_UINT 2.67 1.18 1.15 0.51 1.01 0.57 0.95 0.34 0.31 0.14
REAL_TO_LREAL 2.26 1.01 0.97 0.43 0.88 0.55 0.88 0.37 0.29 0.12
REAL_TO_DINT 3.06 1.14 1.32 0.49 1.05 0.57 0.98 0.34 0.31 0.14
INT_TO_REAL 2.17 1.12 0.93 0.48 0.77 0.56 0.73 0.36 0.24 0.15
UINT_TO_REAL 2.19 1.17 0.94 0.50 0.77 0.57 0.83 0.37 0.28 0.15
DINT_TO_REAL 2.43 1.14 1.04 0.49 0.84 0.60 0.75 0.34 0.27 0.14
DINT_TO_LREAL 2.24 1.01 0.96 0.44 0.85 0.73 0.85 0.42 0.28 0.13
REAL_TRUN_INT 2.22 1.37 0.87 0.49 0.83 0.59 0.56 0.13 0.26 0.11
REAL_TRUN_DINT 2.42 1.13 1.09 0.55 0.89 0.64 0.70 0.13 0.30 0.11
DEG_TO_RAD_REAL 2.39 1.11 1.03 0.48 0.83 0.57 0.87 0.35 0.29 0.12
DEG_TO_RAD_LREAL 2.34 1.05 1.01 0.44 0.92 0.52 0.98 0.34 033 0.11
RAD_TO_DEG_REAL 2.34 1.16 1.03 0.48 0.94 0.57 0.86 0.35 0.29 0.12
RAD_TO_DEG_LREAL 2.33 1.06 1.00 0.44 0.93 0.52 0.98 0.34 0.33 0.11
BCD-4 to REAL 2.42 1.09 1.04 0.48 0.99 0.64 0.89 0.34 0.28 0.14
BCD-8 to REAL 3.07 1.14 1.32 0.49 1.11 0.55 0.98 0.31 0.31 0.14
LREAL_TO_DINT 2.85 1.00 1.21 0.43 1.07 0.73 1.10 0.42 0.36 0.13
LREAL_TO_REAL 2.35 1.09 1.01 0.47 0.87 0.58 0.83 0.35 0.2 0.12
Data Move
BLKCLR 2.13 1.16 0.91 0.50 1.09 0.62 0.73 0.34 0.24 0.11
BITSEQ 3.90 3.93 1.63 1.64 1.76 1.74 1.50 1.59 0.50 0.53
MOVE_BIT 2.93 1.53 1.22 0.63 1.47 0.81 1.06 0.41 0.35 0.14
MOVE_DINT 2.23 1.44 0.92 0.58 1.07 0.75 0.78 0.26 0.3 0.13
MOVE_INT 2.27 1.47 0.94 0.60 1.06 0.75 0.79 0.42 0.26 0.14
MOVE_DWORD 2.31 1.51 0.96 0.62 1.10 0.77 0.81 0.41 0.26 0.14
MOVE_LREAL 2.74 1.43 1.15 0.61 1.56 0.77 0.95 0.42 0.31 0.14
MOVE_REAL 2.18 1.39 0.91 0.57 1.07 0.74 0.78 0.40 0.26 0.14
MOVE_UINT 2.3 1.2 1.0 0.5 - - - - - -
MOVE_WORD 2.25 1.45 0.93 0.59 1.04 0.76 0.80 0.43 0.27 0.14
MOVE_DATA 9.81 3.22 2.72 1.02 2.73 0.95 2.54 1.12 1.11 0.69
MOVE_DATA_EX 12.25 4.22 3.53 1.15 3.35 1.27 2.85 1.44 1.27 0.80
MOVE_TO_FLAT 12.25 4.22 3.53 1.15 3.35 1.27 2.85 1.44 1.27 0.80
MOVE_FROM_FLAT 12.25 4.22 3.53 1.15 3.35 1.27 2.85 1.44 1.27 0.80
BLKMOV_WORD 2.73 2.26 1.17 0.97 1.23 1.14 1.13 0.91 0.38 0.30
BLKMOV_DINT 3.02 2.36 1.30 1.01 1.35 1.10 1.19 0.90 0.40 0.30
BLKMOV_INT 2.71 2.26 1.16 0.97 1.21 1.13 1.11 0.88 0.37 0.30
BLKMOV_DWORD 2.97 2.31 1.28 0.99 1.33 1.08 1.19 0.87 0.40 0.29
BLKMOV_REAL 3.01 2.34 1.29 1.00 1.35 1.10 1.18 0.89 0.39 0.29
BLKMOV_UINT 2.71 2.21 1.17 0.96 1.23 1.15 1.12 0.87 0.37 0.29
DATA_INIT_ASCII 0.91 1.39 0.40 0.60 0.76 0.77 0.30 0.44 0.10 0.15
DATA_INIT_COMM 1.05 1.36 0.46 0.60 0.84 0.78 0.37 0.43 0.11 0.15

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
DATA_INIT_DLAN 1.33 1.49 0.58 0.64 0.94 0.83 0.39 0.45 0.14 0.15
DATA_INIT_DINT 0.92 1.37 0.40 0.59 0.78 0.79 0.30 0.45 0.10 0.15
DATA_INIT_DWORD 0.98 1.39 0.41 0.60 0.79 0.81 0.32 0.45 0.11 0.15
DATA_INIT_INT 0.95 1.41 0.42 0.61 0.81 0.81 0.31 0.46 0.10 0.15
DATA_INIT_REAL 0.90 1.36 0.40 0.59 0.77 0.78 0.30 0.44 0.18 0.22
DATA_INIT_LREAL 0.98 1.33 0.42 0.57 0.79 0.78 0.36 0.48 0.11 0.16
DATA_INIT_WORD 0.90 1.41 0.40 0.61 0.78 0.79 0.30 0.44 0.10 0.15
DATA_INIT_UINT 0.90 1.37 0.39 0.59 0.78 0.79 0.31 0.46 0.10 0.15
SWAP_WORD 2.83 1.41 1.18 0.57 1.34 0.74 0.96 0.42 0.32 0.13
SWAP_DWORD 2.59 1.43 1.08 0.58 1.29 0.73 0.93 0.42 0.31 0.14
SHFR_BIT 6.35 2.94 2.74 1.27 2.92 1.22 2.37 1.08 0.79 0.36
SHFR_WORD 7.08 4.90 3.04 2.11 3.25 2.16 3.27 2.46 1.09 0.82
SHFR_DWORD 7.62 5.03 3.27 2.1 3.39 2.24 3.29 2.43 1.10 0.81
Data Table
SORT_INT 36.57 1.40 15.66 0.60 15.94 0.75 16.50 0.44 5.50 0.15
SORT_UINT 36.48 1.40 15.66 0.60 15.90 0.75 16.50 0.44 5.49 0.15
SORT_WORD 36.51 1.39 15.61 0.60 15.90 0.76 16.46 0.44 5.49 0.15
TBLRD_INT 4.14 1.75 1.79 0.77 2.03 0.97 1.52 0.73 0.49 0.25
TBLRD_DINT 4.19 1.77 1.79 0.76 2.02 0.97 1.47 0.69 0.48 0.22
TBLWRT_INT 4.06 1.74 1.73 0.74 1.72 0.84 1.59 0.74 0.53 0.25
TBLWRT_DINT 4.00 1.70 1.72 0.72 1.70 0.84 1.60 0.72 0.53 0.23
FIFORD_INT 3.92 1.69 1.68 0.71 1.67 0.72 1.58 0.66 0.53 0.22
FIFORD_DINT 3.89 1.71 1.65 0.73 1.65 0.68 1.56 0.66 0.52 0.22
FIFOWRT_INT 3.17 1.46 1.35 0.64 1.41 0.75 1.23 0.49 0.42 0.18
FIFOWRT_DINT 3.10 1.43 1.33 0.62 1.39 0.72 1.25 0.51 0.42 0.17
LIFORD_INT 3.77 1.73 1.60 0.72 1.62 0.72 1.49 0.66 0.50 0.22
LIFORD_DINT 3.77 1.74 1.60 0.72 1.63 0.72 1.48 0.66 0.49 0.22
LIFOWRT_INT 3.18 1.49 1.35 0.63 1.43 0.72 1.25 0.51 0.42 0.17
LIFOWRT_DINT 3.08 1.42 1.33 0.61 1.41 0.72 1.33 0.68 0.42 0.18
LIFOWRT_DWORD 3.15 1.47 1.35 0.63 1.43 0.72 1.25 0.53 0.41 0.18
Array
ARRAY_MOVE_BIT 4.10 2.16 1.76 0.92 1.94 1.06 1.57 0.75 0.52 0.25
ARRAY_MOVE_BYTE 3.12 1.97 1.34 0.84 1.45 0.95 1.25 0.82 0.42 0.27
ARRAY_MOVE_WORD 3.19 2.10 1.37 0.91 1.45 1.05 1.26 0.81 0.42 0.27
ARRAY_MOVE_DINT 3.10 2.04 1.33 0.85 1.41 0.97 1.24 0.81 0.41 0.2
ARRAY_MOVE_DWORD 3.07 1.97 1.32 0.84 1.42 0.95 1.24 0.81 0.42 0.27
ARRAY_MOVE_INT 3.23 2.12 1.39 0.92 1.47 1.03 1.26 0.79 0.42 0.26
ARRAY_MOVE_UINT 3.10 1.96 1.33 0.84 1.53 1.07 1.37 1.14 0.42 0.28
SRCH_BYTE 4.07 1.86 1.74 0.79 2.11 0.91 1.74 0.87 0.58 0.29
SRCH_WORD 3.90 1.86 1.70 0.82 1.83 0.91 1.90 0.83 0.63 0.27
SRCH_DWORD 4.57 1.91 1.96 0.82 1.92 0.96 1.78 0.78 0.59 0.25

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
ARRAY_RANGE_WORD 4.14 1.89 1.80 0.81 1.90 0.96 1.70 0.69 0.57 0.23
ARRAY_RANGE_DWORD 4.61 1.88 1.99 0.80 2.06 0.97 1.70 0.65 0.57 0.22
ARRAY_RANGE_DINT 4.39 1.89 1.88 0.81 1.97 0.99 1.81 0.69 0.61 0.23
ARRAY_RANGE_INT 4.22 1.84 1.81 0.79 1.92 0.96 1.84 0.68 0.61 0.23
ARRAY_RANGE_UINT 4.44 1.82 1.76 0.78 1.91 0.96 1.68 0.66 0.56 0.22
Math
ADD_INT 2.11 1.31 0.91 0.58 0.87 0.66 1.00 0.49 0.33 0.16
ADD_DINT 2.56 1.34 1.12 0.58 0.97 0.67 0.90 0.46 0.30 0.15
ADD_REAL 2.75 1.32 1.19 0.56 0.96 0.66 0.92 0.50 0.30 0.17
ADD_LREAL 2.82 1.30 1.21 0.54 1.09 0.62 1.28 0.53 0.43 0.18
ADD_UINT 2.23 1.42 0.93 0.57 0.96 0.68 0.90 0.51 0.29 0.16
SUB_INT 2.13 1.35 0.91 0.55 0.87 0.65 0.87 0.49 0.29 0.16
SUB_DINT 2.50 1.35 1.09 0.56 0.94 0.65 0.90 0.49 0.30 0.16
SUB_REAL 2.46 1.29 1.13 0.63 1.08 0.85 1.08 0.69 0.30 0.17
SUB_LREAL 1.26 1.26 1.26 0.54 1.10 0.63 1.37 0.53 0.47 0.17
MUL_INT 2.25 1.42 0.93 0.57 0.90 0.65 0.89 0.49 0.30 0.16
MUL_DINT 2.53 1.34 1.10 0.59 0.95 0.69 1.05 0.49 0.35 0.17
MUL_MIXED 2.36 1.31 1.00 0.58 0.89 0.66 0.90 0.51 0.30 0.16
MUL_REAL 2.57 1.39 1.08 0.56 0.93 0.65 0.88 0.48 0.29 0.17
MUL_LREAL 2.87 1.21 1.24 0.52 1.19 0.61 1.28 0.54 044 0.18
MUL_UINT 2.14 1.35 0.92 0.55 0.90 0.65 0.87 0.49 0.29 0.16
DIV_INT 2.25 1.29 0.99 0.58 0.98 0.68 0.90 0.48 0.30 0.16
DIV_DINT 2.71 1.35 1.16 0.60 0.99 0.73 0.93 0.48 0.30 0.16
DIV_REAL 2.70 1.43 1.11 0.56 0.96 0.68 1.07 0.49 0.36 0.16
DIV_LREAL 2.86 1.20 1.23 0.52 1.14 0.61 1.33 0.53 0.45 0.18
DIV_MIXED 2.70 1.35 1.15 0.56 1.11 0.65 0.97 0.49 0.33 0.16
MOD_INT 2.23 1.38 0.95 0.57 0.93 0.66 0.91 0.48 0.30 0.16
MOD_DINT 2.65 1.35 1.12 0.56 1.09 0.79 1.09 0.69 0.30 0.17
MOD_UINT 2.19 1.29 1.01 0.63 0.99 0.74 0.99 0.50 0.33 0.17
ABS_INT 2.01 1.21 0.99 0.63 0.93 0.60 0.84 0.38 0.29 0.13
ABS_DINT 2.44 1.17 1.05 0.50 0.96 0.60 0.84 0.37 0.28 0.12
ABS_REAL 2.45 1.14 1.05 0.49 0.87 0.59 0.90 0.35 0.30 0.12
ABS_LREAL 2.58 1.07 1.11 0.46 0.97 0.53 0.98 0.35 0.33 0.11
SCALE_INT 3.54 1.84 1.57 0.83 1.82 0.91 1.23 0.54 0.48 0.24
SCALE_DINT 2.98 1.79 1.37 0.89 1.61 1.03 1.00 0.51 0.41 0.24
SCALE_UINT 2.89 1.78 1.27 0.81 1.39 0.98 0.98 0.5 0.40 0.25
SQRT_INT 2.39 1.13 1.05 0.50 1.08 0.57 0.99 0.35 0.32 0.12
SQRT_DINT 3.37 1.18 1.44 0.51 1.28 0.58 1.08 0.35 0.36 0.12
SQRT_REAL 2.54 1.23 1.09 0.54 0.91 0.61 0.85 0.37 0.29 0.13
SQRT_LREAL 2.36 1.09 1.00 0.46 0.92 0.53 0.99 0.32 0.34 0.12

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Trigonometric
SIN_REAL 3.02 1.11 1.26 0.48 0.97 0.57 0.95 0.35 0.32 0.12
SIN_LREAL 3.05 1.10 1.31 0.48 1.13 0.55 1.16 0.35 0.39 0.11
COS_REAL 2.96 1.11 1.22 0.48 0.97 0.57 1.06 0.35 0.36 0.12
COS_LREAL 2.88 1.09 1.18 0.47 1.10 0.56 1.17 0.35 0.39 0.11
TAN_REAL 3.02 1.11 1.26 0.48 1.02 0.57 0.96 0.35 0.32 0.12
TAN_LREAL 2.89 1.09 1.23 0.476 1.14 0.56 1.32 0.36 0.44 0.11
ASIN_REAL 3.29 1.20 1.41 0.52 1.26 0.63 1.13 0.35 0.38 0.12
ASIN_LREAL 3.14 10.5 1.32 0.45 1.33 0.54 1.37 0.35 0.46 0.12
ACOS_REAL 3.29 1.20 1.41 0.52 1.26 0.63 1.13 0.35 0.38 0.12
ACOS_LREAL 3.10 1.04 1.32 0.45 1.28 0.53 1.36 0.54 0.47 0.12
ATAN_REAL 3.26 1.25 1.37 0.54 1.02 0.65 1.05 0.37 0.35 0.12
ATAN_LREAL 2.87 1.04 1.20 0.46 1.08 0.53 1.18 0.35 0.40 0.12
Logarithmic
LOG_REAL 2.90 1.16 1.25 0.50 1.03 0.59 1.04 0.35 0.35 0.12
LOG_LREAL 2.88 1.03 1.21 0.43 1.11 0.52 1.19 0.38 0.39 0.12
LN_REAL 2.84 1.13 1.22 0.50 1.01 0.58 1.06 0.37 0.35 0.12
LN_LREAL 2.83 1.07 1.22 0.46 1.16 0.53 1.19 0.34 0.40 0.11
EXPT_REAL 4.13 1.41 1.77 0.63 1.52 0.72 1.39 0.40 0.46 0.13
EXPT_LREAL 3.03 1.33 1.30 0.57 1.35 0.71 1.24 0.42 0.42 0.14
EXP_REAL 2.70 1.16 1.16 0.50 0.97 0.59 1.00 0.37 0.33 0.12
EXP_LREAL 2.71 1.04 1.16 0.45 1.08 0.54 1.25 0.34 0.42 0.12
PID
PIDISA 6.92 6.18 2.98 2.66 3.17 2.79 2.66 2.44 0.89 0.81
PIDIND 6.86 6.13 2.97 2.66 3.17 2.79 2.65 2.43 0.88 0.81
Range
RANGE_INT 3.27 1.89 1.40 0.81 1.35 0.91 1.40 0.87 0.53 0.35
RANGE_DINT 3.26 1.94 1.40 0.83 1.36 0.92 1.41 0.81 0.47 0.27
RANGE_DWORD 3.40 2.02 0.87 0.87 1.46 1.01 1.42 0.82 0.47 0.27
Timers
ONDTR 4.79 3.70 2.01 1.54 2.11 1.57 1.82 1.38 0.61 0.46
OFDT 4.57 4.08 1.92 1.71 1.97 1.76 1.71 1.45 0.57 0.49
TMR 4.52 4.04 1.92 1.71 2.05 1.79 1.71 1.45 0.58 0.49
TOF 9.6 4.9 4.1 2.1 NA NA 3.9 2.0 1.3 0.6
TON 9.5 4.8 4.0 2.0 NA NA 3.9 2.0 1.3 0.6
TP 9.8 4.8 4.2 2.1 NA NA 3.9 2.0 1.3 0.6
Counters
UPCTR 4.13 4.17 1.74 1.76 1.85 1.86 1.59 1.53 0.53 0.51
DNCTR 4.16 4.18 1.73 1.75 1.84 1.86 1.54 1.53 0.52 0.51

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
Control
JUMPN 0.21 0.26 0.06 0.06 0.12 0.09 0.12 0.08 0.04 0.03
FOR/NEXT 1.51 0.72 0.64 0.31 0.90 0.47 0.56 0.26 0.19 0.09
MCRN/ENDMCRN 0.68 0.68 0.28 0.29 0.28 0.28 0.10 0.10 0.03 0.03
Combined
SWITCH_POS 1.91 1.02 0.82 0.44 0.87 0.59 0.60 0.13 0.26 0.12
DOIO 32.78 1.45 17.60 0.63 6.50 0.76 14.94 0.23 9.374 0.15
DOIO with ALT 32.56 1.48 17.47 0.63 6.47 0.75 14.91 0.32 9.36 0.18
DRUM_SEQ 6.98 5.70 2.99 2.45 3.21 2.67 2.63 2.21 0.88 0.74
SCAN_SET_IO 55.21 1.92 32.65 0.83 33.69 0.86 30.40 0.76 22.84 0.25
SUSIO 2.14 0.45 0.92 0.20 1.12 0.35 0.68 0.06 0.30 0.05
COMMREQ 117.27 1.60 73.25 0.73 73.30 0.90 73.42 0.59 65.23 0.22
CALL/RETURN (LD) 7.27 0.51 3.11 0.23 3.58 0.42 2.79 0.06 0.99 0.05
CALL/RETURN 7.84 0.56 2.07 0.23 2.33 0.42 1.94 0.05 0.72 0.06
(Parameterized Block)
CALL/RETURN (C Block) 7.24 0.55 3.05 0.25 3.29 0.45 2.91 0.06 1.04 0.04
Bus71
BUS_RD_BYTE 21.30 2.42 10.87 1.04 1.94 1.18 8.56 1.00 5.24 0.33
BUS_RD_DWORD 21.96 2.51 11.16 1.09 2.13 1.25 8.14 1.00 5.17 0.33
BUS_RD_WORD 21.44 2.54 10.98 1.10 2.11 1.29 8.14 1.01 5.17 0.33
BUS_WRT_BYTE 23.76 2.72 11.62 1.17 3.10 1.26 9.46 0.96 5.76 0.32
BUS_WRT_DWORD 23.52 2.56 11.53 1.10 3.11 1.30 9.48 0.95 5.77 0.32
BUS_WRT_WORD 23.51 2.55 11.54 1.10 3.09 1.28 9.46 0.95 5.76 0.32
BUS_RMW_BYTE 24.44 2.78 12.97 1.19 2.41 1.37 10.28 1.12 6.58 0.37
BUS_RMW_DWORD 24.73 2.82 12.80 1.21 2.23 1.35 10.06 1.13 6.48 0.38
BUS_RMW_WORD 24.00 2.77 12.54 1.19 2.41 1.38 10.25 1.12 6.54 0.38
BUS_TS_BYTE 23.23 2.36 12.23 1.01 2.19 1.28 9.93 0.87 6.45 0.29
BUS_TS_WORD 22.98 2.31 12.14 0.99 2.06 1.15 9.96 0.91 6.5 0.28
71 Results will vary with how quickly the module responds to bus cycles. Because of this, incremental times do not appear in
the RX7i Incremental Times tables.

CPE030 CPE040
CRE03070 CRE04070
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Instruction
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
(μs)
SVC_REQ
#1 6.40 1.20 2.75 0.52 2.78 0.79 2.10 0.1 0.77 0.10
#2 6.45 1.04 2.76 0.45 2.74 0.67 2.67 0.35 0.89 0.12
#3 4.94 1.15 2.10 0.49 2.45 0.74 1.39 0.09 0.53 0.10
#4 4.93 1.12 2.09 0.47 2.49 0.74 1.42 0.08 0.54 0.10
#5 4.99 1.19 2.12 0.50 2.49 0.77 1.44 0.10 0.55 0.10
#6 4.62 1.12 1.96 0.47 1.97 0.74 1.46 0.13 0.55 0.11
#7 8.81 1.17 3.67 0.51 3.72 0.78 3.30 0.34 1.05 0.10
#8 7.08 1.07 3.82 0.46 4.00 0.66 3.92 0.34 2.53 0.12
#9 4.12 1.06 1.76 0.46 1.95 0.66 1.83 0.32 0.60 0.11
#10 6.81 1.10 3.02 0.45 3.04 0.67 2.71 0.35 0.91 0.12
#11 4.26 1.12 1.84 0.48 1.90 0.68 1.82 0.34 0.61 0.11
#12 2.25 1.01 0.97 0.44 1.12 0.66 1.02 0.33 0.34 0.11
#13 4.55 1.24 1.96 0.51 2.78 0.75 1.32 0.08 0.51 0.09
#14 424.95 1.16 188.07 0.48 203.10 0.76 197.46 0.09 71.70 0.10
#15 3.18 1.14 1.38 0.49 1.25 0.51 0.94 0.49 0.31 0.16
#16 4.57 1.20 1.94 0.52 2.06 0.70 1.71 0.35 0.57 0.12
#17 2.94 1.13 1.24 0.49 NA NA 1.27 0.32 035 0.04
#18 112.36 1.18 48.09 0.51 48.20 0.69 69.36 0.33 23.12 0.11
#19 4.61 1.19 1.97 0.51 2.71 0.66 1.51 0.33 0.50 0.11
#20 18.92 1.19 8.09 0.51 7.58 0.65 7.69 0.33 2.56 0.11
#21 36.19 1.23 18.15 0.52 17.77 0.66 13.29 0.32 7.15 0.18
#22 2.86 1.23 1.23 0.53 1.28 0.63 1.19 0.36 0.39 0.12
#23 119.63 1.19 51.22 0.52 54.68 0.65 54.33 0.33 18.01 0.11
#24 150.79 1.17 77.38 0.51 1.26 0.65 58.55 0.32 34.67 0.11
#25 3.03 1.21 1.30 0.52 1.25 0.66 1.30 0.35 0.43 0.121
#26 NA NA NA NA 3.20 2.85 NA NA NA NA
2.65 2.13 0.88 0.71
2.90 2.16 0.97 0.72
3.30 2.17 1.18 0.73
#32 54.47 1.21 48.97 0.50 NA NA 47.36 0.30 45.12 0.12
NA NA NA NA
2.93 2.11 0.98 0.70
#50 4.48 1.18 1.90 0.51 1.92 0.63 1.76 0.33 0.59 0.11
#51 4.60 1.13 1.98 0.49 1.9 0.64 2.27 0.80 0.59 0.10
#56 82.65 1.23 42.66 0.52 44.03 0.78 29.75 0.32 10.26 0.11
#57 19331.60 1.21 19017.30 0.52 18848.20 0.78 13585 0.32 13540 0.11

RX7i Incremental Times

An Increment time is shown for functions that can have variable length inputs.
Incremental time is added to the base function time for each addition to the length of an input
parameter. This time applies only to functions that can have varying input lengths (Search, Array
Moves, etc.)
Units:
 For table functions, increment is in units of length specified.
 For bit operation functions, increment is µs per bit.
 For data move functions, µs per unit.
CPE030/ CPE040/
Instruction CPE010 CPE020 CRE020
CRE030 CRE040
Bit Operation
AND_WORD 0.11572 0.04957 0.05006 0.04553 0.01517
AND_DWORD 0.15567 0.5996 0.6002 0.5095 0.1766
OR_WORD 0.11857 0.05078 0.05039 0.04842 0.01543
OR_DWORD 0.15729 0.06743 0.067 0.05626 0.01859
XOR_WORD 0.1156 0.04983 0.05022 0.04613 0.01532
XOR_DWORD 0.15568 0.06691 0.06669 0.05623 0.0187
NOT_WORD 0.07498 0.03249 0.03248 0.03343 0.01117
NOT_DWORD 0.11946 0.0513 0.05011 0.04666 0.01556
MCMP_WORD 0.26347 0.11279 0.11288 0.0969 0.03228
MCMP_DWORD 0.28671 0.12257 0.1226 0.10587 0.03523
SHL_WORD 0.17382 0.07444 0.0745 0.07786 0.02594
SHL_DWORD 0.18306 0.07839 0.07842 0.07287 0.02428
SHR_WORD 0.18397 0.07872 0.0785 0.08088 0.02686
SHR_DWORD 0.18868 0.08229 0.08062 0.07612 0.02537
BTST_WORD 0.00014 -6E-05 -3E-05 0.00026 0.0001
BTST_DWORD 0.00098 3.3E-05 0.00042 0.00071 0.00024
ROL_WORD 0.1944 0.08303 0.08316 0.08447 0.02821
ROL_DWORD 0.16617 0.07114 0.0714 0.06493 0.02161
ROR_WORD 0.15893 0.06819 0.06809 0.0715 0.02382
ROR_DWORD 0.16617 0.0737 0.07399 0.06634 0.0221
BPOS_WORD 0.76048 0.32549 0.32584 0.28894 0.09634
BPOS_DWORD 1.68499 0.72159 0.7231 0.6378 0.21258
Relational
EQ_DATA 0.00029 0.00004 0.00021 0.00051 2.6E-05
Conversion
REAL_TO_UINT 0 0 0 0 0
REAL_TO_DINT 0 0 0 0 0

CPE030/ CPE040/
CRE030 CRE040
Data Move
MOVE_BIT 0.01958 0.00821 0.00813 0.00919 0.00307
MOVE_DINT 0.04398 0.01884 0.01943 0.0157 0.00533
MOVE_INT 0.02002 0.00833 0.00863 0.00694 0.00231
MOVE_DWORD 0.04447 0.01904 0.0193 0.01584 0.00528
MOVE_LREAL 0.08989 0.03854 0.03878 0.03242 0.01083
MOVE_UINT 0.02 0.01 0.02 0.03 0.01
MOVE_WORD 0.02046 0.00876 0.00839 0.00704 0.00234
MOVE_REAL 0.04464 0.01914 0.01946 0.01572 0.00523
MOVE_DATA 0.00021 0.00015 0.00015 -0.0002 7.2E-05
MOVE_DATA_EX 0.0011 6.9E-05 6.9E-05 3.2E-05 2.1E-05
DATA_INIT_ASCII 0.01057 0.00459 0.00844 0.00686 0.00101
DATA_INIT_COMM 0.01982 0.00851 0.01724 0.01381 0.00229
DATA_INIT_DLAN 0 0 0 0 0
DATA_INIT_DINT 0.04034 0.01713 0.00878 0.00754 0.00464
DATA_INIT_DWORD 0.04032 0.01728 0.0084 0.00649 0.00461
DATA_INIT_INT 0.01952 0.00837 0.01714 0.01392 0.00253
DATA_INIT_REAL 0.03997 0.01711 0 0 0.00453
DATA_INIT_LREAL 0.08051 0.03457 0.03434 0.02621 0.00902
DATA_INIT_WORD 0.02071 0.00888 0.01718 0.01343 0.0025
DATA_INIT_UINT 0.01971 0.00844 0.00849 0.00732 0.00226
SWAP_WORD 0.18858 0.08076 0.08082 0.07672 0.02551
SWAP_DWORD 0.15904 0.06834 0.06833 0.0613 0.0204
BLKCLR 0.02528 0.01094 0.01097 0.0101 0.00334
SHFR_BIT 0.04324 0.01827 0.01867 0.02013 0.00666
SHFR_WORD 0.16054 0.06598 0.06848 0.07023 0.0251
SHFR_DWORD 0.19577 0.08384 0.08263 0.08009 0.02663
Data Table
SORT_INT 0.74431 0.31843 0.31607 0.37118 0.12369
SORT_UINT 0.74589 0.31942 0.317 0.3717 0.12383
SORT_WORD 0.74476 0.31838 0.31632 0.37082 0.12369
TBLRD_INT 0.00096 -0.0001 -9E-05 -0.0005 -0.0002
TBLRD_DINT -0.0002 -0.0001 0.00016 -0.0001 -9E-05
TBLWRT_INT 0.00048 0.00018 0.00023 1.1E-05 -4E-05
TBLWRT_DINT -0.0009 -0.0004 -0.0003 -0.0002 -6E-05
FIFORD_INT 0.1939 0.00816 0.00866 0.00698 0.00234
FIFORD_DINT 0.04449 0.01866 0.0188 0.01529 0.00511
FIFOWRT_INT 0.00058 0.00047 0.00046 -3E-05 -1E-05
FIFOWRT_DINT -0.0007 -0.0003 -0.0004 0 -1E-05
LIFORD_INT 0.00022 0.00031 0.00042 -7E-05 1.1E-05
LIFORD_DINT 0.00087 0.00037 0.00044 0.00027 8.9E-05
LIFOWRT_INT 0.00037 0.00041 0.00042 0.00011 6.7E-05
LIFOWRT_DINT -0.0006 -0.0003 -0.0003 0.00019 0
LIFOWRT_DWORD 0.00101 0.00029 0.00028 -0.0002 -7E-05

CPE030/ CPE040/
CRE030 CRE040
Array
ARRAY_MOVE_BIT 0.01967 0.00841 0.00863 0.00914 0.00304
ARRAY_MOVE_BYTE 0.00957 0.00387 0.00379 0.00358 0.00119
ARRAY_MOVE_INT 0.02002 0.00857 0.00857 0.0067 0.00223
ARRAY_MOVE_DINT 0.04762 0.02019 0.02021 0.0164 0.00547
ARRAY_MOVE_WORD 0.02063 0.00883 0.00878 0.00643 0.00211
ARRAY_MOVE_DWORD 0.04489 0.01922 0.01913 0.01529 0.00511
ARRAY_MOVE_UINT 0.02014 0.00863 0.00922 0.00687 0.00231
SRCH_BYTE 0.07277 0.03143 0.03112 0.03001 0.0101
SRCH_WORD 0.07492 0.03186 0.03177 0.02826 0.0094
SRCH_DWORD 0.06664 0.02854 0.02841 0.02641 0.00882
ARRAY_RANGE_DINT 0.5422 0.232 0.23221 0.23434 0.07808
ARRAY_RANGE_INT 0.51968 0.22242 0.22204 0.22419 0.07467
ARRAY_RANGE_UINT 0.51902 0.22204 0.22200 0.22429 0.07492
ARRAY_RANGE_WORD 0.52001 0.22294 0.22249 0.2255 0.07511
ARRAY_RANGE_DWORD 0.55802 0.23898 0.23903 0.23764 0.07917

A-3 Overhead Sweep Impact Times

This section contains overhead timing information for the PACSystems CPUs. This information can be
used in conjunction with the estimated logic execution time to predict sweep times for the CPUs. The
information in this section is made up of a base sweep time plus sweep impact times for each of the
CPU models. The predicted sweep time is computed by adding the sweep impact time(s), the base
sweep, and the estimated logic execution time.
See sample calculation for estimating sweep times at Sweep Calculations (in µS).
The following components make up the total sweep time:
 Programmer communications sweep impact
 I/O Scan and fault sweep impact
 Ethernet Global Data sweep impact
 Intelligent Option Module (LAN modules) sweep impact
 I/O interrupt performance and sweep impact
 Timed interrupt performance and sweep impact

A-3.1 Base Sweep Times

Base sweep time is the time for an empty _MAIN program block to execute, with no configuration
stored and none of the windows active. The following table gives the base sweep times in
microseconds (µs) for each CPU model.
Family Model Run I/O enabled (µs) Run outputs disabled (µs)
CPU31072 1086 1076
CPU315
180 176
CPU32072
CRU32072 198 194

RX3i
CPE305
426 424
CPE310
CPE330
CPE400
CPE010 457 449
CPE020
182 180
CRE020
RX7i73
CPE030
169 165
CRE030
CPE040
77.4 74.8
CRE040
72 Base sweep time calculated with RUN/STOP switch, single ETM.

73 Base sweep time with I/O enabled includes time to scan the status bits for the Ethernet daughterboard.

The following diagram shows the differences between the full sweep phases and the base sweep
phases.
Base Sweep vs. Full Sweep Phases
Base Sweep Full Sweep
<START OF SWEEP> <START OF SWEEP>
Sweep Housekeeping Sweep Housekeeping
 
NULL Input Scan 74 Input Scan 74
 
Program Logic Execution EGD Consumption Scan 75
 
NULL Output Scan 74 Program Logic Execution
 
 Output Scan 74
 
 EGD Production Scans 75
 
 Poll for Missing I/O Modules 76
 
 Controller Communications Window
 
 Backplane Communications Window
<END OF SWEEP> <END OF SWEEP>
For the base sweep, if there is no configuration, the input and output scan phases of the sweep are
NULL (i.e., check for configuration and then end). The presence of a configuration with no I/O modules
or intelligent I/O modules (GBC) has the same effect. The logic execution time is not zero in the base
sweep. The time to execute the empty _MAIN program is included so that you only need to add the
estimated execution times of the functions actually programmed. The base sweep also assumes no
missing I/O modules. The lack of programmer attachment means that the Controller
Communications Window is never opened. The lack of intelligent option modules means that the
Backplane Communications Window is never opened.
74 If I/O is suspended, the input and output scans are skipped.

75 If no Ethernet Global Data (EGD) exchanges are configured, the consumption and production scans are skipped.
76 Polling for missing I/O modules only occurs if a Loss of ... fault has been logged for an I/O module.

A-3.2 What the Sweep Impact Tables Contain

In some tables, functions are shown as asynchronously impacting the sweep. This means that there
is not a set phase of the sweep in which the function takes place. For instance, the scanning of all I/O
modules takes place during either the input or output scan phase of the CPU’s sweep. However, I/O
interrupts are totally asynchronous to the sweep and will interrupt any function currently in progress.
The communication functions (with the exception of the high priority programmer requests) are all
processed within one of the two windows in the sweep (the Controller Communications Window and
the Backplane Communications Window). Sweep impact times for the various service requests are all
minimum sweep impact times for the defined functions, where the window times have been adjusted
so that no time slicing (limiting) of the window occurs in a given sweep. This means that, as much as
possible, each function is completed in one occurrence of the window (between consecutive logic
scans). The sweep impact of these functions can be spread out over multiple sweeps (limited) by
adjusting the window times to a value lower than the documented sweep impact time. For the
programmer, the default time is 10 ms; therefore, some of the functions listed in that section will
naturally time slice over successive sweeps.

A-3.3 Programmer Sweep Impact Times

The following table shows nominal programmer sweep impact times in microseconds (µs).
RX3i RX7i
Sweep CPU315
Description CPE020 CPE030 CPE040
Impact Item CPU310 CPU320 CPE330 CPE010
CRE020 CRE030 CRE0400
(µs) CRU320 (µs) (µs)
(µs) (µs) (µs)
(µs)
The time required to open the
Programmer Window but not
process any requests. The
Programmer
programmer is attached 2.9 0.2 1.95 0.21 0.2 0.2
window
through an Ethernet
connection; no reference
values are being monitored.
The sweep impact to refresh
the reference table screen.
(The %R table was used as
the example.) Mixed table
Reference display impacts are slightly
table larger. The sweep impact 4.9 0.29 1.2 0.33 0.26 0.29
monitor may not be continuous,
depending on the sweep time
of the CPU and the speed of
the host of the programming
software.
The sweep impact to refresh
the editor screen when
monitoring ladder logic. The
times given in the table are
Editor for a logic screen containing
4.1 0.31 1.41 0.35 0.31 0.31
monitor one contact, two coils, and
eleven registers. As with the
reference table sweep
impact, the impact may not
be continuous.

A-3.4 I/O Scan and I/O Fault Sweep Impact

The I/O scan sweep impact has two parts, Local I/O and Genius I/O. The equation for computing I/O
scan sweep impact is:
I/O Scan Sweep Impact = Local Scan Impact + Genius I/O Scan
Impact
Sweep Impact of Local I/O Modules

The I/O scan of I/O modules is impacted as much by location and reference address of a module as it
is by the number of modules. The I/O scan has several basic parts.
I/O Scan Description
Rack Setup Time Each expansion rack is selected separately because of the addressing of
expansion racks on the VME bus. This results in a fixed overhead per
expansion rack, regardless of the number of modules in that rack.
Per Module Setup Time Each Local I/O module has a fixed setup scan time.
Byte Transfer Time The actual transfer of bytes is much faster for modules located in the main
rack than for those in expansion racks. The byte transfer time differences
will be accounted for by using different times for I/O modules in the main
rack versus expansion racks.
In addition, analog input expander modules (the same as Genius blocks) have the ability to be
grouped into a single transfer as long as consecutive reference addresses are used for modules that
have consecutive slot addresses. Each sequence of consecutively addressed modules is called a
scan segment. There is a time penalty for each additional scan segment.
RX7i I/O Module Types
Type Part Numbers
Discrete Input Type I IC697MDL240, IC697MDL241, IC697MDL251, IC697MDL640,
(16 point, 14 point) IC697MDL671
Discrete Input Type II IC697MDL250, IC697MDL252, IC697MDL253, IC697MDL254,
(32 point) IC697MDL651, IC697MDL652, IC697MDL653, IC697MDL650,
IC697MDL654
Discrete Output Type I IC697MDL340, IC697MDL341, IC697MDL740, IC697MDL940
(16 point, 12 point)
Discrete Output Type II IC697MDL350, IC697MDL750, IC697MDL752, IC697MDL753
(32 point)
Analog Input Type I IC697ALG230
(8 Channel)
Analog Input Type II IC697ALG440, IC697ALG441
(16 Channel with 8 channel AI
module)
Analog Output IC697ALG320
(4 channel)

RX7i Module Sweep Impact Times

The following table provides sweep impact times for modules in the Main rack and in an expansion
(Exp) rack. The base case provides the overhead a single module in the rack. The increment (Inc)
refers to the overhead for each similar module that is added to the same rack.
Model CPE010 (µs) CPE020/CRE020 (µs) CPE030/CRE030 (µs) CPE040/CRE040 (µs)
Rack Main Exp Main Exp Main Exp Main Exp
Impact Base Inc Base Inc Base Inc Base Inc Base Inc Base Inc Base Inc Base Inc
Discrete In.
35.8 9.3 29.6 30.2 9.5 6.3 10.2 13.8 10.2 10.6 14.4 16.5 5.1 4.1 6.0 9.8
Type - I
Discrete In.
35.1 13.4 34.3 31.9 12.1 6.6 14.5 10.9 10.5 6.4 14.4 16.5 5.7 4.6 9.9 13.7
Type - II
Discrete Out.
38.9 14.8 33.1 33.0 12.9 6.2 11.7 14.4 11.5 6.4 10.8 12.9 6.0 4.5 6.3 10.0
Type - I
Discrete Out.
40.2 15.8 36.9 37.2 13.6 7.3 16.2 18.1 11.7 6.9 14.5 17.2 7.0 5.7 10.4 13.9
Type - II
Per fault
106.254 — 111.01 — 44.608 — 45.716 — — — — — — — — —
message
Analog In.
49.5 26.3 71.6 54.7 19.2 11.7 40.3 35.3 16.3 11.9 38 34 9.9 8.7 31.3 30.6
Type 1
Analog Exp –
80.1 15.2 133.9 58.6 33.5 12.6 96.8 56.4 30.1 13.7 94.9 57 22.4 12.6 87.0 55.4
Type 2
Analog Out. 49.9 25.1 63.2 39.6 16.6 11.2 29.3 24.7 15.2 10.2 27 22.3 8.4 7.1 20.1 19.2
Per fault
86.207 — 86.7 — 40.135 60.762 — — — — — — — — —
message
Analog In.
74.0 54.3 N/A N/A 44.9 38.2 N/A N/A 42.8 38.1 N/A N/A 35.8 32.2 N/A N/A
VAL132
Analog In.
VME-3125A
Analog In.
VAL264
Analog In.
VME-3122A
Analog In.
VRD008
Analog Out.
VAL301
Discrete In.
VDD100
Discrete In.
50.5 29.2 NA NA 24.5 18.1 N/A N/A 22.5 18.7 N/A N/A 14.7 14.7 N/A N/A
VME-1182A
Discrete Out.
VDQ120
Discrete Out.
VDR151

RX3i I/O Module Types

Type Part Numbers
Discrete Input, 16 point IC694MDL240, IC694MDL241, IC694MDL645, IC694MDL646
Discrete Input - Smart Digital Input,
IC695MDL664
16 point
Discrete Input, 32 point IC694MDL654, IC694MDL655, IC694MDL654
Discrete Output, 8 point IC694MDL330, IC694MDL732, IC694MDL930, IC694MDL940
Discrete Output, 16 point and 12 point IC694MDL340, IC694MDL341, IC694MDL740, IC694MDL741
Discrete Output – Smart Digital
IC695MDL765
Output. 16 point
IC694MDL350, IC694MDL340, IC694MDL742, IC694MDL752,
Discrete Output, 32 point
IC694MDL753, IC694MDL940
Discrete Output, 32 point IC694MDL758
Discrete In/Out, 8 point IC693MDR390, IC693MAR590
Analog Input, 4 Channel IC695ALG220, IC694ALG221
Analog Input, 6 Channel IC695ALG106
Analog Input, 12 channel IC695ALG112
Analog Input, 16 Channel IC694ALG222, IC694ALG223
Analog Output, 2 channel IC694ALG390, IC694ALG391
Analog Mixed Input/Output IC694LG442
Analog Input with Diagnostics IC694ALG232, IC694ALG233
Analog Mixed Input/Output with
IC694ALG542
Diagnostics

RX3i I/O Module Sweep Impact Times

The following table provides sweep impact times for modules in the Main rack and in an expansion
(Exp) rack. The base case provides the overhead for a single module in the rack. The increment (Inc)
refers to the overhead for each similar module that is added to the same rack. To estimate sweep
impact for modules in a remote rack, multiply the time in the main rack by 6:
main rack base time × 6 = approximate sweep impact in remote rack
CPU310 (µs) CPU315/CPU320 (µs) CPE305/CPE310 (µs)

Main Rack Exp Main Rack Exp Main Rack Exp
Base Inc Base Inc Base Inc Base Inc Base Inc Base Inc
Discrete Input 16 point 57.1 41.4 87.6 74.4 37.4 34.6 68.2 66.3 – – – –
Discrete Input 16 point
24.6 21.6 NA NA – – NA NA – – – –
(Smart Digital Input – IC695MDL664)
Discrete Input 32 point 78.4 59.7 105.9 96.1 56.2 55.3 86.1 85.7 – – – –
Discrete Output 8 point 61.0 40.3 84.3 74.9 35.6 34.7 64.5 65.5 – – – –
Discrete Output 16 point
24.8 21.4 NA NA – – NA NA – – – –
(Smart Digital Output – IC695MDL765)
Discrete Output 32 point (IC694MDL758) – – – – 128.6 123.7 220.9 216.0 193.1 – 288.5 –
Discrete Mixed
104.5 85.7 167.0 151.7 72.2 68.9 132.3 131.2 – – – –
8 point in/ 8 point out
Analog In/Out 4 channel 114.9 99.0 142.7 132.0 93.7 92.5 124.8 123.3 – – – –
Analog Input 16 channel 427.7 407.1 538.8 538.0 385.3 378.8 499.9 499.3 – – – –
Analog Output 2 channel 98.3 80.8 154.4 143.4 69.7 66.8 129.1 128.3 – – – –
Analog Input 6 channel, IC695ALG106 92.9 73.4 N/A N/A 51.6 51.0 N/A N/A – – – –
Analog Input 12 channel, IC695ALG112 111.7 94.8 N/A N/A 66.8 58.7 N/A N/A – – – –
Universal Analog
90.3 77.2 N/A N/A 50.9 45.7 N/A N/A – – – –
IC695ALG600
Analog Input 8 channel
84.4 68.3 N/A N/A 43.3 39.8 N/A N/A – – – –
IC695ALG608
Analog Input 16 channel
99.5 82.6 N/A N/A 56.3 55.6 N/A N/A – – – –
IC695ALG616
Analog Output 4 channel
122.0 101.8 N/A N/A 54.6 48.3 N/A N/A – – – –
IC695ALG704
Analog Output 8 channel
121.6 103.3 N/A N/A 54.7 49.6 N/A N/A – – – –
IC695ALG708

Worksheet A: I/O Module Sweep Time

The following form can be used for computing I/O module sweep impact. The calculation contains
times for analog input expanders that are either grouped into the same scan segment as the
preceding module or are grouped in a separate new scan segment. The sweep impact times of I/O
Modules can be found at RX7i Module Sweep Impact Times and RX3i I/O Module Sweep Impact Times.
Number of expansion racks ______

Sweep impact per expansion rack x ______ = ______
Number of discrete I/O modules—main rack ______
Sweep impact per discrete I/O module—main rack x ______ = ______
Number of discrete I/O modules—expansion rack ______
Sweep impact per discrete I/O module—expansion rack x ______ = ______
Number of analog input base and output modules—main rack ______
Sweep impact per analog input base and output module—main rack x ______ = ______
Number of analog input expander modules (same segment)—main rack ______
Sweep impact per analog input expander module (same segment)—main rack x ______ = ______
Number of analog input expander modules (new segment)—main rack ______
Sweep impact per analog input expander module (new segment)—main rack x ______ = ______
Number of analog input base and output modules—expansion rack ______
Sweep impact per analog input base and output module—expansion rack x ______ = ______
Number of analog input base and output modules (same segment)—exp. rack ______
Sweep impact per analog input base and output module (same seg.)—exp. rack x ______ = ______
Number of analog input base and output modules (new segment)—exp. rack ______
Sweep impact per analog input base and output module (new seg.)—exp. rack x ______ = ______
Predicted I/O Module Sweep Impact ______

Note: If point faults are enabled, substitute the corresponding times for point faults enabled.

Sweep Impact of Genius I/O and GBCs

For the sweep impact of Genius I/O and Genius Bus Controllers (GBC), there is a sweep impact for
each GBC, a sweep impact for each scan segment, and a transfer time (per word) sweep impact for
all I/O data.
The GBC sweep impact has three parts:
1. Sweep impact to open the System Communications Window. This is added only once when
the first intelligent option module (of which the GBC is one) is placed in the system.
2. Sweep impact to poll each GBC for background messages (datagrams). This part is an impact
for every GBC in the system.
Note: Both the first and second parts of the GBC’s sweep impact may be eliminated by closing the
Backplane Communications Window (setting its time to 0). This should only be done to reduce
scan time during critical phases of a process to ensure minimal scan time. Incoming
messages will timeout and COMM_REQs will stop working while the window is closed.
3. Sweep impact to scan the GBC. This results from the CPU notifying the GBC that its new
output data has been transferred, commanding the GBC to ready its input data, and
informing the GBC that the CPU has finished another sweep and is still in RUN Mode.
A scan segment for a Genius I/O block consists of consecutive memory locations starting from a
particular reference address. A new scan segment is created for each starting input or output
reference address. The time to process a single scan segment is higher for an input scan segment
than it is for an output scan segment. The scan segment processing is the same for analog, discrete,
and global data scan segments. Discrete data is transferred a byte at a time and takes longer to
complete the transfer than analog data, which is transferred a word at a time. Global data should be
counted as either discrete or analog, based on the memory references used in the source or
destination.
Sweep Impact Time of Genius I/O and GBCs
Note: Functions in bold type impact the sweep continuously. All other functions impact the sweep
only when invoked. Not all the timing information listed in the following table was available at
print time for this manual (the blank spaces).
CPU310 CPE010 CPE020 CPE030 CPE040
(µs) (µs) (µs) (µs) (µs)
Genius Bus Controller
open backplane communications window 30.0 24.0 4.0 4.0 1.0
per Genius Bus Controller polling for background messages 403.0 19.0 11.0 9.0 6.0
per Genius Bus Controller I/O Scan
Genius Bus Controller in the main rack 469.0 1.0 1.0 1.0 1.0
Genius Bus Controller in the expansion rack 683.0 11.0 7.0 6.9 1.0
Genius I/O Blocks
per I/O block scan segment 3.0 217.0 217.0 193.7 208.0
per I/O block scan segment w/point faults enabled 3.0 217.0 217.0 194.8 213.0
per byte discrete I/O data in the main rack 13.0 3.0 3.0 2.1 3.0
per byte discrete I/O data in expansion racks 16.0 8.0 5.0 4.2 4.0
per word analog I/O data in the main rack 24.0 5.0 4.0 4.0 5.0
per word analog I/O data in expansion racks 34.0 11.0 8.0 8.0 11.0

Worksheet B: Genius I/O Sweep Time

Use the following worksheet for predicting the sweep impact due to Genius I/O. The sweep impact
times can be found in Sweep Impact Time of Genius I/O and GBCs.
Open backplane communications window ______ = ______
______
GBC poll for background messages x ______ = ______
Number of GBCs
GBC I/O scan for the main rack ______
Number of GBCs in the main rack X ______ = ________
GBC I/O scan for the expansion rack ______
Number of GBCs in the expansion rack X ______ = ________
Input block scan segments—number of ______
I/O block scan segments—sweep impact x ______ = ______
Output block scan segments—number of ______
I/O block scan segments—sweep impact x ______ = ______
Bytes of discrete I/O data on GBCs—main rack ______
Sweep impact/bytes of discrete I/O data—main rack x ______ = ______
Bytes of discrete I/O data on GBCs—expansion racks ______
Sweep impact/bytes of discrete I/O data—expansion racks x ______ = ______
Words of analog I/O data on GBCs—main rack ______
Sweep impact/word analog I/O data—main rack x ______ = ______
Words of analog I/O data on GBCs—expansion racks ______
Sweep impact/word analog I/O data—expansion racks x ______ = ______
Predicted Genius I/O Scan Impact ______

A-3.5 Ethernet Global Data Sweep Impact

Note: Refer to the section A-3.6 for Embedded Ethernet interface on RX3i CPE305/310 specific information.
Depending on the relationship between the CPU sweep time and an Ethernet Global Data (EGD)
exchange’s period, the exchange’s data may be transferred every sweep or periodically after some
number of sweeps. Therefore, the sweep impact varies based on the number of exchanges that are
scheduled to be transferred during the sweep. All of the exchanges must be taken into account when
computing the worst-case sweep impact.
The Ethernet Global Data (EGD) sweep impact has two parts, Consumption Scan and Production
Scan:
EGD Sweep Impact = Consumption + Production
Scan Scan
This sweep impact should be taken into account when configuring the CPU constant sweep mode
and setting the CPU watchdog timeout.
Where the Consumption and Production Scans consist of two parts, exchange overhead and byte
transfer time:
Scan Time = Exchange Overhead + Byte Transfer Time
Exchange Overhead
Exchange overhead includes the setup time for each exchange that will be transferred during the
sweep. When computing the sweep impact, include overhead time for each exchange.
Note: The exchange overhead times in the table below were measured for a test-case scenario of
1400 bytes over 100 variables.
EGD Exchange Overhead Time
Embedded Ethernet
Rack-based Ethernet Module
Interface
(µs)
(µs)
CPE305/CPE310/CPE330 Consume / READ —77 —78
Produce / WRITE —77 —
CPU310/NIU001 Consume / READ NA 233.6
Produce / WRITE NA 480.6
CPU315/CPU320 Consume / READ NA 100.0
Produce / WRITE NA 195.1
CPE010 Consume / READ 184.3 238.2
Produce / WRITE 342.0 452.0
77 EGD Class 1 for this CPU type requires RX3i CPE310/CPE305 Firmware Release 8.30 or later. Prior to that, EGD was only
possible in RX3i via the ETM001 module. Refer to the section A-3.6.
78 Performance data not available for this release.

Data Transfer Time

Note: This is the time required to transfer the data between the CPU module and the rack-based
Ethernet module. EGD data transfer times do not increase linearly in relation to data size.
Please use the data values in the table below to estimate data transfer times.
Note: CPE modules do not need to use this table with respect their embedded Ethernet port, as
there is no transfer of data across the backplane related to EGD traffic.
Embedded Rack-based
CPU Data Size (Bytes) Direction Ethernet Ethernet Module
Interface (µS) (µS)
CPU310 1 Consume / READ NA 9.3
NIU00179 100 Consume / READ NA 51.8
200 Consume / READ NA 97.9
1 Produce / WRITE NA 6.5
CPE010 1 Consume / READ 4.1 8.8
100 Consume / READ 25.7 23.5
200 Consume / READ 49.0 38.6
256 Consume / READ 61.4 46.8
1 Produce / WRITE 1.9 8.8
100 Consume / READ 23.6 19.5
200 Consume / READ 46.3 34.9
256 Consume / READ 58.9 42.7
79 EGD performance is different on the IC695NIU001+ (versions-AAAA and later) compared to the IC695NIU001. In general,
consumed data exchanges with a size greater than 31 bytes will result in contributing less of a sweep time impact and
data exchanges with a size less than that will contribute slightly greater sweep impact. All produced exchanges on the
IC695NIU001+ will appear to have a slightly greater sweep impact when compared to the IC695NIU001.

Embedded Rack-based
CPU Data Size (Bytes) Direction Ethernet Ethernet Module
Interface (µS) (µS)
100 Consume / READ 25.8 18.7
200 Consume / READ 50.7 33.4
256 Consume / READ 60.1 40.4
100 Consume / READ 21.1 10.1
200 Consume / READ 43.5 31.4
256 Consume / READ 56.5 39.2
Worksheet C: Ethernet Global Data Sweep Time

Number of consumed exchanges __________________
_________________
Sweep impact per exchange x __________________ =
_
Number of data bytes in all of the

__________________
consumed exchanges
_________________
Sweep impact per consumed data byte x __________________ =
_
Number of produced exchanges __________________

_________________
Sweep impact per exchange x __________________ =
_
Number of data bytes in all of the

__________________
produced exchanges
_________________
Sweep impact per produced data byte x __________________ =
_
_________________
Predicted EGD Sweep Impact _


A-3.6 EGD Sweep Impact for Embedded Ethernet Interface on RX3i CPE
Models
Each EGD production or consumption will take about 200 µs regardless of size of exchange. For
Produced Exchanges on the embedded port you can think of it as a timed interrupt block that takes
200µs duration to execute each time it is triggered. For Consumed Exchanges on the embedded port
you can think of it as an I/O interrupt block that takes 200µs duration to execute each time the
remote unit sends an exchange and it is received on the embedded port.
It is important to note that this 200µs per exchange is not a simple ‘sweep impact’ time, rather per
execution of that exchange time, and depending on sweep time length and production period it may
occur more than one time per sweep.
Users configuring systems with EGD on an embedded Ethernet port should take care to make sure
that production and consumption time on the embedded Ethernet port is accounted for.
EGD Sweep impact for RX3i CPE305/310/330 Embedded Ethernet Interface:
The impact of EGD Exchanges configured on Embedded Ethernet Interface of RX3i CPE305/310 on
the Controller sweep can be reflected in two parameters:
1. 𝑻𝒐𝒕𝒂𝒍_𝑬𝒈𝒅𝑰𝒎𝒑𝒂𝒄𝒕𝑷𝒆𝒓𝑾𝑫𝑻_𝒎𝒔 : This is the total EGD impact per Watchdog Time period
configured in milliseconds (ms).
2. 𝑬𝒈𝒅𝑷𝒓𝒐𝒄𝒆𝒔𝒔𝒐𝒓𝑼𝒕𝒊𝒍𝒊𝒛𝒂𝒕𝒊𝒐𝒏 % : This is the percentage EGD processor utilization.
The formula for calculating these two parameters are shown below:
255
𝑊𝑑𝑡_𝑚𝑠
𝑇𝑜𝑡𝑎𝑙_𝐸𝑔𝑑𝐼𝑚𝑝𝑎𝑐𝑡𝑃𝑒𝑟𝑊𝐷𝑇_𝑚𝑠 = ∑ ( ×𝐸𝑥𝑐ℎ𝑎𝑛𝑔𝑒𝑃𝑟𝑒𝑠𝑒𝑛𝑡𝑛 ×0.2 00)
𝑃𝑒𝑟𝑖𝑜𝑑_𝑚𝑠𝑛
𝑛=1
𝑇𝑜𝑡𝑎𝑙_𝐸𝑔𝑑𝐼𝑚𝑝𝑎𝑐𝑡𝑃𝑒𝑟𝑊𝐷𝑇_𝑚𝑠
𝐸𝑔𝑑𝑃𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛_% = ( ) ×100
𝑊𝑑𝑡_𝑚𝑠
𝑊𝑑𝑡_𝑚𝑠 – Watchdog time configured in ms
𝑃𝑒𝑟𝑖𝑜𝑑_𝑚𝑠𝑛 – Exchange Period nth Exchange, as configured in ms (Production Period for production
exchanges and Consumption timeout for consumption exchanges
𝐸𝑥𝑐ℎ𝑎𝑛𝑔𝑒𝑃𝑟𝑒𝑠𝑒𝑛𝑡𝑛 – nth Exchange configured (value=1) or not configured (value=0)
It is recommended that the calculated 𝑬𝒈𝒅𝑷𝒓𝒐𝒄𝒆𝒔𝒔𝒐𝒓𝑼𝒕𝒊𝒍𝒊𝒛𝒂𝒕𝒊𝒐𝒏_% for a given EGD exchange

configuration and Watchdog period should be less than 50-55% for stable operation within
watchdog period without WDT elapse.
Note: The higher percentage of this parameter indicates that the EGD on Embedded Ethernet
interface could have a greater impact on CPU applications.

Example Calculation for EGD Utilization on CPE305/310/330:-

The watchdog time configured is 200ms for below table calculations:
SN EGD Exchange Type of Exchange Period Total_EgdImpactPerWDT_ms[n]
1 EGD Exchange#1 Producer 25 1.600
5 EGD Exchange#5 Consumer 30 1.333
Total_EgdImpactPerWDT_ms 9.600
EgdProcessorUtilization_% 4.800
Normal Sweep – EGD on RX3i CPE305/310/330 Embedded Ethernet Interface:

The following table shows the chart for setting up EGD exchanges on Embedded Ethernet for RX3i
CPE305/310 with a no sweep load and no network traffic. The table is a compilation of results based
on testing with two RX3i CPE310 Systems in which one is acting as the EGD Producer and the other is
acting as the EGD Consumer.
Production Period
Data size per Exchange Maximum Number of EGD
SN [Consumption Timeout*]
(Bytes) Exchanges ( Recommended)
(ms)
A 500 1400 254
B 500 200 255
C 500 10 255
D 300 1400 166
E 300 200 255
F 300 10 255
G 200 1400 109
H 200 200 255
I 200 10 255
J 100 1400 54
K 100 200 255
L 100 10 255
M 50 1400 27
N 50 200 127
O 50 10 230
P 30 1400 16
Q 30 200 75
R 30 10 136
S 20 1400 11
T 20 200 50
U 20 10 91

* Note: The previous table shows the value of Production Period (ms). Note that the Consumption
Timeout is set as twice the Production Period on the other consuming CPE310 node. For example, for
A, the Production Period for all the Producer exchanges is set to 500ms. This indicates that the
Consumption Timeout for all of the consumer exchanges on the consuming node is set to 1000ms
(twice the production period).
The following are important points to be considered when configuring EGD exchanges on Embedded
Ethernet Interface.
1. The recommended values in the given table should be used in conjunction with the
recommended limit value for 𝑬𝒈𝒅𝑷𝒓𝒐𝒄𝒆𝒔𝒔𝒐𝒓𝑼𝒕𝒊𝒍𝒊𝒛𝒂𝒕𝒊𝒐𝒏_% as per the watchdog time and
sweep load of the application.
2. EGD Consumption and Production below 20ms are not recommended for Embedded
Ethernet Interface on with CPE305/310.
3. It is advisable to limit the number of EGD exchanges or EGD load on Embedded Ethernet
Interface of the CPE305/310, and use higher periods while defining the system and
configuration, and take into account the sweep load for minimizing EGD sweep impact.
Constant Sweep - EGD on RX3i CPE305/310/330 Embedded Ethernet Interface:

The EGD on Embedded Ethernet Interface can be treated as interrupt blocks. Therefore, EGD
exchanges with Constant sweep may cause sweep overruns and should be avoided. It is also
recommended that the Production period for Producer exchanges be set to multiples (3 and above)
of the Constant sweep time set to avoid stale data being produced by the CPE305/310 system on
Embedded Ethernet Interface. Some of the factors affecting the Constant sweep overruns with EGD
on Embedded Ethernet Interface are Constant sweep time, No of Exchanges, Production period, and
Exchange data size.
The Constant sweep with EGD exchanges configured on Embedded Ethernet Interface and timed or
I/O interrupts will also cause constant sweep overruns and are not recommended.

A-3.7 Sweep Impact of Intelligent Option Modules

The tables in this section list the sweep impact times in microseconds (µs) for intelligent option
modules. The fixed sweep impact is the sum of the polling sweep impact and the I/O scan impact.
The opening of the Backplane Communications Window and the polling of each module have
relatively small impacts compared to the sweep impact of CPU memory read or write requests.
Intelligent option modules include GBCs being used for Genius LAN capabilities. The sweep impact for
these intelligent option modules is highly variable.
Fixed Sweep Impact Times of Intelligent Option Modules, RX7i
Sweep Impact Item CPE010 (µs) CPE020 (µs) CPE030 (µs) CPE040 (µs)
IC698ETM001 104 51 48 36
IC698HSC700 267 157 148 116
IC697BEM731 (GBC) See Sweep Impact Time of Genius I/O and GBCs.
Fixed Sweep Impact Times of RX3i Intelligent Option Modules
CPU310 (µs) CPU315/CPU320 (µs) NIU001+ (µs)
Sweep Impact
Main Exp Main Exp Main Exp
Item
Base Inc Base Inc Base Inc Base Inc Base Inc Base Inc
IC694APU300B 1085 — — — 1109 — — — — — — —
and earlier
IC694APU300-CA
and later
Classic 275980 — — — 204381 — — — — — — —
Enhanced 407480 — — — 327681 — — — — — — —
IC694BEM33182 See footnote — — — — — — — —
IC694DSM31483 See footnote — — — — See footnote
IC695ETM001 199 — NA NA 188 51 NA NA — — NA NA
IC695HSC304 208.7 173.9 NA NA 136.4 131.0 NA NA — — NA NA
IC695HSC308 282.4 256.5 NA NA 202.6 200.3 NA NA — — NA NA
IC695PBM300 — NA NA — NA NA — — NA NA
No I/O 132 60
100 bytes Input, 196 105
100 bytes Output
200 bytes Output
100 bytes Output
IC695PNC00184 NA NA NA NA See footnote NA NA NA NA NA NA NA
80 CPU firmware version 7.13

81 CPU firmware version 7.14
82 See Sweep Impact Time of Genius I/O and GBCs
83 See DSM314 Sweep Impact
84 See PROFINET Controller (PNC001) and PROFINET I/O Sweep Impact

PROFINET Controller (PNC001) and PROFINET I/O Sweep Impact

The PLC CPU sweep impact for a PROFINET IO network is a function of the number of PNCs, the
number of PROFINET devices, and the number of each PROFINET device’s IO modules. The table
below shows the measured sweep impact of the RX3i PROFINET Controller, supported VersaMax
PROFINET devices, and I/O modules.
Sweep Impact Item CPU315/CPU320 CPE305/CPE310 CPE330
(µs) (µs) (µs)
RX3i PROFINET Controller (PNC) 50
RX3i Devices
PROFINET Scanner (PNS) IC695PNS001 46
ALG442 Mixed Analog 54
ALG220 Analog Input 27
ALG390 Analog Output 24
MDL645 Discrete Input 23
MDL740 Discrete Output 22
VersaMax Devices
PROFINET Scanner (PNS), IC200PNS001 40
Discrete Input Module (8/16/32 pt.) 23
Discrete Output Module (8/16/32 pt.) 18
Analog Input Module (15 channel) 59
Analog Output Module (12 channel) 21
CMM020 (64AI/64AQ) 204
To calculate the total expected PLC sweep impact for a PROFINET I/O network, add the individual
sweep impact times for each PROFINET Controller, PROFINET Device, and PROFINET Device I/O
module, using the times provided above.
For example, for a PROFINET I/O network that consists of one PNC and one VersaMax PROFINET
Scanner, which has both an 8 point input and an 8 point output module:
Expected PLC Sweep Impact = 50 (PNC) + 40 (PNS) + 23 (8pt. Input) + 18 (8pt. Output)
=131 µs.
DSM314 Sweep Impact

Rx3i CPU310 Rack (µs) Rx3i NIU001+ Rack (µs)
No. of Axes
Configured Main Exp Main Exp
1 1535 2160 1830 2360
2 2018 2906 2304 3160
3 2500 6371 2840 3920
4 2990 4430 3350 4680

A-3.8 I/O Interrupt Performance and Sweep Impact

There are several important performance numbers for I/O interrupt blocks. The sweep impact of an
I/O interrupt invoking an empty block measures the overall time of fielding the interrupt, starting up
the block, exiting the block, and restarting the interrupted task. The time to execute the logic
contained in the interrupt block affects the limit by causing the CPU to spend more time servicing I/O
interrupts and thus reduce the maximum I/O interrupt rate.
The minimum, typical, and maximum interrupt response times reflect the time from when a single I/O
module sees the input pulse until the first line of ladder logic is executed in the I/O interrupt block.
Minimum response time reflects a 300 µs input card filter time + time from interrupt occurrence to
first line of ladder logic in I/O interrupt block. The minimum response time can only be achieved when
no intelligent option modules are present in the system and the programmer is not attached. Typical
response time is the minimum response time plus a maximum interrupt latency of 2.0 ms. This
interrupt latency time is valid, except when one of the following operations occurs:
 The programmer is attached.
 A store of logic, RUN Mode Store, or word-for-word change occurs.
 A fault condition (logging of a fault) occurs.
 Another I/O interrupt occurs.
 The CPU is transferring a large amount of input (or output) data from an I/O controller (such as a
GBC). Heavily loaded I/O controllers should be placed in the main rack whenever possible.
 An event that has higher priority and requires a response occurs. An example of this type of
event is clearing the I/O fault table.
Any one of these events extends the interrupt latency (the time from when the interrupt card signals
the interrupt to the CPU to when the CPU services the interrupt) beyond the typical value. However,
the latency of an interrupt occurring during the processing of a preceding I/O interrupt is unbounded.
I/O interrupts are processed sequentially so that the interrupt latency of a single I/O interrupt is
affected by the duration of the execution time of all preceding interrupt blocks. (The worst case is
that every I/O interrupt in the system occurs at the same time so that one of them has to wait for all
others to complete before it starts.)
The maximum response times shown below do not include the two unbounded events.
I/O Interrupt Block Performance and Sweep Impact Times
CPE305 CPU310 CPU315/ CPE010 CPE020 CPE030 CPE040
Sweep Impact Item CPE310 (µs) CPU320 (µs) (µs) (µs) (µs)
(µs) (µs)
I/O interrupt sweep impact -85 127.8 - 309.7 335 125.6 24.0
Minimum response time — 151.7 326.1 392.4 334 330.6 315.2
Typical response time 175.0 327.3 396.1 336 331.5 315.5
Maximum response time 302.7 346.2 434.9 359 375.1 325.7
Note that the min, typical, and max response times include a 300 µs Input card filter time.
85 Performance data not available for this release.

Dropped Interrupts
When multiple interrupts are triggered during the interrupt latency period, it is possible that interrupt
blocks will only be executed one time even though the interrupt trigger has occurred more than
once. The likelihood of this occurring will increase if the system interrupt latency has increased due to
the specific configuration and use of the system.
This will not cause the CPU to miss a given interrupt; just consolidate the number of times an
interrupt block is executed even though the interrupt stimulus had occurred more than one time.
Interrupt Trigger
Interrupt Logic Block
Interrupt
Logic
Suspended
Higher-priority event
Figure 52: Interrupt Execution Considerations

Worksheet D: Programmer, IOM, I/O Interrupt Sweep Time

The following worksheet can be used to calculate the sweep impact times of programmer sweep
impact, intelligent option modules, and I/O Interrupts. For time data, refer to the following tables:
Programmer Sweep Impact Times
RX7i Module Sweep Impact Times or RX3i I/O Module Sweep Impact Times
Sweep Impact Time of Genius I/O and GBCs
Programmer sweep impact = ______
IOM—first module (open comm. window) ______
IOM—per module (polling) + ______
LAN module I/O scan + ______
Total IOM Sweep Impact = ______
CPU memory access from IOMs = ______

I/O interrupt sweep impact ______
I/O interrupt response time + ______ = ______
Predicted Sweep Time (Other) ______

A-3.9 Timed Interrupt Performance

The sweep impact of a timed interrupt invoking an empty program block or timed program measures
the overall time of fielding the interrupt, starting up the program or block, exiting the program or
block, and restarting the interrupted task. The minimum, average, and maximum interrupt period
reflect the time period from when the first line of ladder logic is executed in the timed interrupt block.
Timed Interrupt Performance and Sweep Impact Times for a 0.001s Timed Interrupt Block
Sweep Impact Item CPU310 CPU315 CPE010 CPE020 CPE030 CPE040
(µs) CPU320 (µs) (µs) (µs) (µs)
(µs)
Timed interrupt sweep impact 87.3 26.2 88.6 28.0 31.2 23.3
Minimum interrupt period 908.3 969.8 951.4 946.0 922.8 973.0
Average interrupt period 1000.0 1000.0 1005.5 999.7 1000.0 999.9
Maximum interrupt period 1081.2 1030.8 1056.6 1054.0 1077.0 1026.9

A-3.10 Example of Predicted Sweep Time Calculation

The sweep time estimate in this example does not include a time for logic execution. The calculated
sweep is for normal sweep time with point faults disabled, and the programmer is not attached. The
times used in the calculation are extracted from the following tables:
Base Sweep Times
RX7i Module Sweep Impact Times or RX3i I/O Module Sweep Impact Times
Sweep Impact Time of Genius I/O and GBCs.
A sample calculation of predicted sweep times is provided after the example.
Sample RX7i System Configuration
PS CPE010 BTM 32PT 32PT 32PT 32PT 8CHN 4CHN ETM

Input Input Output Output Analog Analog
Input Output
0 1 2 3 4 5 6 7 8 9
MAIN RACK
Sweep Calculations (in µS)
Predicted Sweep = Base Sweep + I/O Scan Impact
Base Sweep Time = 465

I/O Scan Impact …
Number of discrete input type 2 modules—main rack 2
Sweep impact time per discrete I/O module x 37.9 = 75.8
Number of discrete output type 2 modules—main rack 2
Sweep impact time per discrete I/O module x 80.4 = 80.4
Number of analog input modules—main rack 1
Sweep impact time per analog base and output module x 49.3 = 49.3
Number of analog output modules—main rack 1
Sweep impact time per analog base and output module x 49.7 = 49.7
Ethernet Module 1 x 55.0 = 55.0
Predicted Sweep Time = 775.2

Appendix B User Memory Allocation
User Memory Size is the number of bytes of memory available to the user for PLC applications.
Model User Memory Size (MB)

IC695CPE305 5MB
IC695CPU310, IC695CPE310, IC698CPE010, IC698CPE020, IC698CRE020 10MB
IC695CPU315 20MB
IC695CPE400, IC695CPE330, IC695CPU320, IC695CRU320 64MB
IC698CPE030, IC698CRE030
64MB
IC698CPE040, IC698CRE040
For a list of items that count against user memory, see below.

Appendix B. User Memory Allocation
B-1 Items that Count Against User Memory

The following items count against the CPU memory and can be used to estimate the minimum
amount of memory required for an application. Additional space may be required for items such as
Advanced User Parameters, zipped source files, user heap, and published symbols.
Register Memory Size (%R) Bytes = %R references configured  2
Word Memory Size (%W) Bytes = %W references configured  2
Analog Inputs (%AI) If point faults enabled: Bytes = %AI references configured  3
If point faults disabled: Bytes = %AI references configured  2
Analog Outputs (%AQ) If point faults enabled: Bytes = %AQ references configured  3
If point faults disabled: Bytes = %AQ references configured  2
Discrete Point Faults If point faults enabled: Bytes = 3072
Managed Memory The total number of bytes required for symbolic and I/O variables. Calculated
(Symbolic Variable and I/O as follows:
Variable Storage) [(number of symbolic discrete bits) × 3 / (8 bits/byte)]
+ [(number of I/O discrete bits) × Md / (8 bits/byte)]
+ [(number of symbolic words) × (2 bytes/word)]
+ [(number of I/O words) × (Mw bytes/word)]
Md = 3 or 4. The number of bits is multiplied by 3 to keep track of the force,
transition, and value of each bit. If point faults are enabled, the number of I/O
discrete bits is multiplied by 4.
Mw = 2 or 3. There are two 8-bit bytes per 16-bit word. If point faults are
enabled, the number of bytes is multiplied by 3 because each I/O word
requires an extra byte.
EGD (included in HWC) Bytes = 0 if no Ethernet Global Data pages are configured
I/O Scan Set File Based on number of scan sets used.
(included in HWC) Note: 32 bytes of user memory are consumed if the application scans all
I/O every sweep (the default).
User Programs Refer to User Program Memory Usage below for details on user programs.

Appendix B. User Memory Allocation
B-2 User Program Memory Usage

Space required for user logic includes the following items.
B-2.1 %L and %P Program Memory
%L and %P are charged against your user space and sized depending on their use in your
applications. The maximum size of %L or %P is 8192 words per block.
The %L and %P tables are sized to allow extra space for RUN Mode Stores per the following rules.
 If %L memory is not used in the block, the %L memory size is 0 bytes. If %L memory is used in the
block, a buffer is added beyond the highest %L address actually used in logic or in the variable
table. The default buffer size is 256 bytes, but can be changed by editing the Extra Local Words
parameter in the block Properties.
 The same rules apply for the size of %P memory, but %P memory can be used in any block in the
program.
 The buffer cannot make the %P or %L table exceed the maximum size of 8,192 words. In such a
case, a smaller buffer is used.
 You can add, change, or delete %L and/or %P variables in your application and RUN Mode Store
the application if these variables fit in the size of the last-stored %L/%P tables (where the size
includes the previous buffer space), or if going from a zero to non-zero size.
 The size of the %L/%P tables is always recalculated for STOP Mode Stores.
B-2.2 Program Logic and Overhead
The data area for C (.gefelf) blocks is considered part of the user program and counts against
the user program size. Additional space is required for information internal to the CPU that is
used for execution of the C block.
The program block is based on overhead for the block itself plus the logic and register data being
used (that is, %L).
Note: The program stack of the LD is not counted against the CPU’s memory size.
Note: If your application needs more space for LD logic, consider changing some %P or %L
references to %R, %W, %AI, or %AQ. Such changes require a recompilation of the program block and
a STOP Mode Store to the CPU.

GE’s Automation & Controls Additional Resources
Information Centers For more information, please
Headquarters: visit GE’s Automation &
1-800-433-2682 or 1-434-978-5100 Controls web site:
Global regional phone numbers www.geautomation.com
are available on our web site
www.geautomation.com
Copyright ©2003-2016 General Electric

Company. All Rights Reserved
*Trademark of General Electric Company. GFK-2222Y
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respective holders.

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Automation & Controls

RX7i & RX3i CPU Reference Manual

Warnings, Cautions, and Notes as Used in this Publication GFL-002

* indicates a trademark of General Electric Company and/or its subsidiaries.

©Copyright 2003-2016 General Electric Company.

General Contact Information

Europe, the Middle East, and Africa

1.1 Revisions in this Manual ............................................................................................................. 2

1.2 PACSystems Control System Overview .................................................................................... 4

1.3 RX3i Overview ............................................................................................................................... 6

1.4 RX7i Overview ............................................................................................................................... 9

1.5 Migrating Series 90 Applications to PACSystems ................................................................ 10

Chapter 2 CPU Features & Specifications .......................................................................................... 13

2.1 Common CPU Features ............................................................................................................. 14

2.2 RX3i CPU Features and Specifications ................................................................................... 23

2.3 RX7i CPU Features and Specifications ................................................................................... 69

GFK-2222Y December 2016 i

2.3.2 CPE010, CPE020 and CRE020 .........................................................................................................................................75

Chapter 3 CPU Configuration............................................................................................................... 83

3.1 Configuring the CPU .................................................................................................................. 84

3.2 Configuration Parameters........................................................................................................ 85

3.3 Storing (Downloading) Hardware Configuration ............................................................... 102

3.4 Configuring the Embedded Ethernet Interface .................................................................. 103

Chapter 4 CPU Operation ................................................................................................................... 107

4.1 CPU Sweep ................................................................................................................................. 108

4.2 Program Scheduling Modes ................................................................................................... 115

4.3 Window Modes ......................................................................................................................... 115

4.4 Data Coherency in Communications Windows.................................................................. 115

4.5 Run/Stop Operations ............................................................................................................... 116

4.6 Flash Memory Operation ........................................................................................................ 120

ii PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

4.8 Clocks and Timers .................................................................................................................... 123

4.9 System Security ........................................................................................................................ 126

4.10 PACSystems I/O System .......................................................................................................... 131

4.11 Power-Up and Power-Down Sequences .............................................................................. 138

Chapter 5 Communications ............................................................................................................... 145

5.1 Ethernet Communications ..................................................................................................... 146

5.2 Serial Communications ........................................................................................................... 151

Chapter 6 Serial I/O, SNP & RTU Protocols ...................................................................................... 163

GFK-2222Y December 2016 iii

6.1.4 Invalid Port Configuration Combinations .............................................................................................................. 165

6.2 Serial I/O Protocol .................................................................................................................... 169

6.3 RTU Slave Protocol ................................................................................................................... 187

6.4 SNP Slave Protocol ................................................................................................................... 218

Appendix A Performance Data ................................................................................................................... 219

A-1 Boolean Execution Times ..................................................................................................................... 220

A-2 Instruction Timing ................................................................................................................................. 221

A-3 Overhead Sweep Impact Times .......................................................................................................... 247

iv PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

A-3.3 Programmer Sweep Impact Times ........................................................................................................................... 251

Appendix B User Memory Allocation ......................................................................................................... 273

B-1 Items that Count Against User Memory ........................................................................................... 274

B-2 User Program Memory Usage ............................................................................................................. 275

GFK-2222Y December 2016 v

vi PACSystems* RX7i & RX3i CPU Reference Manual GFK-2222Y

Figure 51: RTU Error Response Format _________________________________________________________ 214

GFK-2222Y December 2016 vii

GFK-2222Y December 2016 1

1.1 Revisions in this Manual