Daewoo Dtl-2950 K GB Chassis Cp-650

P/N : TCP650FEF0
Service Manual
COLOR Television
CHASSIS :CP-650
Model :DTL-2950
DTL-2950K
DTL-2950GB
Caution
: In this Manual, some parts can be changed for improving. their
performance without notice in the parts list. So, if you need the
latest parts information, please refer to PPL(Parts Price List)in
Service Information Center.
APR.2006
CP-650 Service Manual
CONTENTS
DOCUMENT HISTORY .................................................................................................................3

1 MAIN FEATURES ..................................................................................................................4
1.1 SPECIFICATIONS ..........................................................................................................4
1.1.1 GENERAL ................................................................................................................4
1.1.2 EURO-SCART 1 (21 Pin) .........................................................................................4
1.1.3 EURO-SCART 2 (21 Pin) .........................................................................................5
1.2 CHANNEL/FREQUENCY TABLE...................................................................................6
2 SAFETY INSTRUCTION ........................................................................................................9
3 ALIGNMENT INSTRUCTIONS.............................................................................................10
3.1 MICROCONTROLLER CONFIGURATION : SERVICE MODE ....................................10
3.2 SERVICE MODE NAVIGATION....................................................................................10
3.3 MICROCONTROLLER CONFIGURATION : OPTION BITS ........................................11
3.4 OPTION 1......................................................................................................................11
3.5 OPTION 2......................................................................................................................11
3.6 NVM DEFAULT SETTING ............................................................................................12
3.7 TV SET ALIGNMENT....................................................................................................14
3.7.1 G2 ALIGNMENT.....................................................................................................14
3.7.2 WHITE BALANCE ..................................................................................................14
3.7.3 FOCUS...................................................................................................................14
3.7.4 VERTICAL GEOMETRY ........................................................................................14
3.7.5 HORIZONTAL PICTURE CENTRING ....................................................................14
3.7.6 EAST / WEST CORRECTION................................................................................14
3.7.7 AGC........................................................................................................................15
4 IC DESCRIPTION.................................................................................................................16
4.1 UOC III SERIES..............................................................................................................16
4.1.1 IC MARKING AND VERSION ................................................................................16
4.2 TDA8946J STEREO AUDIO AMPLIFIER.....................................................................24
4.2.1 FEATURES ............................................................................................................25
4.3 TDA8358J VERTICAL AMPLIFIER ..............................................................................27
4.3.1 TDA8358J ..............................................................................................................27
4.4 TDA6107AJF ................................................................................................................29
4.4.1 Features .................................................................................................................29
4.4.2 Pin description........................................................................................................29
4.5 24WC16 - 16 KB EEPROM...........................................................................................30
4.6 STR – W6754 ................................................................................................................31
4.6.1 GENERAL DESCRIPTION.....................................................................................31
4.6.2 FEATURES ............................................................................................................31
4.6.3 BLOCK DIAGRAM .................................................................................................31
4.6.4 PIN DESCRIPTION ................................................................................................32
4.6.5 MOSFET ELECTRICAL CHARACTERISTICS.......................................................32
4.6.6 ELECTRICAL CHARACTERISTICS.......................................................................33
5 CIRCUIT DESCRIPTION......................................................................................................34
5.1 BLOCK DIAGRAM........................................................................................................34
5.2 FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR ............................................35
5.2.1 Vision IF amplifier ...................................................................................................35
5.2.2 QSS sound circuit...................................................................................................35
5.2.3 FM demodulator .....................................................................................................35
5.2.4 Audio input selector and volume contro..................................................................36
DTV R&D Europe 1
5.2.4.1 STEREO AND AV STEREO VERSIONS............................................................36

5.2.4.2 MONO VERSIONS .............................................................................................36
5.2.5 CVBS and Y/C input signal selection......................................................................36
5.2.5.1 ALL VERSIONS ..................................................................................................36
5.2.6 Synchronisation circuit............................................................................................37
5.2.7 Horizontal and vertical drive ...................................................................................38
5.2.8 Chroma, luminance and feature processing ...........................................................38
5.2.9 Colour decoder.......................................................................................................39
5.2.10 RGB output circuit ..................................................................................................40
5.2.11 I2C-BUS USER INTERFACE DESCRIPTION........................................................42
5.3 GENERAL DESCRIPTION OF THE TV SOUND OF SOUND PROCESSOR ..............42
5.3.1 Supported standards ..............................................................................................43
5.4 FUNCTIONAL DESCRIPTION SOUND PROCESSOR ................................................44
5.4.1 The UOC III TV Sound Concept .............................................................................44
5.4.2 Functional Overview Of the digital controller sound part ........................................45
5.4.3 Demodulator and decoder ......................................................................................46
6 SERVICE PARTS LIST ........................................................................................................49
6.1 DTL-2950 ......................................................................................................................49
7 EXPLODED VIEW................................................................................................................68
7.1 DTL-2950 ......................................................................................................................68
8 PRINTED CIRCUIT BOARD ................................................................................................69
8.1 PCB MAIN(4859812493)...............................................................................................69
8.2 PCB SUB)4859816424)................................................................................................ 70
9 SCHEMATIC DIAGRAM ......................................................................................................71
DTV R&D Europe 2

DOCUMENT HISTORY
VERSION DATE COMMENTS

V1.00 28/03/06 Creation of document (Author JS KIM) for project CP650 50Hz SLIM TV.
DTV R&D Europe 3

1 MAIN FEATURES
1.1 SPECIFICATIONS
1.1.1 GENERAL
TV standard PAL - SECAM B/G D/K, PAL I/I, SECAM L/L’

Colour system Tuner PAL, SECAM
AV PAL, SECAM, PAL 60, NTSC M, NTSC 4.43
Sound system NICAM B/G, I, D/K, L,
FM 2Carrier B/G, D/K
Power 105W
consumption
Sound Output 7W x 2 (at 60% mod, 10%THD)
Power
Speaker 12W 8 ohm x2
Teletext system 10 pages memory FASTEXT (FLOF or TOP)
Aerial input 75 ohm unbalanced
Channel coverage Off-air channels, S-cable channels and hyperband
Tuning system frequency synthesiser tuning system
Visual screen size 68cm
Channel indication On Screen Display
Program Selection 100 programmes
Aux. terminal EURO-SCART 1 : Audio / Video In and Out, R/G/B
In, Slow and Fast switching.
EURO-SCART 2 : Audio / Video In and Out, SVHS
In.
AV3 : Audio-Video Jack on front of cabinet.
Headphone jack (3.5 mm) on front of cabinet
SVHS3 : Jack on side of cabinet – sound input
common with AV3.
Remote Control R-49C10
Unit
1.1.2 EURO-SCART 1 (21 Pin)

Pin Signal Description Matching value
1 Audio Output Right 0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
2 Audio Input Right 0.5 Vrms, Impedance > 10 kΩ
3 Audio Output Left 0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
4 Audio Earth
5 Blue Earth
6 Audio Input Left 0.5 Vrms, Impedance > 10 kΩ
7 Blue Input 0.7 Vpp ±0.1V, Impedance 75Ω
8 Slow Switching TV : 0 to 2V, AV 16/9 : 4.5 to 7V, AV 4/3 : 9.5 to 12V , Impedance
> 10 kΩ
9 Green Earth
10 N.C.
DTV R&D Europe 4

11 Green Input 0.7 Vpp ± 0.1V, Impedance 75Ω

12 N.C.
13 Red Earth
14 Blanking Earth
15 Red Input 0.7 Vpp ± 0.1V, Impedance 75Ω
16 Fast Switching 0 to 0.4V : Logic “0”, 1 to 3V : Logic “1”, Impedance 75Ω
17 Video Out Earth
18 Video In Earth
19 Video Output 1 Vpp ± 3dB, Impedance 75Ω
20 Video Input 1 Vpp ± 3dB, Impedance 75Ω
21 Common Earth
1.1.3 EURO-SCART 2 (21 Pin)
Pin Signal Description Matching value
1 Audio Output Right 0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
2 Audio Input Right 0.5 Vrms, Impedance > 10 kΩ
3 Audio Output Left 0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
4 Audio Earth
5 Earth
6 Audio Input Left 0.5 Vrms, Impedance > 10 kΩ
7 N.C.
8 N.C.
9 N.C.
10 N.C.
11 N.C.
12 N.C.
13 Earth
14 Earth
15 Chroma Input ± 3dB for a luminance signal of 1 Vpp
16 N.C.
17 Earth
18 Video In Earth
19 Video Output 1 Vpp ± 3dB, Impedance 75Ω ( Monitor output )
20 Video Input, Y In. 1 Vpp ± 3dB, Impedance 75Ω
21 Common Earth
DTV R&D Europe 5

1.2 CHANNEL/FREQUENCY TABLE
CHANNEL EUROPE CCIR FRANCE GB(IRELAND) EAST OIRT

C01 46.25 - 45.75 49.75
C02 48.25 55.75 (L') 53.75 59.25
C03 55.25 60.5 (L') 61.75 77.25
C04 62.25 63.75 (L') 175.25 85.25
C05 175.25 176.00 183.25 93.25
C06 182.25 184.00 191.25 175.25
C07 189.25 192.00 199.25 183.25
C08 196.25 200.00 207.25 191.25
C09 203.25 208.00 215.25 199.25
C10 210.25 216.00 223.25 207.25
C11 217.25 189.25 (LUX) 231.25 215.25
C12 224.25 69.25 (L') 239.25 223.25
C13 53.75 76.25 (L') 247.25 -
C14 - 83.25 (L') 49.75 -
C15 82.25 90.25 57.75 -
C16 - 97.25 65.75 -
C17 183.75 - 77.75 -
C18 192.25 - 85.75 -
C19 201.25 - - -
C20 - - - -
C21 471.25 471.25 471.25 471.25
C22 479.25 479.25 479.25 479.25
C23 487.25 487.25 487.25 487.25
C24 495.25 495.25 495.25 495.25
C25 503.25 503.25 503.25 503.25
C26 511.25 511.25 511.25 511.25
C27 519.25 519.25 519.25 519.25
C28 527.25 527.25 527.25 527.25
C29 535.25 535.25 535.25 535.25
C30 543.25 543.25 543.25 543.25
C31 551.25 551.25 551.25 551.25
C32 559.25 559.25 559.25 559.25
C33 567.25 567.25 567.25 567.25
C34 575.25 575.25 575.25 575.25
C35 583.25 583.25 583.25 583.25
C36 591.25 591.25 591.25 591.25
C37 599.25 599.25 599.25 599.25
C38 607.25 607.25 607.25 607.25
C39 615.25 615.25 615.25 615.25
C40 623.25 623.25 623.25 623.25
C41 631.25 631.25 631.25 631.25
C42 639.25 639.25 639.25 639.25
C43 647.25 647.25 647.25 647.25
C44 655.25 655.25 655.25 655.25
C45 663.25 663.25 663.25 663.25
DTV R&D Europe 6

C46 671.25 671.25 671.25 671.25

C47 679.25 679.25 679.25 679.25
C48 687.25 687.25 687.25 687.25
C49 695.25 695.25 695.25 695.25
C50 703.25 703.25 703.25 703.25
C51 711.25 711.25 711.25 711.25
C52 719.25 719.25 719.25 719.25
C53 727.25 727.25 727.25 727.25
C54 735.25 735.25 735.25 735.25
C55 743.25 743.25 743.25 743.25
C56 751.25 751.25 751.25 751.25
C57 759.25 759.25 759.25 759.25
C58 767.25 767.25 767.25 767.25
C59 775.25 775.25 775.25 775.25
C60 783.25 783.25 783.25 783.25
C61 791.25 791.25 791.25 791.25
C62 799.25 799.25 799.25 799.25
C63 807.25 807.25 807.25 807.25
C64 815.25 815.25 815.25 815.25
C65 823.25 823.25 823.25 823.25
C66 831.25 831.25 831.25 831.25
C67 839.25 839.25 839.25 839.25
C68 847.25 847.25 847.25 847.25
C69 855.25 855.25 855.25 855.25
C70 863.25 863.25 863.25 863.25
C71 69.25 - - -
C72 76.25 - - -
C73 83.25 - - -
C74 90.25 - - -
C75 97.25 - - -
C76 59.25 - - -
C77 93.25 - - -
S01 105.25 104.75 103.25 105.25
S02 112.25 116.75 111.25 112.25
S03 119.25 128.75 119.25 119.25
S04 126.25 140.75 127.25 126.25
S05 133.25 152.75 135.25 133.25
S06 140.25 164.75 143.25 140.25
S07 147.25 176.75 151.25 147.25
S08 154.25 188.75 159.25 154.25
S09 161.25 200.75 167.25 161.25
S10 168.25 212.75 - 168.25
S11 231.25 224.75 - 231.25
S12 238.25 236.75 - 238.25
S13 245.25 248.75 255.25 245.25
S14 252.25 260.75 263.25 252.25
S15 259.25 272.75 271.25 259.25
S16 266.25 284.75 279.25 266.25
S17 273.25 296.75 287.25 273.25
DTV R&D Europe 7

S18 280.25 136.00 295.25 280.25

S19 287.25 160.00 303.25 287.25
S20 294.25 - - 294.25
S21 303.25 303.25 - 303.25
S22 311.25 311.25 311.25 311.25
S23 319.25 319.25 319.25 319.25
S24 327.25 327.25 327.25 327.25
S25 335.25 335.25 335.25 335.25
S26 343.25 343.25 343.25 343.25
S27 351.25 351.25 351.25 351.25
S28 359.25 359.25 359.25 359.25
S29 367.25 367.25 367.25 367.25
S30 375.25 375.25 375.25 375.25
S31 383.25 383.25 383.25 383.25
S32 391.25 391.25 391.25 391.25
S33 399.25 399.25 399.25 399.25
S34 407.25 407.25 407.25 407.25
S35 415.25 415.25 415.25 415.25
S36 423.25 423.25 423.25 423.25
S37 431.25 431.25 431.25 431.25
S38 439.25 439.25 439.25 439.25
S39 447.25 447.25 447.25 447.25
S40 455.25 455.25 455.25 455.25
S41 463.25 463.25 463.25 463.25
DTV R&D Europe 8

2 SAFETY INSTRUCTION
WARNING: Only competent service personnel may carry out work involving the testing or repair
of this equipment.
X-RAY RADIATION PRECAUTION
1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION. To avoid
such hazards, the high voltage must not exceed the specified limit. The nominal value of the high
voltage of this receiver is 28.5KV at max beam current. The high voltage must not, under any
circumstances, exceed 30 KV. Each time a receiver requires servicing, the high voltage should
be checked. It is important to use an accurate and reliable high voltage meter.
2. The only source of X-RAY Radiation in this TV receiver is the picture tube. For continued
X-RAY RADIATION protection, the replacement tube must be exactly the same type tube as
specified in the parts list.
SAFETY PRECAUTION
Potentials of high voltage are present when this receiver is operating. Operation of the receiver
outside the cabinet or with the back board removed involves a shock hazard from the receiver.
Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions
necessary when working on high voltage equipment.
Discharge the high potential of the picture tube before handling the tube. The picture tube is
highly evacuated and if broken, glass fragments will be violently expelled.
If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement
Parts List.
When replacing a high wattage resistor (metal oxide film resistor) in the circuit board, keep the
resistor 10 mm away from circuit board.
Keep wires away from high voltage or high temperature components.
This receiver must operate under AC 230 volts, 50 Hz. NEVER connect to a DC supply or any
other voltage or frequency.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this equipment have special safety-related
characteristics. These characteristics are often passed unnoticed by a visual inspection and the
X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using
replacement components rated for higher voltage, wattage, etc. Replacement parts which have
these special safety characteristics are identified in this manual and its supplements, electrical
components having such features are identified by designated symbol on the parts list. Before
replacing any of these components, read the parts list in this manual carefully. The use of
substitutes replacement parts which do not have the same safety characteristics as specified in
the parts list may create X-RAY Radiation.
DTV R&D Europe 9

3 ALIGNMENT INSTRUCTIONS
3.1 MICROCONTROLLER CONFIGURATION : SERVICE MODE
To switch the TV set into service mode please see instruction below.
1 - Select PR. number 91

2 - Adjust sharpness to minimum and exit all menus.
3 – Within 2 seconds press the key sequence : RED - GREEN - menu
The software version is displayed beside the word Service, e.g. “SERVICE VER 01.44”.
To exit SERVICE menu press menu key or Std By key.

3.2 SERVICE MODE NAVIGATION
Pr Up/Down remote keys : cycle through the service items available.

Vol -/+ remote keys : Dec./Increment the values within range – Cycle trough option bits.
OK key : Toggle bits in option byte
Order Setting In Indication Default setting

Note : All settings are approximate
1 HOR CEN 52
2 RED GAIN 31
3 GRN GAIN 31
4 BLUE GAIN 31
5 RED BIAS 31
6 GRN BIAS 31
7 AGC LEVEL 31
8 G2 – SCREEN -
9 OPTION1 0011 1000 (0x38)
10 OPTION2 0000 1111 (0x0F)
11 AVL OFF
12 PARABOLA 33
13 HOR WIDTH 55
14 CORNER T 45
15 CORNER B 50
16 HOR. PARAL 29
17 V. LINEAR 40
18 V. SLOPE 28
19 EW TRAPEZ 20
20 S CORRECT 37
21 VERT CENT 44
22 VERT SIZE 28
23 BRIGHTNESS 0
24 SHIPPING OFF
DTV R&D Europe 10

3.3 MICROCONTROLLER CONFIGURATION : OPTION BITS
There are two option bytes available (16 bits in all). These option bits are available from Service
mode. First find the OPTION1 or OPTION2 control, and then use the Volume PLUS/MINUS
buttons on the remote control keypad to locate the bits, and OK key to toggle them. The table
below shows the two option bytes available;
3.4 OPTION 1
B7 B6 B5 B4 B3 B2 B1 B0
TOP FASTEXT VAI bit set Dolby
TUBE SVHS3 TUNER OPTIONS
1 Teletext (FLOF) to 1 in Virtual
4:3 disable 00 = Philips
OFF OFF SECAM L OFF
01 = Not used
TOP VAI bit set Dolby
FASTEXT TUBE SVHS3 10 = Alps
0 Teletext to 0 in Virtual
(FLOF) ON 16:9 enable 11 = Parstnic (DW)
ON SECAM L ON
3.5 OPTION 2
B7 B6 B5 B4 B3 B2 B1 B0
JVC AVL 5 keys Full Double n.u.
PICTURE
1 remote control lacal ATSS Window Must
TILT ON
control OFF keyboard Enabled be set
Fixed to
to 1 for
‘0’ Daewoo AVL 7 keys Double
PICTURE Basic future
0 Remote control lacal Window
TILT OFF ATSS compa
control ON keyboard Disabled
tibility
DTV R&D Europe 11

3.6 NVM default setting
The purpose of this message, when you change a virgin EEPROM, is to allow to modify
the NVM DATA to desired values.
1 - Introduction :
The NVM default valus are fixed for the user, but for flexibility in service, these data are stored in
NVM and can be changed when the TV set is in a special mode call "NVM EDITOR". This mode
can only be access from "FACTORY" mode.
2 - Entering into "FACTORY" mode.

To switch the TV set into FACTORY mode, use the factory remote control, and press on “SVC”
key. The factory menu will appear on the screen, showing “FACTORY” , plus other relevant
information like software version and date.
WARNING : When in "FACTORY" mode you should not press any key other than the keys
described in the procedure below. Unwanted key stroke could misadjust the TV set.
3 - Entering into "NVM EDITOR" mode.

To switch the TV set into NVM EDITOR mode, use the user remote control, and press on
“PICTURE/OK” key. The NVM EDITOR window will appear on the screen. This mode allow you
to access all data stored in NVM. The current NVM address is given in column "ADDR." in both
DECimal and HEXadecimal format. The column DATA gives the value contained at selected
address in both DECimal and HEXadecimal format.
4 - Navigation in "NVM EDITOR" mode.

Use Program Up/Dwn keys to select the desired address. Use Volume Up/Dwn keys to change
the data at selected address. You must press "PICTURE/OK" key to store value after
modification.
The data can be adjusted between 0 and 63.
5 - Exit "NVM EDITOR" mode.

To switch the TV set back into FACTORY mode, use the user remote control, and press on
“MENU” key.
The factory menu will appear on the screen, showing “FACTORY”.
6 - Exit "FACTORY" mode.

To exit "FACTORY" mode, use the factory remote control, and press on “SVC” key.
The factory menu will disappear from the screen.
DTV R&D Europe 12

NVM DATA for CP-650

No Register Name Address SETTING VALUE
1 AGC start(Philips) 0x5C5 0x0C
2 AGC start(nc) 0x5C6 0x0C
3 AGC start(ALPS) 0x5C7 0x0C
4 AGC start(Partsnic) 0x5C8 0x0C
5 OCP_THRESHOLD 0x58F 0x91
6 DCXO 0x590 0x4E
7 POWER ON1 0x595 0x2D
8 POWER ON2 0x596 0x1E
9 AVLLEV 0x621 0x5
10 AVL 0x622 0x0
11 TTX_Brightness 0x642 0x12
12 Nor1_Bright 0x64A 0x25
13 Nor1_contrast 0x64B 0x2E
14 Nor1_Colour 0x64C 0x20
15 Nor1_Sharpness 0x64D 0x23
16 Nor1_Tint 0x64E 0x1F
17 Nor2_Bright 0x653 0x28
18 Nor2_Contrast 0x654 0x13
19 Nor2_Colour 0x655 0x19
20 Nor2_Sharpness 0x656 0x1B
21 Nor2_Tint 0x657 0x1F
22 BOW 0x665 0x19
23 V-LINEAR 0x667 0x28
24 Peaking White Level 0x671 0x01
25 Soft Clipping Level 0x672 0x05
26 PresetGainRGB 0x673 0x18
29 Cathode_Drive 0x67B 0x00
30 RPA 0x680 0x01
31 Black Stretch 0x682 0x01
32 BSD 0x683 0x01
33 AAS 0x684 0x00
34 BCS 0x685 0x00
35 Y_delay_PAL_BG 0x686 0x0F
36 Y_delay_SECAM_BG 0x687 0x8
37 Y_delay_PAL_DK 0x688 0x08
38 Y_delay_SCM_DK 0x689 0x06
39 Y_delay_PAL_I 0x68A 0x0B
40 Y_delay_SECAM 0x68B 0x5
41 Y_delay_SECAM-L 0x68C 0x05
42 Y_delay_AV 0x68D 0x0F
43 G2_Bright 0x68E 0x28
44 G2_Contrast 0x68F 0x42
45 TxTPIT_Hoffset 0x693 0x10
DTV R&D Europe 13

3.7 TV SET ALIGNMENT
3.7.1 G2 ALIGNMENT
- Tune a colour bar pattern.
- Find the “G2 – SCREEN” item in service mode.
- Adjust screen volume (on FBT) to bring the cursor to central position(Green).
3.7.2 WHITE BALANCE
- Select a dark picture and adjust RED BIAS and GRN BIAS to the desired colour temperature.
- Select a bright picture and adjust RED, GRN and BLUE GAIN to the desired colour temperature.
3.7.3 FOCUS
Adjust the Focus volume (on FBT) to have the best resolution on screen.
3.7.4 VERTICAL GEOMETRY
Adjust V. LINEAR (linearity), S CORRECT (S. Correction), VERT SIZE (Vertical amplitude),
VERT CENT (vertical centring) to compensate for vertical distortion.
3.7.5 HORIZONTAL PICTURE CENTRING

Adjust HOR CEN (Horizontal centre) to have the picture in the centre of the screen.
3.7.6 EAST / WEST CORRECTION
Adjust the PARABOLA, HOR WIDTH, CORNER, HOR PARAL, EW TRAPEZ, to compensate for
geometrical distortion.
HOR PARAL
DTV R&D Europe 14

HOR WIDTH
adjust for 93% overscan.
PARABOLA
CORNER B & CORNER T
EW TRAPEZ
3.7.7 AGC
- Make sure option bits are correct for the tuner fitted on the chassis (See above how to change
option bits).
- Adjust the antenna signal level at 62 dBµV
- Tune a colour bar pattern.
- Find the “AGC” item in service mode.
- Press the key “OK” on the remote keypad and wait until AGC level stabilise to the optimum
value.
- Alternatively, use “Vol Up/Dwn” keys to adjust manually to the desired Tuner Take Over Point
(TOP).
DTV R&D Europe 15
4 IC DESCRIPTION
4.1 UOC III Series
The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a
FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed
Caption decoder. In addition the following functions can be added:
• Adaptive digital (4H/2H) PAL/NTSC combfilter

• Teletext decoder with 10 page text memory
• Multi-standard stereo decoder
• BTSC stereo decoder
• Digital sound processing circuit
• Digital video processing circuit
4.1.1 IC MARKING AND VERSION

Chassis IC marking OSD languages ATSS countries Text
BULGARIAN,
CZECH, GERMAN, Austria, Belgium,
DANISH, SPANISH, Switzerland, Czech
FRENCH, FINNISH, Republic, Germany,
ENGLISH, GREEK, Denmark, Spain,
HUNGARIAN, France, Finland, GB,
TDA12021H ITALIAN, PAN-EUROPEAN
CP-650 Greece, Hungary, Italy, LATIN, CYRILLIC,
1/N1F01 NORWEGIAN, Ireland, Norway, GREEK.
DUTCH, Netherlands, Portugal,
PORTUGAL, Poland, Sweden,
POLISH, Slovak Republic,
ROMANIAN, Others
RUSSIAN,
SWEDISH
DTV R&D Europe 16

4.1.2. BLOCK DIAGRAM
DTV R&D Europe 17

4.1.3. PINNING
QFP 128pin Symbol Short Description

1 P1.5/TX Port 1.5 or UART bus
2 P1.4/RX port 1.4 or UART bus
3 P1.2/INT2 port 1.2 or external interrupt 2
4 VSSC3 Ground
5 VDDC3 digital supply to core (1.8V)
6 P2.5/PWM4 port 2.5 or PWM4 output
8 VSSC/P digital ground for m-Controller core and periphery
9 P3.3/ADC3 port 3.3 or ADC3 input
11 DECV1V8 decoupling 1.8 V supply
12 VDDC1 digital supply to core (+1.8 V)
18 P2.0/TPWM port 2.0 or Tuning PWM output
supply to periphery and on-chip voltage regulator (3.3
19 VDDP(3.3V)
V)
20 P1.7/SDA port 1.7 or I2C-bus data line
21 P1.6/SCL port 1.6 or I2C-bus clock line
22 P1.3/T1 port 1.3 or Counter/Timer 1 input
23 P0.0/I2SDI1/O port 0.0 or I2S digital input 1 or I2S digital output
24 P0.1/I2SDO1 port 0.1 or I2S digital output 1
25 P0.2/I2SDO2 port 0.2 or I2S digital output 2
26 P0.3/I2SCLK port 0.3 or I2S clock
27 P0.4/I2SWS port 0.4 or I2S word select
28 VSSC2 Ground
29 VDDC2 digital supply to core (1.8 V)
30 P1.1/T0 port 1.1 or Counter/Timer 0 input
31 P1.0/INT1 port 1.0 or external interrupt 1
external interrupt 0 or port 0.5 (4 mA current sinking
32 INT0/P0.5
capability for direct drive of LEDs)
33 VDDadc(1.8) supply voltage video ADC
34 VSSadc ground for on-chip temperature sensor
35 VDDA2(3.3) supply voltage SDAC (3.3 V)
36 VDDA(1.8) analogue supply for audio ADCs (1.8 V)
37 GNDA Ground
38 VREFAD reference voltage for audio ADCs (3.3/2 V)
39 VREFAD_POS positive reference voltage (3.3 V)
40 VREFAD_NEG negative reference voltage (0 V)
analog supply for TCG m-Controller and digital supply
41 VDDA1 for
TV-processor (+3.3 V)
42 BO Blue output
43 GO Green output
DTV R&D Europe 18

44 RO Red output
45 BLKIN black current input
46 BCLIN beam current limiter input
47 VP3 3rd supply for TV processor
48 GND3 ground 3 for TV-processor
49 B/PBIN3 3rd B input / PB input
50 G/YIN3 3rd G input / Y input
51 R/PRIN3 3rd R input / PR input
52 INSSW3 3rd RGB / YPBPR insertion input
V-output for YUV interface (general purpose switch
53 VOUT(SWO1)
output)
U-output for YUV interface (2nd RGB / YPBPR
54 UOUT(INSSW2)
insertion input)
55 YOUT Y-output (for YUV interface)
56 YSYNC Y-input for sync separator
Y-input for YUV interface (2nd G input / Y input or
57 YIN (G/YIN2/CVBS-Yx)
CVBS/YX input))
58 UIN (B/PBIN2) U-input for YUV interface (2nd B input / PB input)
V-input for YUV interface (2nd R input / PR input or CX
59 VIN (R/PRIN2/CX)
input)
60 VDDcomb supply voltage for comb filter (5 V)
61 VSScomb ground connection for comb filter
62 HOUT horizontal output
flyback input/sandcastle output or composite H/V
63 FBISO/CSY
timing output
64 SVM scan velocity modulation output
65 CVBSO/PIP CVBS / PIP output
66 AUDOUTHPR audio output for headphone channel (right signal)
67 AUDOUTHPL audio output for headphone channel (left signal)
68 AUDOUTLSR audio output for audio power amplifier (right signal)
69 AUDOUTLSL audio output for audio power amplifier (left signal)
70 C2/C3 chroma-2/3 input
71 CVBS3/Y3 CVBS3/Y3 input
72 AUDIOIN3R audio 3 input (right signal)
73 AUDIOIN3L audio 3 input (left signal)
75 AUDIOIN2R audio 2 input (right signal)
76 AUDIOIN2L audio 2 input (left signal)
77 C4 chroma-4 input
79 AUDIOIN4R audio-4 input (right signal)
80 AUDIOIN4L audio-4 input (left signal)
81 IFVO/SVO/CVBSI (2) IF video output / selected CVBS output / CVBS input
82 VP2 2nd supply voltage TV processor (+5 V)
83 AGC2SIF AGC capacitor second sound IF
84 VCC8V 8 Volt supply for audio switches
85 DVBO/FMRO (2) Digital Video Broadcast output / FM radio output
Digital Video Broadcast output / IF video output / FM
86 DVBO/IFVO/FMRO (2)
radio output
DTV R&D Europe 19

AGC sound IF / internal-external AGC for DVB

87 SIFAGC/DVBAGC (2)
applications
88 PLLIF IF-PLL loop filter
89 GND2 ground 2 for TV processor
QSS intercarrier output / AM output / deemphasis
QSSO/AMOUT/AUDEE
90 (front-end audio
M (2)
out)
91 DECSDEM decoupling sound demodulator
92 AUDOUTSR audio output for SCART/CINCH (right signal)
93 AUDOUTSL audio output for SCART/CINCH (left signal)
94 AUDIOIN5R audio-5 input (right signal)
95 AUDIOIN5L audio-5 input (left signal)
Automatic Volume Levelling / switch output / sound IF
input /
AVL/SWO/SSIF/
96 subcarrier reference output / external reference signal
REFO/REFIN (2)
input for I
signal mixer for DVB operation
97 EHTO EHT/overvoltage protection input
98 AGCOUT tuner AGC output
99 SIFIN2/DVBIN2 (2) SIF input 2 / DVB input 2
100 SIFIN1/DVBIN1 (2) SIF input 1 / DVB input 1
101 GNDIF ground connection for IF amplifier
102 IREF reference current input
103 VSC vertical sawtooth capacitor
104 VIFIN2 IF input 2
105 VIFIN1 IF input 1
106 VDRA vertical drive A output
107 VDRB vertical drive B output
108 EWD/AVL (1) East-West drive output or AVL capacitor
109 DECBG bandgap decoupling
110 SECPLL SECAM PLL decoupling
111 GND1 ground 1 for TV-processor
112 PH1LF phase-1 filter
113 PH2LF phase-2 filter
114 VP1 1st supply voltage TV-processor (+5 V)
115 DECDIG decoupling digital supply
V-guard input / I/O switch (e.g. 4 mA current sinking
116 VGUARD/SWIO capability for
direct drive of LEDs)
117 VSSA1 Ground
118 XTALOUT crystal oscillator output
119 XTALIN crystal oscillator input
120 VREF_POS_HPR positive reference voltage SDAC (3.3 V)
121 VREF_NEG_HPL+HPR negative reference voltage SDAC (0 V)
122 VREF_POS_LSR+HPR positive reference voltage SDAC (3.3 V)
123 VREF_NEG_LSL+HPL negative reference voltage SDAC (0 V)
124 VREF_POS_LSL positive reference voltage SDAC (3.3 V)
125 VDDA3(3.3V) supply (3.3 V)
126 VDDC4 digital supply to SDACs (1.8V)
127 VSSC4 Ground
128 VSSP2 Ground
DTV R&D Europe 20
4.1.4 FEATURES
Analogue Video Processing (all versions)

· Multi-standard vision IF circuit with alignment-free PLL demodulator
· Internal (switchable) time-constant for the IF-AGC circuit
· Switchable group delay correction and sound trap (with switchable centre frequency) for the
demodulated CVBS signal
· DVB/VSB IF circuit for preprocessing of digital TV signals.
· Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as
Y-input for Y/C signals. However, only 2 Y/C sources can be selected because the circuit has 2
chroma inputs. It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the
YUV interface and the RGB/YPRPB input are not needed.
· Automatic Y/C signal detector
· Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the
chrominance signal.
· Integrated luminance delay line with adjustable delay time
· Picture improvement features with peaking (with switchable centre frequency, depeaking,
variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring),
dynamic skin tone control, gamma control and blue- and black stretching. All features are
available for CVBS, Y/C and RGB/YPBPR signals.
· Switchable DC transfer ratio for the luminance signal
· Only one reference (24.576 MHz) crystal required for the TCG m-Controller, digital sound
processor, Teletext and the colour decoder
· Multi-standard colour decoder with automatic search system and various “forced mode”
possibilities
· Internal base-band delay line
· Indication of the Signal-to-Noise ratio of the incoming CVBS signal
· Linear RGB/YPBPR input with fast insertion.
· YUV interface. When this feature is not required some pins can be used as additional
RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input
(CVBS/YX and CX).
· Tint control for external RGB/YPBPR signals
· Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and
RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages.
· RGB control circuit with ‘Continuous Cathode Calibration’, white point and black level off-set
adjustment so that the colour temperature of the dark and the light parts of the screen can be
chosen independently.
· Contrast reduction possibility during mixed-mode of OSD and Text signals
· Adjustable ‘wide blanking’ of the RGB outputs
· Horizontal synchronization with two control loops and alignment-free horizontal oscillator
· Vertical count-down circuit
· Vertical driver optimized for DC-coupled vertical output stages
· Horizontal and vertical geometry processing with horizontal parallelogram and bow correction
and horizontal and vertical zoom
· Low-power start-up of the horizontal drive circuit
Analogue video processing (stereo versions)
· The low-pass filtered ‘mixed down’ I signal is available via a single ended or balanced output
stage.
Analogue video processing (mono versions)
· The low-pass filtered ‘mixed down’ I signal is available via a single ended output stage
Digital Video Processing (some versions)
· Double Window mode applications. It is possible to display a video and a text window or 2 text
DTV R&D Europe 21
windows in parallel.
· Linear and non-linear horizontal scaling of the video signal to be displayed.
Sound Demodulation (all versions)
· Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation.
· AM demodulator without extra reference circuit
· The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched
to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such
that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this
demodulator is optional for special applications. Normally the FM demodulators of the stereo
demodulator/decoder part are used (see below).
· The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second
sound channel can be demodulated. In such an application it is necessary that an external
bandpass filter is inserted.
· The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio
signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be
demodulated.
· Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF)
Audio Interfaces and switching (stereo versions with Audio DSP)
· Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for
HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R
channel. Finally 1 stereo SPEAKER output with digital controls.
· AVL (Automatic Volume Levelling) circuit for the headphone channel.
· Digital input crossbar switch for all digital signal sources and destinations
· Digital output crossbar for exchange of channel processing functionality
· Digital audio input interface (stereo I2S input interface)
· Digital audio output interface (stereo I2S output interface)
Audio interfaces and switching (AV stereo versions without Audio DSP)
· Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo
SPEAKER output with analogue volume control.
· Analogue mono AVL circuit at left audio channel
Audio interfaces and switching (mono versions)
· Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output
· AVL circuit
Stereo Demodulator and Decoder (full stereo versions)
· Demodulator and Decoder Easy Programming (DDEP)
· Auto standard detection (ASD)
· Static Standard Selection (SSS)
· DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation
· NICAM decoding (B/G, I, D/K and L standard)
· Two-carrier multistandard FM demodulation (B/G, D/K and M standard)
· Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound
· Adaptive de-emphasis for satellite FM
· Optional AM demodulation for system L, simultaneously with NICAM
· Identification A2 systems (B/G, D/K and M standard) with different identification time constants
· FM pilot carrier present detector
· Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option
· BTSC MPX decoder
· SAP decoder
· dbx® noise reduction (4)
· Japan (EIAJ) decoder
· FM radio decoder
· Soft-mute for DEMDEC outputs DEC, MONO and SAP
DTV R&D Europe 22
· FM overmodulation adaptation option to avoid clipping and distortion

Audio Multi Channel Decoder (stereo versions with Audio DSP)
· Dolby® Pro Logic® (DPL) (1)
· Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit
this feature an external DAC is required.
Volume and tone control for loudspeakers (stereo versions with Audio DSP)
· Automatic Volume Level (AVL) control
· Smooth volume control
· Master volume control
· Soft-mute
· Loudness
· Bass, Treble
· Dynamic Bass Boost (DBB) (2)
· Dynamic Virtual Bass (DVB) (3)
· BBE® Sound processing (4)
· Graphic equalizer
· Processed or non processed subwoofer
· Programmable beeper
Reflection and delay for loudspeaker channels (stereo versions with Audio DSP)
· Dolby® Pro Logic® Delay (1)
· Pseudo hall/matrix function
Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (stereo
versions with Audio DSP)
· Extended Pseudo Stereo (EPS) (5)
· Extended Spatial Stereo (ESS) (6)
· Virtual Dolby® Surround (VDS 422,423) (1)
· SRS 3D and SRS TruSurround® (4)
RDS/RBDS
· Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data
System (RBDS) signal
· RDS and RBDS block detection
· Error detection and correction
· Fast block synchronisation
· Synchronisation control (flywheel)
· Mode control for RDS/RBDS processing
· Different RDS/RBDS block information output modes
m-Controller
· 80C51 m-controller core standard instruction set and timing
· 0.4883 ms machine cycle
· maximum of 256k x 8-bit flash programmable ROM
· maximum of 8k x 8-bit Auxiliary RAM
· 12-level Interrupt controller for individual enable/disable with two level priority
· Two 16-bit Timer/Counter registers
· One 24-bit Timer (16-bit timer with 8-bit Pre-scaler)
· WatchDog timer
· Auxiliary RAM page pointer
· 16-bit Data pointer
· Stand-by, Idle and Power Down modes
· 24 general I/O
· 14 bits PWM for Voltage Synthesis Tuning
· 8-bit A/D converter with 4 multiplexed inputs
DTV R&D Europe 23
· 5 PWM (6-bits) outputs for analogue control functions

· Remote Control Pre-processor (RCP)
· Universal Asynchronous Receiver Transmitter (UART)
Data Capture
· Text memory up to 10 pages
· Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle
Page Table (SPT)
· Data Capture for US Closed Caption
· Data Capture for 525/625 line WST, VPS (PDC system A) and Wide Screen Signalling (WSS)
bit decoding
· Automatic selection between 525 WST/625 WST
· Automatic selection between 625 WST/VPS on line 16 of VBI
· Real-time capture and decoding for WST Teletext in Hardware, to enable optimized m-
processor throughput
· Automatic detection of FASTEXT transmission
· Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters
· Signal quality detector for video and WST/VPS data types
· Comprehensive teletext language coverage
· Vertical Blanking Interval (VBI) data capture of WST data
Display
· Teletext and Enhanced OSD modes
· Features of level 1.5 WST and US Close Caption
· 50Hz/60Hz display timing modes
· Two page operation for 16:9 screens
· Serial and Parallel Display Attributes
· Single/Double/Quadruple Width and Height for characters
· Smoothing capability of both Double Size, Double Width & Double Height characters
· Scrolling of display region
· Variable flash rate controlled by software
· Soft colours using CLUT with 4096 colour palette
· Globally selectable scan lines per row (9/10/13/16/) and character matrix [12x9, 12x10, 12x13,
12x16, 16x18, (VxH)]
· Fringing (Shadow) selectable from N-S-E-W direction
· Fringe colour selectable
· Contrast reduction of defined area
· Cursor
· Special Graphics Characters with two planes, allowing four colours per character
· 64 software redefinable On-Screen display characters
· 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic)
· G1 Mosaic graphics, Limited G3 Line drawing characters
· WST Character sets and Closed Caption Character set in single device
· SVM for Text
4.2 TDA8946J STEREO AUDIO AMPLIFIER
The TDA 8946J is a dual-channel audio power amplifier with an output power of 2 x 15 W at an 8
Ω load and a 18 V supply. The circuit contains two Bridges Tied Load (BTL) amplifiers with an
DTV R&D Europe 24

all-NPN output stage and standby/mute logic. The TDA8946J comes in a 17-pin DIL-bent-
SIL(DBS) power package.
4.2.1 FEATURES
Few external components

Fixed gain
Standby and mute mode
No on/off switching plops
Low standby current
High supply voltage ripple rejection
Outputs short-circuit protected to ground, supply and across the load
Thermally protected
Pin description
Pin Symbol Description

1 OUT1- negative loudspeaker terminal 1
2 GND1 ground channel 1
3 Vcc1 supply voltage channel 1
4 OUT1+ positive loudspeaker terminal 1
5 n.c. not connected
6 IN1+ positive input1
7 n.c. not connected
8 IN1- negative input1
9 IN2- negative input2
10 MODE mode selection input
11 SVR half supply voltage decoupling (ripple rejection)
12 IN2+ positive input2
DTV R&D Europe 25

Block diagram TDA8946J
DTV R&D Europe 26

4.3 TDA8358J VERTICAL AMPLIFIER
The TDA8358J are power circuit for use in 90° and 110° colour deflection systems for field
frequencies of 25 to 200Hz field frequencies, and for 4:3 and 16/9 picture tubes. The IC contains
a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge
output circuit allows DC coupling of the deflection coil in combination with single positive supply
voltages.
The east-west output stage is able to supply the sink current for a diode modulator circuit.
The IC is constructed in a Low Voltage DMOS(LVDMOS) process that combines bipolar, CMOS
and DMOS devices. DMOS transistors are used in the output stage because of the absence of
second breakdown.
4.3.1 TDA8358J
Features :
Few external components

Highly efficient fully DC-coupled vertical bridge output circuit
Vertical flyback switch with short rise and fal times
Built-in guard circuit
Thermal protection circuit
Improved EMC performance due to differential inputs
East-west output stage
DTV R&D Europe 27

Pinning

1 INA Positeve vertical input
2 INB Negative vertical input
3 VP Supply voltage
4 OUTB Vertical output voltage B
5 INEW East-west input voltage
6 VGND Vertical ground
7 EWGND East-west ground
8 OUTEW East-west output voltage
9 VFB Flyback supply voltage
10 OUTA Vertical output voltage A
11 GUARD Guard output voltage
12 FEEDB Input measuring resistor
13 COMP Input compensation current
Block diagram TDA8358J
DTV R&D Europe 28

4.4 TDA6107AJF
The TDA6107AJF includes three video output amplifiers and is intended to drive the three
cathodes of a colour CRT directly. The device is contained in a plastic DIL-bent-SIL 9-pin
medium power(DBS9MPF) package, and uses high-voltage DMOS technology.
To obtain maximum performance, the amplifier should be used with black-current control.
4.4.1 Features
Typical bandwidth of 5.5 MHz for an output signal of 60 Vpp
High slew rate of 900V/µs
No external components required
Very simple application
Single supply voltage of 200V
Internal reference voltage of 2.5 V
Fixed gain of 81.
Black-current stabilisation (BCS) circuit with voltage window from 1.8 to 6 V and current
window form 100uA to -10mA
Thermal protection
Internal protection against positive flashover discharges appearing on the CRT
4.4.2 Pin description

1 Vi(1) inverting input 1
4 GND ground (fin)
5 Iom black current measurement output
6 VDD supply voltage
7 VOC(3) cathode output 3
DTV R&D Europe 29

Block diagram TDA6107AJF
4.5 24WC16 - 16 KB EEPROM
Features :
16 Kbit serial I2C bus EEPROM
400KHz I2C Bus Compatible
supply voltage : 1.8 V to 6.0 V
Low Power CMOS Technology
1 Million Erase/Write cycles (minimum)
100 year data retention (minimum)
Pin description
Pin No. Name Description
1, 2, 3 A0, A1, A2 Device address – not used
5 SDA Serial Data/Address Input/Output
6 SCL Serial clock
7 WP Write control
8 Vcc Supply voltage
4 Vss Ground
The memory device is compatible with the I2C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit
unique device type identifier code (1010) in accordance with the I2C bus definition.
Serial Clock (SCL)

The SCL input is used to strobe all data in and out of the memory.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory.
DTV R&D Europe 30

4.6 STR – W6754
4.6.1 GENERAL DESCRIPTION
The STR-W6700 series is a Hybrid IC (HIC) designed for Quasi-Resonant type Switching Mold
Power Supply built-in a Power MOSFET and Control IC.
4.6.2 FEATURES
operation mode turns blocking oscillation by reducing output voltage at stand-by mode.
In addition to the existing Quasi-Resonant Operation, the Bottom-Skip Function is added in
order to be efficient from light to medium load.
Soft-Start Operation is provided at the SMPS start-up.
Switching noise is reduced by Step-Drive Function.
Avalanche energy of the MOSFET is guaranteed.
Overcurrent Protection (OCP), Overvoltage Protection (OVP), Overload Protection (OLP),
and Maximum ON-Time control circuits are incorporated.
It is possible to save the SMPS design time by utilizing the present designs and evaluation
processes.
4.6.3 BLOCK DIAGRAM
４
VCC
DRIV E D
Abnormal Reg １
＋ Reg& latch
－
Iconst R
Delay
Burst Q
Start Control
S
Stop
OVP Burst ３
S/GND
FB ６
＋
－
FB
R Q
Q S －
S ＋
OSC R OCP
MaxON BSD －
＋＋ BD
＋ OCP/BD
－
－７
OLP Bottom Selector
Soft Start Counter SS/OLP
５
DTV R&D Europe 31

4.6.4 PIN DESCRIPTION
Terminal
Pin No. Symbols Functions
Descriptions
1 D Drain Terminal MOSFET Drain
2 － Source/Grand MOSFET Source and
3 S/GND Terminal Ground
Control Circuit Power Supply
4 VCC Power Supply Terminal
Input
Overload Protection and
Delay at Overload/Soft-
5 SS/OLP Start set up Terminal Soft- Start Operation Time
set up
Constant Voltage Control
6 FB Feedback Terminal Signal Input, Blocking
Oscillation Control
Overcurrent Protection Overcurrent Detection
7 OCP/BD Input/Bottom Detection Signal Input / Bottom
Terminal Detection Signal Input
4.6.5 MOSFET ELECTRICAL CHARACTERISTICS

Ratings
Parameters Terminal Symbols Units Conditions
MIN TYP MAX
Drain-Source Voltage ※
1-3 VDSS 650 ― ― V
7
Drain Leakage Current 1-3 IDSS ― ― 300 µA ※6
ON Resistance ※7 1-3 RDS(ON) ― ― 0.73 Ω
Switching Time 1-3 ｔf ― ― Nsec
Channel – Internal Frame
Thermal Resistance ※7 ― θ ch-F ― ― ℃/Ｗ
DTV R&D Europe 32

4.6.6 ELECTRICAL CHARACTERISTICS
Ratings
Parameters Terminal Symbols Units
MIN TYP MAX
ower Supply Start-up Operation

Operation Start-up Voltage 4-3 VCC(ON) 18.2 V
Operation Stop Voltage 4-3 VCC(OFF) 9.6 V
Operation Circuit Current 4-3 ICC(ON) ― ― 6 mA
Non Operation Circuit Current 4-3 ICC(OFF) ― ― 100 µA
Oscillation Frequency 1-3 fOSC 22 kHz
Soft-Start Operation Stop Voltage 5-3 VSSOLP(SS) 1 V
Soft-Start Operation Charging Current 5-3 ISSOLP(SS) -450 µA
ormal Operation
Overcurrent Detection Threshold Voltage 7-3 VOCPBD(LIM) -0.95 V
Bottom-Skip Operation Threshold Voltage 1 7-3 VOCPBD(BS1) -0.66 V
Bottom-Skip Operation Threshold Voltage 2 7-3 VOCPBD(BS2) -0.44 V
OCP/BD Terminal Outflow Current 7-3 IOCPBD µA
Quasi-Resonant Operation Threshold Voltage 1 7-3 VOCPBD(TH1) 0.4 V
Quasi-Resonant Operation Threshold Voltage 2 7-3 VOCPBD(TH2) 0.8 V
Minimum Quasi-Resonant Signal Input Time 7-3 TOFF(MIN) ― ― 1 µsec
FB Terminal Threshold Voltage 6-3 VFB(OFF) 1.5 V
FB Terminal Inflow Current (Normal Operation) 6-3 IFB(ON) mA
tand-by Operation
Stand-by Operation Start-up Power Supply
4-3 VCC(S) 11.2 V
Voltage
Stand-by Power Supply Voltage Interval 4-3 VCC(SK) 1.5 V
Stand-by Non-Operational Circuit Current 4-3 ICC(S) 30 μ A
FB Stand-by Operation Threshold Voltage 6-3 VFB(S) V
FB Terminal Inflow Current (Stand-by) 6-3 IFB(S) µA
Minimum ON Time 1-3 TON(MIN) 1 µsec
otection Operation
Maximum ON Time 1-3 TON(MAX) 34 µS
OLP Operation Threshold Voltage 5-3 VSSOLP(OLP) 5 V
OLP Operation Charging Current 5-3 ISSOLP(OLP) -10 µA
Normal Operation Discharging Current 5-3 ISSOLP(NOR) 40 µA
OLP Delay Time 1-3 TOLP ms
OVP Operational Voltage 4-3 VCC(OVP) 27.5 V
Latch Circuit Holding Current ※10 4-3 ICC(H) ― ― 150 µA
Latch Circuit Releasing Power Supply Voltage ※
4-3 VCC(La.OFF) 7.3 V
10
DTV R&D Europe 33

5 CIRCUIT DESCRIPTION
5.1 BLOCK DIAGRAM
DTV R&D Europe 34

5.2 FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
5.2.1 Vision IF amplifier

The vision IF amplifier can demodulate signals with positive and megative modulation. The PLL
demodulator is completely alignment-free.
The VCO of the PLL circuit is internal and the grequency is fixed to the required value by using
the clock ftequency of the TCG u-Controller as a reference. The setting of the various
frequencies (e.g. 38, 38.9, 45.75 and 58.75MHz) can be made via the control bits IFA-IFC in
subaddress 2FH. Because of the internal VCO the IF circuit has a high immunity to EMC
interferences.
The output of the AFC detector can be read from output byte o4H and has a resolution of
7bit(25kHz per step). By means of this information a fast tuning algorithm can be designed.
The IC contains a group delay correction circuit which can be switched between the BG and a
uncompensated group delay response characteristic. This hasthe advantage that in multi-
standard receivers no compromise has to be made for the choice of the SAW filter. This group
delay corection is realised for the demodulated CVBS output signal. The IC contains in addition a
sound trap circuit with a switchable centre frequency.
5.2.2 QSS sound circuit

The sound IF amplifier is similar to the vision IF amplifier and has an external AGC decoupling
capacitor.
ThesinglereferenceQSSmixerisrealisedbyamultiplier. In this multiplier the SIF signal is converted

to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The
mixer output signal is suppliedtotheoutputviaahigh-passfilterforattenuation of the residual video
signals. With this system a high performance hi-fi stereo sound processing can be achieved.
TheAMsounddemodulatorisrealisedbyamultiplier.The modulated sound IF signal is multiplied in

phase with the limited SIF signal. The demodulator output signal is supplied to the output via a
low-pass filter for attenuation of the carrier harmonics.
SwitchingbetweentheQSSoutputandAMoutputismade by means of the AM bit in subaddress 33H.
5.2.3 FM demodulator
TheFMdemodulatorisrealisedasnarrow-bandPLL with internal loop filter, which provides the
necessary selectivity without using an external band-pass filter. To obtain a good selectivity a
linear phase detector and a constant input signal amplitude are required. For this reason the
intercarrier signal is internally supplied to the demodulator via a gain controlled amplifier and
AGC circuit. To improve the selectivity an internal bandpass filter is connected in front of the PLL
circuit.
The nominal frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5
MHz) by means of a calibration circuit which uses the clock frequency of the TCG(1)-Controller
as a reference. It is also possible to frequencies of 4.72 and 5.74Mhz so that a second sound
channel can be demodulated. In the latter application an external bandpass filter has to be
DTV R&D Europe 35

applied to obtain sufficient selectivity (the sound input can be activated by means of the setting of
CMB2-CMB0 bits in subaddress 4AH). The setting to the wanted frequency is realised by means
of the control bits FMA, FMB and FMC in the control bit 33H.
From the output status bytes it can be read whether the PL Lfrequency is inside or outside the
window and whether thePLL is in lock or not. With this information it is possible to make an
automatic search system for the incoming sound frequency. This can be realised by means of a
software loop which switches the demodulator to the various frequencies and then select the
frequency on which a lock condition has been found.
The amplitude deemphasis output signal changed with 6dB by means of the AGN bit. In this way
output signal differences between the 4.5 MHz standard (frequency deviation25 kHz) and the
other standards (frequency deviation50 kHz) can be compensated.
5.2.4 Audio input selector and volume contro
5.2.4.1 STEREO AND AV STEREO VERSIONS
The audio input selector circuit has 4 external stereo inputs, a stereo output for SCART/CINCH
and stereo outputs for headphone and audio power amplifiers. The selection is made with the
bits SAS2/0, SO2/0 and HPO2/0. AV stereo versions without Audio DSP have no headphone
output. The input signal selection for the volumecontrolledaudiooutputsisrealisedbytheHPO2/0
bits.
The gain from an external audio input to each of the (non-controlled) analog output is 0 or
+6dB(controlled by the DSG bit). A supply voltage of 5V allows input and output amplitude of
1VRMS full scale, as required to comply with the SCART specification, the audio supply voltage
must be 8V. In that case the gain of the audio amplifier must be doubled. This can be realised
with the DSG bit in subaddress 32H.
The circuit contains an analogue stereo volume control circuit with a control range of about 70dB.
This volume control circuit is used for the headphone channel (stereo versions with Audio DSP)
or for the main channel (AV stereo versions without Audio DSP). The analogue control circuit
also contains an Automatic Volume Levelling(AVL) function. When this function is activated it
stabilises the audio output signal to a certainl evel so that big fluctuations of the output power are
prevented.
5.2.4.2 MONO VERSIONS
The audio input selector circuit has 4 inputs for mono signals. The selection is made with the
HPO2/0 bits.
The circuit contains an analogue volume control circuit with a control range of about 70dB and an
AVL circuit.
5.2.5 CVBS and Y/C input signal selection
5.2.5.1 ALL VERSIONS
DTV R&D Europe 36

The Ics have 3 inputs for external CVBS signals. All CVBS inputs can be used as Y input for the
insertion of Y/C signals.However, the CVBS(Y)2 input has to be combined with the C3 input. It is
possible to add and extra CVBS(Y/C) input via the pins which are intended to be used for YUV
interface (or RGB/YPrPb input). The selection of this additional CVBS(Y/C) input is made via the
YC bit.
The function of the IFVO/SVO/CVBSI pin is determined by the SVO1/SVO0 bits. When used as
output a selection can be made between the IF video output signal or the selected CVBS signal
(monitor out). This pin can also be used as additional CVBS input. This signal is inserted in front
of the group delay / sound trap circuit. It is also possible to use the group delay and sound trap
circuit for the CVBS2 signal (via the CV2 bit).
For the CVBS(Y/C) inputs the circuit can detect whether a CVBS or Y/C signal is present on the
input. The result can be read from the status register (YCD bit in subaddress 03H) and this
information can be used to put the input switch in the right position (by means of the INA-IND bits
in subaddress 38H). The Y/C detector is only active for the CVBS(Y)3/C3, CVBS(Y)4/C4 and
CVBS(Y)x/Cx inputs. It is not active for the CVBS(Y)2/C3 input.
The video ident circuit can be connected to all video input signals. This ident circuit is
independent of the synchronisation and can be used to switch the synchronisation and can be
used to switch the presence of a video signal (via the VID bit). In this way a very stable OSD can
be realised. The result of the video ident circuit can be read from the output bit SID (subaddress
00).
5.2.6 Synchronisation circuit
The IC contains separator circuits for the horizontal and vertical sync pulses. To obtain an
accurate timing of the displayed picture the input signal of the sync separator is not derived from
the various CVBS/Y or RGB/YPrPb inputs but from the YOUT pin. For this reason the YOUT pin
must be capacitively coupled to the YSYNC pin. The delay between the various inputs and the
YOUT signal can have rather large differences (e.g. comb filter active or not). By choosing the
YOUT signal as input signal for the sync separator these delays have no effect on the picture
position. Only for RGB signals without sync on green the input of the sync separator has to be
connected to one of the CVBS inputs. This selection is made by means of the SYS bit.
The horizontal drive signal is obtained from an internal VCO which is running at a frequency of
25 MHz. This oscillator is stabilised to this frequency by using the clock signal coming from the
reference oscillator of the TCG -Controller.
To obtain a stable On-Screen-Display (OSD) under all conditions it is important that the first
control loop is switched off or set to low gain when no signal is available at the input. The input
signal condition is detected by the video identification circuit. The video identification circuit can
automatically switch first control loop to a low gain when no input signal is available. This mode is
obtained when the VID bit is set to “0”. When the VID bit is “1” the mode of the first control loop
can be switched by means of the FOA/FOB or POC bits.
For a good performance during normal TV reception (display of the front-end signal) various
connections are active between the vision IF amplifier and the synchronisation circuit (e.g. gating
pulses for the AGC detector and noise gating of the sync separator). These connections are not
allowed when external video signals are displayed. The switching of these connections can be
coupled to the input signal selection bits (INA-IND). This mode is obtained when the VDXEN bit
is “0”. Due to the input signal selector configuration it is possible that the internal CVBS signal is
DTV R&D Europe 37

available on one of the other CVBS inputs.In this condition the connections between the vision IF
amplifier and the synchronisation circuit can be switched on and off by means of the VDX bit.
The VDXEN bit must be set to “1” for this mode.
The vertical synchronisation is realised by means of a divider circuit.
5.2.7 Horizontal and vertical drive

The horizontal drive is switched on and off via the soft start/stop procedure. The soft start
function is realised by means of variation of the TON of the horizontal drive pulses. During the
soft-stop period the horizontal output frequency is doubled resulting in a reduction of the EHT so
that the picture tube capacitance can easily be discharged. In addition the horizontal drive circuit
has a ‘low-power start-up’ function.
The vertical ramp generator needs an external resistor and capacitor. For the vertical drive a
differential output current is available. The outputs must be DC coupled to the vertical output
stage.
The IC has the following geometry control functions:

Vertical amplitude
Vertical slope
S-correction
Vertical shift
Vertical zoom
Vertical scroll
Vertical linearity correction. When required the linearity setting for the upper and lower part
of the screen can have a different setting.
Horizontal shift
EW width
EW parabola width
EW upper and lower corner parabola correction
EW trapezium correction
Horizontal parallelogram and bow correction.
When the East-West geometry function is not required (e.g. for 90 picture tubes) the EW output
pin can be used for the connection of the AVL capacitor. This function is chosen by means of the
AVLE bit.
5.2.8 Chroma, luminance and feature processing
Someversionscontaina4H/2H(2D)adaptivePAL/NTSC comb filter. The comb filter is

automatically activated when standard CVBS signals are received.A signal is considered as
“standard signal” when a PAL or NTSC signal is identified and when the vertical divider is in the
modes ‘standard narrow window’ or ‘standard TV norm’.For non-standard signals and for
SECAM signals the comb filter is bypassed and the signal is filtered by means of bandpass and
trap filters.
The chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by
means of internal filters and are tuned to the right frequency by comparing the tuning frequency
with the reference frequency of the colour decoder.
DTV R&D Europe 38

The circuit contains the following picture improvement features:

Peaking control circuit. The peaking function can be activated for all incoming CVBS, Y/C
and RGB/YPrPb signals. Various parameters of the peaking circuit can be adapted by means
of the I2C-bus. The main parameters are:
- Peaking centre frequency (via the PF1/PF0 bits in subaddress 19H).

- Ratio of positive and negative peaks (via the RPO1/RPO0 bits in subaddress 47H). The
peaks in the direction “white” are the positive peaks.
- Ratio of pre- and aftershoots (via the RPA1/RPA0 bits in subaddress 47H).
Video dependent coring in the peaking circuit. The coring can be activated only in the low-
light parts of the screen. This effectively reduces noise while having maximum peaking in the
bright parts of the picture.
Black stretch. This function corrects the black level for incoming signals which have a
difference between the black level and the blanking level. The amount of stretching (A-A in
Fig. 72) and the minimum required back ground to activate the stretching can be set by
means of the I2C-bus (BSD/AAS in subaddress 45H).
Gamma control. When this function is active the transfer characteristic of the luminance
amplifier is made non-linear.Thecontrolcurvecanbeadaptedbymeans of I2C-bus settings (see
Fig. 74). It is possible to make the gamma control function dependent on the picture content
(Average Picture Level, APL). The effect is illustrated in Fig. 75. Previously this function was
mentioned under the name “white stretch function”.
Blue-stretch. This circuit is intended to shift colour near ‘white’ with sufficient contrast values
towards more blue to obtain a brighter impression of the picture.
Dynamic skin tone (flesh) control. This function is realised in the YUV domain by detecting
the colours near to the skin tone.
Scan-Velocity modulation output. Also the SVM function can be activated for all incoming
CVBS, Y/C and RGB/YPrPb signals. The delay between the RGB output signals and the
SVM output signal can be adjusted (by means of the SVM2-SVM0 bits in subaddress 48H)
so that an optimum picture performance can be obtained. Furthermore a coring function can
be activated. It is possible to generate Scan Velocity Modulation drive signals during the
display of ‘full screen’ teletext (not in mixed mode). Another feature is that the SVM output
signal can be made dependent on the horizontal position on the screen (parabola on the
SVM output).
5.2.9 Colour decoder
The ICs decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need
external reference crystals but has an internal clock generator which is stabilised to the required
frequency by using the clock signal from the reference oscillator of the TCG u -Controller.
Under bad-signal conditions (e.g. VCR-playback n feature mode), it may occur that the colour
killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is
possible to overrule the colour killer by forcing the colour decoder to the required standard and to
activate the FCO-bit (Forced Colour On) in subaddress3CH. The sensitivity of the colour decoder
for PAL and NTSC can be increased by means of the setting of the CHSE1/CHSE0 bits in
subaddress 3CH.
The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 3BH)
prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received.
The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal.
This has the advantage that the colour sensitivity is not affected by this function.
DTV R&D Europe 39

The SECAM decoder contains an auto-calibrating PLL demodulator which has two references,
viz: the divided reference frequency (obtained from the-Controller) which is used to tune the PLL
to the desired free-running frequency and the bandgap reference to obtain the correct absolute
value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period,
when the IC is in search or SECAM mode. The frequency offset of the B-Y demodulator can be
reduced by means of the SBO1/SBO0 bits in subaddress 3CH.
The base-band delay line is integrated. In devices without CVBS comb filter this delay line is also
active during NTSC to obtain a good suppression of cross colour effects. The demodulated
colour difference signals are internally supplied to the delay line. The baseband comb filter can
be switched off by means of the BPS bit (subaddress 3CH).
The subcarrier output is combined with a 3-level output switch (0 V, 2.1 V and 4.5 V). The output
level and the availability of the subcarrier signal is controlled by the CMB2-CMB0 bits.
5.2.10 RGB output circuit
In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The IC
has a YUV interface so that additional picture improvement ICs can be applied. To compensate
signal delays in the external YUV path the clamp pulse in the control circuit can be shifted by
means of the CLD bit in subaddress 44H. When the YUV interface is not required some of the
pins can be used for the insertion of RGB/YPrPb signals or as additional CVBS(Y)/C input. When
the YUV interface is not used one of the pins (VOUT) is transferred to general purpose output
switch (SWO1). The IC has also a YUV interface to th edigita ldie. Via this loop digital features
like “double window” are added.
A tint control is available for the base-band U/V signals. For this reason this tint control can be
activated for all colour standards. The signals for OSD and text are internally supplied to the
control circuit. The output signal has an amplitude of about 1.2V black-to-white at nominal input
signals and nominal settings of the various controls.
To obtain an accurate biasing of the picture tube the ‘Continuous Cathode Calibration’ system
has been included in these ICs. The system is slightly adapted compared with the previous
circuits. In the new configuration the cut-off level of the picture tube is controlled with a
continuous loop whereas the correction of the amplitude of the output signals is realised by
means of a digital loop. As a consequence the current measurement can be controlled from the-
Processor. The value of the “highcurrent”intheCCCloopcanbechosenviatheSLG0 and SLG1 bits
(subaddresses 42H and 46H). The gain control in the 3 RGB channels is realised by means of 7-
bit DACs. The total gain control range is6 dB. The change in amplitude at the cathodes of the
picture tube for one LSB is about 1.1 Vp-p. The setting of the control DAC is determined by the
following registers:
The white point setting of the R, G and B channel in subaddress 20H to 22H. This register
has a resolution of 6 bits and the control range in output signal amplitude is +/-3 dB.
The cathode drive setting (CL3-CL0 in subaddress 42H). This setting is valid for all channels,
there solution is 4 bits and the control range is +/-3 dB.
The gain setting of the R, G and B channel. During switch on this register is loaded with the
preset gain setting of subaddress 23H to 25H and when necessary it will be adapted by the
CCC control loop. These registers have a resolution of 7 bits. The control of the gain setting
is illustrated in table below.
DTV R&D Europe 40

WPR(GB) ‘0’ B5 B4 B3 B2 B1 B0 Max 64

CL ‘0’ B3 B2 B1 B0 ‘0’ ‘0’ Max 60
CCC-gain B6 B5 B4 B3 B2 B1 B0 Max 126
R(GB)-gain B6 B5 B4 B3 B2 B1 B0 Max 126
The setting of the gain registers of the 3 channels can be stored during switch off and can be
loaded again during switch-on so that the drive conditions are maintained.
When required the operation of the CCC system can be changed into a one-point black current
system. The switching between the 2 possibilities is realised by means of the EGL bit (EGL = 0)
in subaddress 42H. When used asone-point control loop the system will control the black level of
the RGB output signals to the ‘low’ reference current and not on the cut off point of the cathode.
In this way spreads in the picture tube characteristics will not be taken into account. In this
condition the settings of the “white point control registers”(subaddress 20H-22H) and the
“cathode drive level bits” (CL3 - CL0 in subaddress 42H) are added to the settings of the RGB
preset gain registers (subaddress 23H - 25H).
A black level off-set can be made with respect to the level which is generated by the black
current stabilization system. In this way different colour temperatures can be
obtainedforthebrightandthedarkpartofthepicture.The black level control is active on the Red and
the Green output signal. It is also possible to control the black level of the Blue and the Green
output signal (OFB bit = 1).
In the Vg2 adjustment mode (AVG=1) the black current stabilization system checks the output
level of the 3 channels and indicates whether the black level of the highest output is in a certain
window(WBC-bit) or below or above this window (HBC-bit). This indication can be read from the
status byte 01 and can be used for automatic adjustment of the Vg2 voltage during the
production of the TV receiver. During this test the vertical scan remains active so that the
indication of the 2 bits can be made visible on the TV screen.
The control circuit contains a beam current limiting circuit and a peak white limiting circuit. The
control is realised by means of a reduction of the contrast and brightness control settings. The
way of control (first contrast and then brightness or contrast and brightness in parallel) can be
chosen by means of the CBS bit (subaddress 44H). The peak white level is adjustable via the
I2C-bus.
To prevent that the peak white limiting circuit reacts on the high frequency content of the video
signal a low-passfilter is inserted in front of the peak detector. The circuit also contains a soft-
clipper which prevents that the high frequency peaks in the output signal become too high. The
difference between the peak white limiting level and the soft clipping level is adjustable via the
I2C-bus in a few steps.
During switch-off of the TV receiver a fixed beam current is generated by the black current
control circuit. This current ensures that the picture tube capacitance is discharged. During the
switch-off period the vertical deflection can be placed in an overscan position so that the
discharge is not visible on the screen.
A wide blanking pulse can be activated in the RGB outputs by means of the HBL bit in
subaddress 43H. The timing of this blanking can be adjusted by means of the bits WBF/R bits in
subaddress 26H.
DTV R&D Europe 41

5.2.11 I2C-BUS USER INTERFACE DESCRIPTION

The UOC III series is fully controlled via the I2C-bus. Control is exercised by writing data to one
or more internal registers. Status information can be read from a set of info registers to enable
the controlling microcontroller determine whether any action is required. The device has an I2C-
bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of
400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to
use it” (order number 939839340011). To avoid conflicts in a real application with other ICs
providing similar or complementary functions, there are two possible slave addresses available
which can be selected by the SVM pin(pin 65).
Possible slave address

SVM PIN SLAVE ADDRESS A6 TO A0
Scavem application 1000101
Tied 5 volts 1000111
The device will not respond to a ‘generalcall’ on the I2C-bus, i.e. when a slave address of
0000000 is sent by a master.
Write registers
Each address of the address space (see below) can only be written.
Correct operation is not guaranteed if registers in the range $FB to $FF will be addressed!
Read registers
The output registers of the TV processor are only available via auto-increment mode, no address
can be used and all registers must be read.
5.3 GENERAL DESCRIPTION OF THE TV SOUND OF SOUND PROCESSOR
The TV Sound Processor is a digital TV sound processor for analog multi-channel sound
systems in TV sets. It is based on a 24 bit DSP and designed to support several applications.
A new easy-to-use control concept was implemented for easiest configuration programming of
the very complex functionality of the TV Sound Processor. Pre-defined setups are available for
all implemented sound processing modes. Aloud speaker switching concept allows it to adapt the
pre-defined setups to the specific loudspeaker application.The built-in intelligence for pre-defined
standards and Auto Standard Detection (ASD) allows an easy setup of the demodulator and
decoder part.
The control concept for the audio processor is based on the following new features:
Pre-defined setups for the sound processing modes like Dolby® Pro Logic® and Virtual
Dolby® Surround (422, 423)
Flexible configuration of audio outputs to the loudspeaker configuration with an additional
output crossbar
Master volume function
The control concept for the demodulator and decoder (DEMDEC) is based on the following new
features:
Easy demodulator setup for all implemented standards with Demodulator and Decoder Easy
Programming (DDEP) for a pre-selected standard or combined with Auto Standard Detection
(ASD) for automatic detection of a transmitted standard
DTV R&D Europe 42

Automatic decoder configuration and signal routing depending on the selected or detected
standard
FM overmodulation adaptation option to avoid clipping and distortion
5.3.1 Supported standards
The multistandard capability of the TV Sound Processor covers all terrestrial TV sound standards,
FM Radio and satellite FM.
The AM sound of L/L' standard is normally demodulated in the 1st sound IF. The resulting AF
signal has to been tered into the mono audio input of the TV Sound Processor. A second
possibility is to use the AMdemodulator in the DEMDEC part, however this may result in limited
performance.
Korea has a stereo sound system similar to Europe. It is supported by the TV Sound Processor.
Differences include deviation, modulation contents and identification. It is based on M standard.
Other features of the DEMDEC are:

M/BTSC and N standards supported
M/Japan (EIAJ) supported
FM Radio stereo decoding
Alignment-free, fully digital system
For BTSC full dbx® performance
SAP demodulation (without dbx®) simultaneously with stereo decoding, or mono plus SAP
with dbx®
Line/pilot frequency selectable from 15.734 kHz and 15.625 kHz (or automatic detection /
auto search)
High selectivity for pilot detection, high robustness against high-frequent audio components
Pilot lock indicator
SAP detector
Separate noise detectors for stereo and SAP with adjustable threshold levels, hysteresis, and
automute function
An overview of the supported standards and sound systems and their key parameters is given in
the following tables.
The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2
carrier systems).
ANALOG 2-CARRIER SYSTEMS

[Table] Frequency modulation
CARRIER MODULATION BANDWIDTH/
SOUND FM DEVIATION(kHz)
STANDARD FREQUENCY DE-EMPHASIS
SYSTEM NOM./MAX./OVER SC1 SC2
(MHz) (kHz/us)
M Mono 4.5 15/25/50 Mono - 15/75
M A2+ 4.5/4.724 15/25/50 1/2(L+R) 1/2(L+R) 15/75(Korea)
B/G A2 5.5/5.742 27/50/80 1/2(L+R) R 15/50
I Mono 6.0 27/50/80 mono - 15/50
D/K(1) A2* 6.5/6.258 27/50/80 1/2(L+R) R 15/50
D/K(2) A2* 6.5/6.742 27/50/80 1/2(L+R) R 15/50
D/K(3) A2* 6.5/5.742 27/50/80 1/2(L+R) R 15/50
[Table] Identification for A2 systems

DTV R&D Europe 43
PARAMETER A2/A2* A2+ (KOREA)

Pilot frequency 54.6875kHz = 3.5 x line freq. 55.0699 kHz = 3.5 x line freq.
Stereo identification frequency 117.5 Hz = line freq / 133 149.9 Hz = line freq / 105
Dual indetification frequency 274.1 Hz = line freq / 57 276.0 Hz = line freq / 57
AM modulation depth 50% 50%
2-CARRIERSYSTEMSWITHNICAM
[Table] NICAM standards
SC1
MODULATION SC2
DEVIATION (MHz) DE- ROLL- NICAM
STANDARD FREQUENCY
TYPE INDEX(%) (kHz) NICA EMPAHSIS OFF (%) CODING
(MHz)
NOM./MAX. NAM./MAX. M
/OVER
B/G 5.5 FM - 27/50/80 5.85 J17 40 Note1
I 6.0 FM - 27/50/80 6.552 J17 100 Note1
D/K 6.5 FM - 27/50/80 5.85 J17 40 Note1
L 6.5 AM 54/100 - 5.85 J17 40 Note1
Note 1. See ‘EBU specification’ or equivalent specification.
5.4 FUNCTIONAL DESCRIPTION SOUND PROCESSOR
5.4.1 The UOC III TV Sound Concept
The UOCIII sound concept is implemented over the video processor and TCG-microcontroller.
Only relevant blocks, functions and signal flows for sound are given.
The tuner receives a RF signal and converts it to IF. Via appropriate SAW filters the SIF signal is
delivered to the QSS stage of the video processor and if channels according to standard L/L’ are
received also to the AM demodulator. The Quasi Split Sound demodulation generates the SSIF
or intercarrier signal. By the SSIF switch it is possible to choose between the internally derived
DTV R&D Europe 44

intercarrier and an external second SIF(2NDSIFEXT), e.g. an intercarrier coming from a PIP
frontend. In other applications a 10.7MHz radio IF or satellite FM may be connected to this input.
The selected SSIF passes some anti alias filtering, is amplified in an AGC amplifier (SSIF AGC)
and is then converted from analogue to digital (SSIF ADC).
The audio signal out of the AM demodulator is connected to the analogue crossbar at the video
processor. All other inputs to this multiplexer/audio switch come from external, either from a PIP
frontend or SCART/CINCH(AUDINx) or the DAC output signals from the digital controller. The
audio AD converters are digitising the audio signals foreseen for further digital processing. One
stereo output (AUDOUTS) is available for connections to SCART/CINCH sockets.
The sound part on the digital controller consists of the demodulator/decoder(DEMDEC), a digital
input crossbar, the digital audio processing for the loudspeaker and DAC channels, the I2S
processing and interfacing, a digital output crossbar as well as the DA conversion.
An auxiliary audio control (volume control, AUX audio contr.) is available on the video processor.
Here it is applied to the headphone channel.
The part of the concept located in the digital controller will be described in the next chapters.
5.4.2 Functional Overview Of the digital controller sound part
The digital controller sound part consists of the SSIFADC, audio ADCs, DEMDEC HW, the sound
DSP core, audio DACs and I2S interface hardware as shown in fig below. The DEMDEC part of
the Sound DSP is used for the decoder and partly demodulator tasks. The AUDIO part provides
the sound features, from the level adjust unit up to the output crossbar. Audio DACs and I2S
hardware are converting the processed signals to analogue or digital audio.
The SSIF signal is applied to the SSIF ADC for conversion and is then fed to the DEMDEC
hardware processing mainly for demodulation but also some decoding tasks. Remaining
DTV R&D Europe 45
decoding is done in the DEMDEC block of the Sound DSP. The DEMDEC processing will be
described in the next chapter.
The audio signals (AUD ADC IN) from the analogue crossbar pass the audio ADC and are fed
directly into the AUDIO part of the Sound DSP like the I2S signals, which is coming from I2S
processing hardware. After level adjust all signals from the DEMDEC and the I2S input are
available at the digital input crossbar. A special input is provided for the Noise/Silence Generator
needed for olby® Pro Logic® processing.
In standard TV applications the main channel signal(L,R) will be connected to the DAC2 for
reproduction at the speakers. With multichannel signals centre, surround or subwoofer channels
may be passed to the I2S outputs where external DACs may be applied. By this it is possible to
build Dolby Normal/Wide, Dolby Phantom Centre or Dolby 3 Stereo set-ups and also a VDS423
application.
5.4.3 Demodulator and decoder
INTRODUCTION
The TV sound processor provides an easy-to-use programming interface and built-in intelligence
for the demodulator and decoder part.
The sound demodulator is able to search for sound carriers and react to transmission mode
changes autonomously, without interaction of the micro controller software.
It is possible for a typical terrestrial TV application to setup the entire demodulator with
transmission of few control words.
The control interface still allows access to every detail, called demodulator expert mode, for
special applications such as satellite TV, more elaborated search algorithms etc.
The new TV Sound ProcessorDemodulator and

DecoderEasyProgramming(DDEP)interfaceprovides three possible approaches to setup the
demodulator and decoder parts:
Auto Standard Detection (ASD)
Static Standard Selection (SSS)
Demodulator and Decoder Expert Mode (DDXM)
MIXER
The digitized 2nd SIF input signal is fed to the mixers, which mix one or both input sound carriers
down to zero IF. The mixer frequency is derived by the standard setting (Easy Programming) or
in the Demodulator and Decoder Expert Mode (DDXM) by a 24-bit control word for each carrier.
For NICAM demodulation, a feedback signal is added to the control word of the second carrier
mixer to establish a carrier-frequency loop.
FMANDAMDEMODULATION
An FM or AM input signal is fed via a band-limiting filter to a one of two demodulators that can be
used for either FM or AM demodulation. Four filters with different bandwidth are available. The
DTV R&D Europe 46

output signal of the first demodulator can be used for further demodulation of multiplex signals
used in the BTSC, EIAJ and FM Radio standards.
FMIDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of the

pilot signal and narrow-band detection of the identification frequencies. The result is available via
the control bus interface. A selection can be made for three different modes that represent
different trade-offs between speed and reliability of identification. The mode is set by DDEP (for
FM two-carrier standards) or via expert mode. DDEP also performs automatic FM de-matrix
control in dependence on the identification.
FM/AMDECODING
A high-pass filter suppresses DC offsets from the FM/AM demodulators due to carrier frequency
offsets and supplies the monitor/peak function with DC values and an un-filtered signal, e.g. for
the purpose of carrier detection.
The audio bandwidth is approx. 15 kHz.
The de-emphasis function offers fixed settings for the supported standards (50s, 60s, 75s and
J17).
A matrix performs the de-matrixing of the A2 stereo, dual and mono signals to obtain the left (L)
and right (R) or language A and B signals.
FMPILOTCARRIERPRESENTDETECTOR
The TV Sound Processor provides FM A2 standard pilot carrier detection.
NICAMDEMODULATION
The NICAM signal is transmitted via DQPSK modulation at a bit rate of 728kBit/s. The NICAM
demodulator performs DQPSK demodulation and feeds the resulting bit stream and clock signal
to the NICAM decoder.
A timing loop controls the sample rate conversion circuitry to lock the sampling rate to the symbol
timing of the NICAM data.
NICAM DECODER
The NICAM decoder performs all decoding functions in accordance with theEBU NICAM 728
specification. After locking to the frame alignment word, the data is de scrambled by applying the
defined pseudo-random binary sequence; the NICAM decoder will then synchronize to the
periodic frame flag bitC0.
The status of the NICAM decoder can be read out from the NICAM status register by the user
(see the control-bus register description). The OSB bit indicates that the decoder has locked to
the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that
the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono
channel is identical to the sound conveyed by the NICAM channel. The error byte contains the
DTV R&D Europe 47

number of sound sample errors, resulting from parity checking, that occurred in the past 128ms
period. The Bit Error Rate (BER) can be calculated using the following equation;
During NICAM mode a switchable J17 de-emphasis is supplied.
NICAM AUTO-MUTE
If the Auto Standard Detection (ASD) or the Static Standard Detection (SSS) feature is activated
the following auto mute function is in effect.
If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes poor,
the built-in control automatically switches the output signal (DEC output) to FM channel 1. The
automatic switching depends on the NICAM bit error rate. The auto-mute function can be
disabled via the control bus.
This function is enabled by setting bit NIC_AMUTE to 0. Upper and lower error limits may be
defined by writing appropriate values to the corresponding control bits (NICLOERRLIM and
NICUPERRLIM). When the number of errors in a 128 ms period exceeds the upper error limit the
auto-mute function will switch the output sound from
NICAMtowhateversoundisonthefirstsoundcarrier(FM or AM). When the error count is smaller than
the lower error limit the NICAM sound is restored.
The auto-mute function can be disabled by setting bit NIC_AMUTE to 1. In this condition clicks
become audible when the error count increases; the user will hear a signal of degrading quality.
For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF. The
demodulated AM is provided by the internal IF processor. For applications with external IF
processing the external demodulated AM signal can be connected to the SCART/Mono input of
the TV Sound Processor. By setting the EXTAM bit, the auto-mute function will switch to the
audio ADC input signal named EXTAM instead of switching to the first sound carrier. The ADC
source selector should be set to internal AM mono signal or to the external SCART/mono input,
where the AM sound signal should be connected.
DTV R&D Europe 48

Caution
: In this Manual, some parts can be changed for improving. their performance without notice in the parts list. So, if you need the
latest parts information, please refer to PPL(Parts Price List)in Service Information Center(http://svc.dwe.co.kr)
MPORTANT SAFETY NOTICE
Components Identified by mark have special characteristics inportant for safety.
When replacing any of these components, use only manufacturers specified parts. In case of
Ordering these spare parts, please always add the complete Model-Type number to your order.
NO LOC PARTS CODE PARTS NAME PARTS DESCRIPTION REMARK

1 ZZ100 PTACPWL2950F ACCESSORY AS DTL-2950FZF-S
2 12000 48B5849C1001 TRANSMITTER REMOCON R-49C10
3 13000 4850Q00910 BATTERY AAA R03 SUPERGARD/ROCKET
4 14000 4858213801 BAG INSTRUCTION L. D. P. E. T0. 05X250X400
5 ZZ120 PTBCSHL2950S COVER BACK AS DTL-2950FZF-S
6 M211 4852174911 COVER BACK 2950 HIPS GY8301A
7 M211D 4857817630 CLOTH BLACK FELT T0.7 L=400
8 M541 4855415800 S/PLATE 150ART P/E FILM (C/TV)
9 M542 485580002207 LABEL SERIAL ART 90
10 ZZ130 PTCACAL2950FFS CABINET AS DTL-2950FZF-S
11 M201A 4856017752 SCREW CRT FIX 6X35 L120 YL 3CR
12 M201B 4856219502 WASHER RUBBER CR T2.0 BLACK
13 M201C 7178301051 SCREW TAPPTITE TT2 WAS 3X10 MFZN 3CR
14 M201D 4856017800 SCREW SPKR FIX SWRM+SECC 3CR
15 M211A 7172401652 SCREW TAPPTITE TT2 TRS 4X16 MFZN BK 3CR
16 M211B 7172401652 SCREW TAPPTITE TT2 TRS 4X16 MFZN BK 3CR
17 M352 2TF01612CL TAPE FILAMENT 12MMX55ME CLEAR
18 M481 485487071101 BUTTON POWER 2950 GY340A+SV2405BP
19 M481A 4856716000 SPRING 14Q1/M3 SWPA PIE0.5
20 M561 48556293SD02 MARK BRAND “DAEWOO 25” “29” “32” “NEW”
21 PWC1 4859906210 CORD POWER W/F 6-LO (LOMAX NEW)
22 SP01A 4856017800 SCREW SPKR FIX SWRM+SECC 3CR
23 SP02A 4856017800 SCREW SPKR FIX SWRM+SECC 3CR
24 V901 4859650560 “CRT (PHILIPS 29””)” A68ERS870X05 P38
25 ZZ131 58G0000182 COIL DEGAUSSING DC-29SF AL
26 ZZ132 48519A7810 CRT GROUND AS 2903S-1015-1P
27 ZZ200 PTFMSJL2950S MASK FRONT AS DTL-2950FZF-S
28 M201 4852092411 MASK FRONT 2950 HIPS GY
29 ZZ201 PTSPPWL2950F SPEAKER AS DTL-2950FZF-S
30 51100 4850704S28 CONN AS YH025-04+35089+ULW=600
31 SP01 48A8309300 SPEAKER SYSTEM SS-58126F04
32 SP02 48A8309300 SPEAKER SYSTEM SS-58126F04
33 ZZ280 PTSBMSL2950FF PCB SUB MANUAL AS DTL-2950FZF-S
34 C801 CL1UC3474M C LINE ACROSS 0.47MF 1J(UCVSNDF/SV
35 DL01 DH1L25RS— LED(RED) HI-L25RS
36 DL02 DH1L25G—- “LED (R,G-3 COLOR)” HI-L25G
37 F801 5FSCB4022R FUSE CERA SEMKO F4AH 4A 250V MF51
49
38 HP01 4859105240 JACK PHONO LGT1516-0100
39 I703 1TS0P4838Y IC PREAMP TSOP34838YA1
40 JPA3 4859105450 JACK PIN BOARD YSC03P-4120-9S
41 JPA4 4859105340 JACK S-VHS DSW-10 (STRAIGHT)
42 LF801 5PLF24A3— FILTER LINE LF-24A3
43 LF802 58C0000153 COIL CHOKE PFC 6001.0016B
44 M201E 7178301051 SCREW TAPPTITE TT2 WAS 3X10 MFZN 3CR
45 M231 485233251102 PANEL CTRL 2950 ABS GY
46 M231A 7178301051 SCREW TAPPTITE TT2 WAS 3X10 MFZN 3CR
47 M351 485356811101 HOLDER SENSOR 2950 GY340A(SILVER)
48 M491 485496331101 BUTTON CTRL 2950 ABS GY
49 M551 485555530001 DECO SENSOR 2950 GPPS GY9304AT
50 P702A 4850703N43 CONNECTOR YH025-03+YBH250-03+ULW=500
51 P703A 4850704S02 CONN AS YH025-04+YST025+ULW=200
52 P801 4859287320 CONN WAFER MKS2822 (LOMAX NEW TYPE)
53 P803 4859238620 CONN WAFER YPW500-02
54 PA01A 4850712S05 CONNECTOR YH025-12+YBNH250-12+ULW=400
55 SW801 5S40101146 SW POWER PUSH SS-160-7-B
56 ZZ200 PTSBJBL2950FF PCB SUB EYE LET AS DTL-2950FZF-S
57 E1 4856310300 EYE LET BSR T0.2 (R1.6) SMALL
64 ZZ200 PTSBJRL2950FF PCB SUB RADIAL AS DTL-2950FZF-S
65 C690 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5*11) TP
67 C770 CEXF1C101V C ELECTRO 16V RSS 100MF (6.3X11) TP
68 CA21 CCXB1H472K C CERA 50V B 4700PF K (TAPPING)
69 F801A 4857415001 CLIP FUSE PFC5000-0702
70 F801B 4857415001 CLIP FUSE PFC5000-0702
71 Q506 T2SC5343Y- TR 2SC5343Y
72 Q507 T2SA1980Y- TR 2SA1980Y
73 SW700 5S50101Z90 SW TACT SKHV10910A
79 Z601 5PXF1B471M FILTER EMI CFI 06 B 1H 470PF
50
83 ZZ200 PTSBJAL2950FF PCB SUB AXIAL AS DTL-2950FZF-S
84 10 2TM14006LB TAPE MASKING 3M #232 6.0X2000M (W/O GLUE)
85 20 2TM10006LB TAPE MASKING 3M #232-MAP-C 6.2X2000M (WITH GLUE)
86 A001 4859816424 PCB SUB 246X246(120X210X2)D1B
87 C608 CCZB1H471K C CERA 50V B 470PF K (AXIAL)
89 CA20 CCZB1H472K C CERA 50V B 4700PF K (AXIAL)
90 J001 85801060GY WIRE COPPER 1/0.6 TIN COATING
91 L701 5CPZ560K02 COIL PEAKING 56UH 3.5MM K (LAL02TB)
92 R530 RD-AZ151J- R CARBON FILM 1/6 150 OHM J
94 R532 RD-AZ102J- R CARBON FILM 1/6 1K OHM J
96 R608 RD-2Z151J- R CARBON FILM 1/2 150 OHM J
104 R802 RD-2Z824J- R CARBON FILM 1/2 820K OHM J
105 RA21 RD-AZ750J- R CARBON FILM 1/6 75 OHM J
107 ZZ290 PTMPMSL2950FF PCB MAIN MANUAL AS DTL-2950FZF-S
108 10 2193110001 SOLDER WIRE SN-3.0AG (NP303T) 3.0
109 20 2193110002 SOLDER WIRE SN-3.0AG-0.5CU (DHB-RMA3)
110 30 2291050620 FLUX SOLDER DF-2810U (0.810)
111 40 2291050314 FLUX SOLVENT IM-1000
112 C315 CEXF2A470V C ELECTRO 100V RSS 47MF (10X16) TP
113 C402 CMYH3C602J C MYLAR 1.6KV 6000PF J (BUP)
114 C404 CMYH3C752J C MYLAR 1.6KV 7500PF J (BUP)
115 C408 CMYE2G184J C MYLAR 400V PU 0.18MF J
116 C412 CEXF2E479V C ELECTRO 250V RSS 4.7MF (10X16)TP
118 C440 CMXE2G223J C MYLAR 400V PU 0.022MF J
119 C499 CEYD1H689W C ELECTRO 50V RHD 6.8MF (16X35.5)
120 C604 CEXF1E102V C ELECTRO 25V RSS 1000MF (13X20) TP
121 C805 CEYD2G181D C ELECTRO 400V FHS 180MF
122 C812 CH1BFE472M C CERA AC AC400V 4700PF M U/C/V
123 C813 CEYF2E470V C ELECTRO 250V RSS 47MF (16X25
124 C814 CEXF2E101V C ELECTRO 250V RSS 100MF 18X35.5
125 C820 CCXR3D221K C CERA 2KV R 220PF K125C
127 C840 CEXF1C332V C ELECTRO 16V RSS 3300MF
51
128 C861 CEXF1E102C C ELECTRO 25V RUS 1000MF 13X20 TP
130 C965 CBXB3D102K C CERA SEMI 2KV BL(N) 1000PF K (T)
132 CP01 CMXF2G124J C MYLAR MPP 400V 0.12MF J
133 CP02 CMXE2J822J C MYLAR 630V PL 8200PF J
134 CP04 CEXF1H221V C ELECTRO 50V RSS 220MF (10X16) TP
135 CP07 CMYF2J154J C MYLAR 630V MPP 0.15MF J
136 D403 DBY228—— DIODE BY228
137 D404 DBYW76—— DIODE BYW76
138 D407 DRGP30J—- DIODE RGP30J
139 D820 DBYW76—— DIODE BYW76
141 I301 1TDA8358J- IC VERTICAL TDA8358J
142 I301A 4857028227 HEAT SINK AL EX ANODIZING
143 I301B 7174301051 SCREW TAPPTITE TT2 RND 3X10 MFZN 3CR
144 I502 124LC16B1B IC MEMORY 24LC16B1B
145 I602 1TDA8946J- IC AUDIO TDA8946J
146 I602A 4857028215 HEAT SINK AL EX NO ANODOZING
148 I801 1STRW6754- IC POWER STR-W6754
149 I801A 4857024600 HEAT SINK AL EX B/K
151 I804 1LTV817C— IC PHOTO COUPLER LTV-817C
152 I806 1DP142—— IC ERROR AMP DP142
153 I820 1S7805P1C- IC REGULATOR S7805PIC 5.0V 1.0A
154 I822 1K78R08—- IC REGULATOR KIA78R08API
155 I822A 4857026900 HEAT SINK AL EX
157 I823 1LD1117V33 IC REGULATOR LD1117AV33 3.3V TO-220
158 I823A 4857026900 HEAT SINK AL EX
160 I824 1S7805P1C- IC REGULATOR S7805PIC 5.0V 1.0A
161 I901 1TDA6107AJ IC VIDEO TDA6107AJF
162 I901A 4857031100 HEAT SINK A1050P-H24 T2.0
164 IA01 1MM1118—- IC A/V SWITCH MM1118
165 JPA1 4859200401 SOCKET RGB SR-21A1 (ANGLE TYPE)
166 JPA2 4859200401 SOCKET RGB SR-21A1 (ANGLE TYPE)
167 L401 58H0000101 COIL H-LINEARITY TRL-220D
168 L402 58C7070085 COIL CHOKE TLN-3062A
169 L403 58C0000026 COIL BEAD HC-4035
170 P401 4850705N18 CONNECTOR BIC-05T-25T+ULW=400
171 P403 4859242420 CONN WAFER YFW800-04
172 P501 4850705N14 CONNECTOR BIC-05T-25T+ULW=500
52
173 P601 4859231720 CONN WAFER YW025-04
174 P701 4859231720 CONN WAFER YW025-04
175 P702 4859231620 CONN WAFER YW025-03
176 P703 4859231720 CONN WAFER YW025-04
177 P802 4859242220 CONN WAFER YFW800-02
178 P804 4859238620 CONN WAFER YPW500-02
179 P804A 4850702N08 CONN AS YPH500-02+YLT500+USW=300
180 P903 4859238620 CONN WAFER YPW500-02
181 PA01 4859235520 CONN WAFER YW025-12
182 Q401 T2SD2578— TR 2SD2578
183 Q401A 4857027611 HEAT SINK AL EX BK
184 Q401B 7174300851 SCREW TAPPTITE TT2 RND 3X8 MFZN 3CR
185 Q807 TKTA1659AY TR KTA1659AY
186 QP03 T1RF640N— FET IRF640NPBF
187 QP03A 4857026902 HEAT SINK AL EX BK
188 QP03B 7174300851 SCREW TAPPTITE TT2 RND 3X8 MFZN 3CR
189 R393 RS02Y189JS R M-OXIDE FILM 2W 1.8 OHM J SMALL
191 R406 RS02Y221JS R M-OXIDE FILM 2W 220 OHM J SMALL
192 R801 DJ5020M270 POSISTOR J502P72D070M270
195 R819 RX07B339JP R CEMENT 7W 3.3 OHM J BEN 15MM 4P
197 R842 RS02Y240JS R M-OXIDE FILM 2W 24 OHM J SMALL
199 R920 RS01Y249J- R M-OXIDE FILM 1W 2.4 OHM J
200 SCT1 4859303530 SOCKET CRT PCS629-03C
201 T401 50D19A1—- TRANS DRIVE TD-19A1
202 T402 50H0000312 FBT 1362.5067
203 T801 50M4818A1- TRANS SMPS 2094.0118A
204 U100 4859724930 TUNER VARACTOR UV1316/AI-4
205 X501 5XJ24R576E CRYSTAL QUARTZ HC-49/S 24.576MHZ 30PPM
206 Y801 5SC0101003 SW RELAY DG12D1-0(M)-II 1C-1P
207 Z101 5PK3953M— FILTER SAW K3953M
208 Z102 5PK9650M— FILTER SAW K9650M
209 ZZ200 PTMPJBL2950FF PCB MAIN EYE LET AS DTL-2950FZF-S
211 E03 4856310600 EYE LET BSR 2.3(R2.3) BIG
212 E04 4856310600 EYE LET BSR 2.3(R2.3) BIG
213 E05 4856310600 EYE LET BSR 2.3(R2.3) BIG
214 E06 4856310600 EYE LET BSR 2.3(R2.3) BIG
215 E07 4856310600 EYE LET BSR 2.3(R2.3) BIG
216 E08 4856310600 EYE LET BSR 2.3(R2.3) BIG
217 E09 4856310600 EYE LET BSR 2.3(R2.3) BIG
53
218 E10 4856310600 EYE LET BSR 2.3(R2.3) BIG
219 E13 4856310600 EYE LET BSR 2.3(R2.3) BIG
220 E14 4856310600 EYE LET BSR 2.3(R2.3) BIG
221 E15 4856310600 EYE LET BSR 2.3(R2.3) BIG
222 E16 4856310600 EYE LET BSR 2.3(R2.3) BIG
223 E17 4856310600 EYE LET BSR 2.3(R2.3) BIG
224 E18 4856310600 EYE LET BSR 2.3(R2.3) BIG
225 E19 4856310600 EYE LET BSR 2.3(R2.3) BIG
226 E20 4856310600 EYE LET BSR 2.3(R2.3) BIG
246 E56 4856310600 EYE LET BSR 2.3(R2.3) BIG
247 E57 4856310600 EYE LET BSR 2.3(R2.3) BIG
248 E58 4856310600 EYE LET BSR 2.3(R2.3) BIG
249 E59 4856310600 EYE LET BSR 2.3(R2.3) BIG
250 ZZ200 PTMPJ2L2950FF PCB CHIP MOUNT B AS DTL-2950FZF-S
251 I501 1TDA21HF01 IC MICOM FLASH TDA12021H1/N1/F01
252 ZZ200 PTMPJRL2950FF PCB MAIN RADIAL AS DTL-2950FZF-S
254 C104 CCXB1H102K C CERA 50V B 1000PF K (TAPPING)
255 C106 CEXF1H220V C ELECTRO 50V RSS 22MF (5X11) TP
258 C305 CEXF1E221V C ELECTRO 25V RSS 220MF (8X11.5) TP
259 C313 CMXM2A104J C MYLAR 100V 0.1MF J TP
260 C320 CBXF1H104Z C CERA SEMI 50V F 0.1MF Z (TAPPING)
54
263 C370 CCXF1H473Z C CERA 50V F 0.047MF Z (TAPPING)
264 C401 CEXF1H101V C ELECTRO 50V RSS 100MF (8*11.5) TP
271 C430 CXSL2H560J C CERA 500V SL 56PF J (TAPPING)
272 C501 CEXF1C470V C ELECTRO 16V RSS 47MF (5X11) TP
278 C510 CEXF1E101V C ELECTRO 25V RSS 100MF (6.3X11) TP
279 C513 CMXL1J224J C MYLAR 63V MEU 0.22MF J TP
284 C521 CMXM2A222J C MYLAR 100V 2200PF J TP
288 C526 CMXL1J224J C MYLAR 63V MEU 0.22MF J TP
291 C529 CMXL1J154J C MYLAR 63V MEU 0.15MF J
292 C534 CEXF1H229V C ELECTRO 50V RSS 2.2MF (5X11) TP
298 C540 CMXL1J104J C MYLAR 63V MEU 0.1MF J
55
327 C661 CMXM2A224J C MYLAR 100V 0.22MF J
328 C662 CMXM2A224J C MYLAR 100V 0.22MF J
334 C803 CCXF3A472Z C CERA 1KV F 4700PF Z (T)
335 C804 CCXF3A472Z C CERA 1KV F 4700PF Z (T)
336 C806 CCXR3A102K C CERA 1KV R 1000PF (T) 125C
341 C831 CEXF1H330V C ELECTRO 50V RSS 33MF (6.3X11) TP
351 C866 CCXR3A471K C CERA 1KV R 470PF K 125C
56
353 C968 CMXL2E104K C MYLAR 250V 0.1MF K MEU TP
354 CA10 CCXB1H102K C CERA 50V B 1000PF K (TAPPING)
355 CA30 CEXF1H100V C ELECTRO 50V RSS 10MF (5X11) TP
356 CA31 CEXF1H100V C ELECTRO 50V RSS 10MF (5X11) TP
357 CA32 CEXF1C470V C ELECTRO 16V RSS 47MF (5X11) TP
358 CP05 CEXF1H100V C ELECTRO 50V RSS 10MF (5X11) TP
359 CP06 CCXB3A102K C CERA 1KV B 1000PF K (TAPPING)
360 G900 4SG0DX0001 SPARK GAP SSG-102-A1 (1.0KV)
365 L802 58CX430599 COIL CHOKE AZ-9004Y 940K TP
366 Q120 T2SC5343Y- TR 2SC5343Y
367 Q402 T2SD1207T- TR 2SD1207-T (TAPPING)
368 Q501 T2SC5343Y- TR 2SC5343Y
369 Q502 T2SA1980Y- TR 2SA1980Y
370 Q503 T2SC5343Y- TR 2SC5343Y
371 Q504 T2SA1980Y- TR 2SA1980Y
372 Q508 T2SC5343Y- TR 2SC5343Y
373 Q509 T2SC5343Y- TR 2SC5343Y
374 Q513 T2SA1980Y- TR 2SA1980Y
375 Q515 TH2N7000— TR H2N7000
376 Q601 T2SC5343Y- TR 2SC5343Y
377 Q602 T2SA1980Y- TR 2SA1980Y
378 Q809 T2SC5343Y- TR 2SC5343Y
379 Q810 T2SC5343Y- TR 2SC5343Y
380 Q812 TKTC3203Y- TR KTC3203-Y
381 Q813 T2SA1980Y- TR 2SA1980Y
382 Q814 T2SC5343Y- TR 2SC5343Y
383 Q815 T2SA1980Y- TR 2SA1980Y
384 Q816 T2SC5343Y- TR 2SC5343Y
385 QP01 T2SD1207T- TR 2SD1207-T (TAPPING)
386 QP02 T2SC5343Y- TR 2SC5343Y
387 R331 RN02B331JS R METAL FILM 2W 330 OHM J SMALL
388 R399 RN02B689JS R METAL FILM 2W 6.8 OHM J SMALL
389 R400 RN02B689JS R METAL FILM 2W 6.8 OHM J SMALL
392 R450 RN02B752JS R METAL FILM 2W 7.5K OHM J SMALL
397 RP04 RN02B753JS R METAL FILM 2W 75K OHM J SMALL
57
398 RP05 RN02B333JS R METAL FILM 2W 33K OHM J SMALL
407 ZZ200 PTMPJAL2950FF PCB MAIN AXIAL AS DTL-2950FZF-S
408 10 2TM14006LB TAPE MASKING 3M #232 6.0X2000M (W/O GLUE)
409 20 2TM10006LB TAPE MASKING 3M #232-MAP-C 6.2X2000M (WITH GLUE)
410 A001 4859812493 PCB MAIN CP-650 DTL-2950 (330X246 D1B)
412 C123 CCZB1H103K C CERA 50V B 0.01MF K (AXIAL)
416 C512 CBZF1H104Z C CERA SEMI 50V F 0.1MF Z (AXIAL)
418 C531 CCZF1H103Z C CERA 50V F 0.01MF Z
58
445 CA27 CZSL1H470J C CERA 50V SL 47PF J
447 CA33 CCZB1H103K C CERA 50V B 0.01MF K (AXIAL)
448 D101 DBAT85—— DIODE BAT85 (TAPPING)
449 D102 DBA282—— DIODE BA282
450 D313 D1N4937G— DIODE 1N4937G
451 D405 D1N4937G— DIODE 1N4937G
453 D410 D1N4004S— DIODE 1N4004S
454 D411 D1N4004S— DIODE 1N4004S
455 D414 D1N4004S— DIODE 1N4004S
456 D450 D1N4937G— DIODE 1N4937G
457 D501 DBAT85—— DIODE BAT85 (TAPPING)
458 D503 DTZX3V9B— DIODE ZENER TZX3V9B (TAPPING)
460 D520 D1N4148—- DIODE 1N4148 (TAPPING)
466 D801 DLT2A05G— DIODE LT2A05G
470 D805 D1N4937G— DIODE 1N4937G
471 D806 D1N4937G— DIODE 1N4937G
472 D807 D1N4937G— DIODE 1N4937G
473 D808 DUZ6R8BM— DIODE ZENER UZ 6.8B 500MW SILICON
477 D830 D1N4937G— DIODE 1N4937G
478 D831 D1N4937G— DIODE 1N4937G
479 D904 DBAV21—— DIODE BAV21 (TAPPING)
483 DA01 85801060GY WIRE COPPER 1/0.6 TIN COATING
484 DA02 DTZX5V6B— DIODE ZENER TZX5V6B (TAPPING)
485 DA03 85801060GY WIRE COPPER 1/0.6 TIN COATING
59
492 DP01 D1N4937G— DIODE 1N4937G
493 DP02 D1N4148—- DIODE 1N4148 (TAPPING)
495 DP04 DTZX12C—- DIODE ZENER TZX12C (TAPPING)
496 DP05 DTZX5V1B— DIODE ZENER TZX5V1B (TAPPING)
498 DP07 DTZX12C—- DIODE ZENER TZX12C (TAPPING)
499 I805 DTZX33B—- DIODE ZENER TZX33B (TAPPING)
60
61
62
626 L101 85801060GY WIRE COPPER 1/0.6 TIN COATING
627 L350 5MC0000100 COIL BEAD MD-5 (HC-3550)
629 L505 5CPZ479K02 COIL PEAKING 4.7UH 3.5MM K (LAL02TB)
647 LA30 5CPZ479K02 COIL PEAKING 4.7UH 3.5MM K (LAL02TB)
656 R131 RD-AZ472J- R CARBON FILM 1/6 4.7K OHM J
660 R350 RN-AZ2201F R METAL FILM 1/6 2.2K OHM F
661 R351 RN-AZ2201F R METAL FILM 1/6 2.2K OHM F
662 R370 RD-4Z159J- R CARBON FILM 1/4 1.5 OHM J
667 R401 RD-4Z272J- R CARBON FILM 1/4 2.7K OHM J
63
678 R500 85801060GY WIRE COPPER 1/0.6 TIN COATING
705 R541 RN-AZ3902F R METAL FILM 1/6 39K OHM F
64
65
772 R811 RC-2Z825KP R CARBON COMP 1/2 8.2M OHM K
788 R833 RD-2Z105J- R CARBON FILM 1/2 1M OHM J
796 R913 RC-2Z102K- R CARBON COMP 1/2 1K OHM K
802 R996 RD-2Z105J- R CARBON FILM 1/2 1M OHM J
807 RA05 RD-AZ103J- R CARBON FILM 1/6 10K OHM J
66
809 RA07 RD-AZ332J- R CARBON FILM 1/6 3.3K OHM J
832 RP01 RD-AZ823J- R CARBON FILM 1/6 82K OHM J
833 RP02 RD-4Z101J- R CARBON FILM 1/4 100 OHM J
834 RP03 RD-AZ102J- R CARBON FILM 1/6 1K OHM J
835 RP06 RD-4Z222J- R CARBON FILM 1/4 2.2K OHM J
840 RP14 RD-2Z474J- R CARBON FILM 1/2 470K OHM J
841 RP16 RD-2Z474J- R CARBON FILM 1/2 470K OHM J
842 ZZ140 PTPKCPL2950F PACKING AS DTL-2950FZF-S
843 10 6520010200 STAPLE PIN #3417 ALL
844 M681 2TP06575CL TAPE OPP T0.065XW75X500M CLEAR
845 M801 DMP5012400 BOX DTL-2950
846 M811 485819C900DN PAD DOWN 2950 EPS
847 M811A 485819C900UP PAD UP 2950 EPS
848 M821 4858215601 BAG P.E EFOAM T0.5X1600X1270 25” - 28”
67
-2950_ F .sch-1 - Thu Apr 13 19:02:29 2006
DAEWOO ELECTRONICS CORP.
686, AHYEON-DONG, MAPO-GU,
SEOUL, KOREA.
C.P.O. BOX 8003 SEOUL KOREA
PRINTED DATE : APR. 2006

Daewoo Dtl-2950 K GB Chassis Cp-650

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P/N : TCP650FEF0

DOCUMENT HISTORY .................................................................................................................3

5.2.4.1 STEREO AND AV STEREO VERSIONS............................................................36

DTV R&D Europe 2

VERSION DATE COMMENTS

DTV R&D Europe 3

TV standard PAL - SECAM B/G D/K, PAL I/I, SECAM L/L’

1.1.2 EURO-SCART 1 (21 Pin)

DTV R&D Europe 4

11 Green Input 0.7 Vpp ± 0.1V, Impedance 75Ω

DTV R&D Europe 5

1.2 CHANNEL/FREQUENCY TABLE

CHANNEL EUROPE CCIR FRANCE GB(IRELAND) EAST OIRT

DTV R&D Europe 6

C46 671.25 671.25 671.25 671.25

DTV R&D Europe 7

S18 280.25 136.00 295.25 280.25

DTV R&D Europe 8

X-RAY RADIATION PRECAUTION

PRODUCT SAFETY NOTICE

DTV R&D Europe 9

3.1 MICROCONTROLLER CONFIGURATION : SERVICE MODE

1 - Select PR. number 91

To exit SERVICE menu press menu key or Std By key.

Pr Up/Down remote keys : cycle through the service items available.

Order Setting In Indication Default setting

DTV R&D Europe 10

3.3 MICROCONTROLLER CONFIGURATION : OPTION BITS

DTV R&D Europe 11

3.6 NVM default setting

2 - Entering into "FACTORY" mode.

3 - Entering into "NVM EDITOR" mode.

4 - Navigation in "NVM EDITOR" mode.

The data can be adjusted between 0 and 63.

5 - Exit "NVM EDITOR" mode.

6 - Exit "FACTORY" mode.

DTV R&D Europe 12

NVM DATA for CP-650

DTV R&D Europe 13

3.7 TV SET ALIGNMENT

3.7.5 HORIZONTAL PICTURE CENTRING

DTV R&D Europe 14

CORNER B & CORNER T

4.1 UOC III Series

• Adaptive digital (4H/2H) PAL/NTSC combfilter

4.1.1 IC MARKING AND VERSION

DTV R&D Europe 16

4.1.2. BLOCK DIAGRAM

DTV R&D Europe 17

QFP 128pin Symbol Short Description

DTV R&D Europe 18

DTV R&D Europe 19

AGC sound IF / internal-external AGC for DVB

Analogue Video Processing (all versions)

· FM overmodulation adaptation option to avoid clipping and distortion

· 5 PWM (6-bits) outputs for analogue control functions

4.2 TDA8946J STEREO AUDIO AMPLIFIER

DTV R&D Europe 24

Few external components