L11 f08

EE247
Lecture 11
• Data converters
– Areas of application
– Data converter transfer characteristics
– Sampling, aliasing, reconstruction
– Amplitude quantization
– Static converter error sources
• Offset
• Full-scale error
• Differential non-linearity (DNL)
• Integral non-linearity (INL)
EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 1
Material Covered in EE247

Where are We?
9 Filters
– Continuous-time filters
• Biquads & ladder type filters
• Opamp-RC, Opamp-MOSFET-C, gm-C filters
• Automatic frequency tuning
– Switched capacitor (SC) filters
• Data Converters
– D/A converter architectures
– A/D converter
• Nyquist rate ADC- Flash, Pipeline ADCs,….
• Oversampled converters
• Self-calibration techniques
• Systems utilizing analog/digital interfaces

Converter Applications
Data Converter Basics

Analog Input
• DSPs benefited from device scaling
Analog
Preprocessing
Filters
• However, real world signals are still
A/D
analog: Conversion
?
– Continuous time
000
– Continuous amplitude DSP ...001...
110
• DSP can only process: D/A

Conversion
?
– Discrete time
– Discrete amplitude Analog
Æ Need for data conversion from Postprocessing
Filters
analog to digital and digital to
analog Analog Output

A/D & D/A Conversion
A/D Conversion
D/A Conversion
Data Converters
• Stand alone data converters

– Used in variety of systems
– Example: Analog Devices AD9235 12bit/ 65Ms/s
ADC- Applications:
• Ultrasound equipment
• IF sampling in wireless receivers
• Various hand-held measurement equipment
• Low cost digital oscilloscopes

Data Converters
• Embedded data converters
– Integration of data conversion interfaces along
with DSPs and/or RF circuits Æ Cost, reliability,
and performance
– Main issues
• Feasibility of integrating sensitive analog functions in a
technology typically optimized for digital performance
• Down scaling of supply voltage as a result of downscaling of
feature sizes
• Interference & spurious signal pick-up from on-chip digital
circuitry and/or high frequency RF circuits
• Portable applications dictate low power consumption
Embedded Converters
Example: Typical Cell Phone
Contains in integrated form:
• 4 Rx filters
• 4 Tx filters
Dual Standard, I/Q
• 4 Rx ADCs
• 4 Tx DACs
Audio, Tx/Rx power
• 3 Auxiliary ADCs
control, Battery charge
• 8 Auxiliary DACs control, display, ...
Total: Filters Æ 8
ADCs Æ 7
DACs Æ 12

D/A Converter Transfer Characteristics
MSB
• An ideal digital-to- b1
analog converter: b2
Vo or Io
…….…
– Accepts digital inputs D/A
b1-bn
bN
– Produces either an LSB
analog output voltage
or current Nomenclature:
– Assumption (will be N = # o f b it s
revisited) VF S = fu ll sc a l e o ut p ut
• Uniform, binary digital Δ = min . step size → 1LS B
encoding VF S
Δ=
• Unipolar output 2N
V
ranging from 0 to VFS o r N = lo g2 F S → re so lu t io n
Δ
D/A Converter Transfer Characteristics

MSB
N = # of bit s b1
b2
Vo or Io
…….…
VFS = f u l l s cal e o u t p u t
D/A
Δ = m i n . st ep s i z e → 1L S B
bN
VFS LSB
Δ=
2N
N bi
V0 = VFS ∑
i =1 2
i
N ot e : D ( bi = 1,all i )
→ Vomax = VFS − Δ
N ⎛ 1 ⎞
→ Vomax = VFS ⎜ 1 −
= Δ × ∑ b i × 2 N −i , b i = 0 or 1 ⎝ 2N ⎠
⎟
i =1
binary-weighted

D/A Converter
Exampe: D/A with 3-bit Resolution
Example: for N=3 and VFS=0.8V MSB LSB

b1 b2 b3
input codeÆ 101
1 0 1
Find the output value V0
V0 = Δ ( b1 × 22 + b2 × 21 + b3 × 20 )
D/A
The n : Δ =VFS / 23 = 0. 1V
→ V0 = 0 .1V (1 × 22 + 0 × 21 + 1 × 20 ) =
→ V0 = 0.5V V0
N
Not e : M SB → VFS / 2 & LSB → VFS / 2
Ideal 3-Bit D/A Transfer Characteristic

Analog
• Ideal DAC Output
VFS
introduces
no error! Ideal Response
• One-to-one
mapping
from input to VFS /2
output Step Height (1LSB =Δ)
VFS /8
Digital Input
000 001 010 011 100 101 110 111
Code

A/D Converter Transfer Characteristics
MSB
• An ideal analog-to-digital b1
converter: b2
…….…
– Accepts analog input in the
form of either voltage or
Vin A/D
current
bN LSB
– Produces digital output either
in serial or parallel form N = # of bits
VFS = f ull sc ale output
– Assumption (will be revisited)
• Unipolar input ranging from 0 Δ = min. re solv able input → 1LSB
to VFS
VFS
• Uniform, binary digital Δ=
encoding 2N
V
or N = log2 FS → re solution
Δ
Ideal A/D Transfer Characteristic

Example: 3Bit A/D Converter
Digital
• Ideal ADC
Output
introduces error
with max peak- 111
to-peak: 110
Æ(+-1/2 Δ)
101
Δ = VFS /2 N
100
N= # of bits
011
• This error is 010

called
``quantization 001 1LSB Analog
error`` input
000
0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
VFS

Non-Linear Data Converters
• So far data converter characterisitics studied

are with uniform, binary digital encoding
• For some applications to maximize dynamic

range non-linear coding is used e.g. Voice-
band telephony,
– Small signals Æ larger # of codes
– Large signals Æ smaler # of codes
Example: Non-Linear A/D Converter

For Voice-Band Telephony Applications
Non-linear ADC and DAC Coder Output
used in voice-band (DIGITAL)
CODECs
• To maximize dynamic
range without need for
large # of bits
-VFS -VFS/2 -VFS/4
• Non-linear Coding Coder Input
scheme called A-law & (ANALOG)
μ-law is used
SEGMENT
• Also called companding #
Ref: P. R. Gray, et al. "Companded
pulse-code modulation voice codec SIGN STEP
using monolithic weighted capacitor BIT #
arrays," IEEE Journal of Solid-State
Circuits, vol. 10, pp. 497 - 499,
December 1975.

Data Converter Performance Metrics
• Data Converters are typically characterized by static, time-domain,
& frequency domain performance metrics :
– Static
• Offset
• Full-scale error
• Differential nonlinearity (DNL)
• Integral nonlinearity (INL)
• Monotonicity
– Dynamic
• Delay, settling time
• Aperture uncertainty
• Distortion- harmonic content
• Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR)
• Idle channel noise
• Dynamic range & spurious-free dynamic range (SFDR)
Typical Sampling Process

C.T. ⇒ S.D. ⇒ D.T.
Continuous time
Time
Physical
Signals
Sampled Data
(e.g. T/H signal)
Clock
"Memory
Discrete Time
Content"

Discrete Time Signals
• A sequence of numbers (or vector) with discrete index
time instants
• Intermediate signal values not defined

(not the same as equal to zero!)
• Mathematically convenient, non-physical
• We will use the term "sampled data" for related signals

that occur in real, physical interface circuits
Uniform Sampling
y(kT)=y(k)
t= 1T 2T 3T 4T 5T 6T ...
k= 1 2 3 4 5 6 ...
• Samples spaced T seconds in time

• Sampling Period T ⇔ Sampling Frequency fs=1/T
• Problem: Multiple continuous time signals can yield
exactly the same discrete time signal (aliasing)

Data Converters
• ADC/DACs need to sample/reconstruct to

convert from continuous-time to discrete-time
signals and back
• Purely mathematical discrete-time signals are
different from "sampled-data signals" that
carry information in actual circuits
• Question: How do we ensure that
sampling/reconstruction fully preserve
information?
Aliasing
• The frequencies fx and nfs ± fx, n integer, are
indistinguishable in the discrete time domain
• Undesired frequency interaction and

translation due to sampling is called aliasing
• If aliasing occurs, no signal processing
operation downstream of the sampling
process can recover the original continuous
time signal!

Frequency Domain Interpretation
Amplitude
Continuous
Time
Signal scenario
before sampling
fin fs /2 fs 2fs …….. f
Discrete
Signal scenario Amplitude Time
after sampling Æ DT
0.5 f/fs
ÆSignals @ nfS ± fmax__signal fold back into band of interest Æ Aliasing
Brick Wall Anti-Aliasing Filter

Amplitude Filter
Continuous
Time
0 fs 2fs ... f
Discrete
Time
0 0.5 f/fs
Sampling at Nyquist rate (fs=2fsignal) Æ required brick-wall anti-aliasing filters

Practical Anti-Aliasing Filter
Desired Parasitic
Signal Tone
Continuous Attenuation
Time
0 B fs/2 fs-B fs ... f
Discrete
Time
0 B/fs 0.5 f/fs
• Practical filter: Nonzero "transition band"

• In order to make this work, we need to sample faster than 2x the
signal bandwidth
• "Oversampling"
Data Converter
Classification
• fs > 2fmax Nyquist Sampling
– "Nyquist Converters"
– Actually always slightly oversampled (e.g. CODEC fsigmax =3.4kHz &
ADC sampling 8kHz Æ fs /fmax=2.35)
– Requires anti-aliasing filtering prior to A-to-D conversion
• fs >> 2fmax Oversampling

– "Oversampled Converters"
– Anti-alias filtering is often trivial
– Oversampling is also used to reduce quantization noise, see later
in the course...
• fs < 2fmax Undersampling (sub-sampling)

Sub-Sampling
Amplitude
BP Filter
Continuous
Time
0 fs ... f
Discrete
Time
0 0.5 f/fs
• Sub-sampling Æ sampling at a rate less than Nyquist rate Æ aliasing
• For signals centered @ an intermediate frequency Æ Not destructive!
• Sub-sampling can be exploited to mix a narrowband RF or IF signal down
to lower frequencies
Nyquist Data Converter Topics

• Basic operation of data converters
– Uniform sampling and reconstruction
– Uniform amplitude quantization
• Characterization and testing

• Common ADC/DAC architectures
• Selected topics in converter design
– Practical implementations
– Compensation & calibration for analog circuit non-idealities
• Figures of merit and performance trends

Where Are We Now?
Analog Input
• We now know how to Analog Anti-Aliasing

Preprocessing Filter
preserve signal
A/D Sampling
information in CTÆDT Conversion (+Quantization)
transition 000
DSP ...001...
110
D/A
• How do we go back from Conversion
?
DTÆ CT? Analog
Postprocessing
Analog Output
Ideal Reconstruction
x(k) x(t)
⇒
• The DSP books tell us:

∞
sin( 2πBt )
x(t ) = ∑ x(k ) ⋅ g (t − kT )
k = −∞
g (t ) =
2πBt
• Unfortunately not all that practical...

Zero-Order Hold Reconstruction
1 • How about just

creating a staircase,
0.6 i.e. hold each discrete
Amplitude
time value until new

0.2 information becomes
available?
-0.2
• What does this do to
-0.6 the frequency content
sampled data
of the signal?
-1 after ZOH
0 10 20 30
Time [μs]
• Let's analyze this in
two steps...
DTÆ CT: Infinite Zero Padding
Time Domain Frequency Domain
DT sequence ... ...

0.5 f /fs
Infinite
Zero padded ... ... f /fs
Interpolation:
0.5fs 1.5fs 2.5fs
CT Signal
Next step: pass the samples through a sample & hold stage (ZOH)

Hold Pulse Tp=Ts Transfer Function
1
sin(Tπ fsin(
Ts )πfT )
| H ( f ) |= p p
0.8 | H ( f ) |= π f Ts
abs(H(f)) Ts πfT p
0.6
0.4
0.2
0
0 0.5 1 1.5 2 2.5 3
f /fs
ZOH Spectral Shaping

1
Continuous Time X(k)

0.5
Pulse Train
Spectrum
0
0 0.5 1 1.5 2 2.5 3
1
ZOH Transfer
Function 0.5 ZOH
("Sinc Shaping")
0
0 0.5 1 1.5 2 2.5 3
1
ZOH output,
Spectrum of 0.5
Staircase
Approximation
0
0 0.5 1 1.5 2 2.5 3
f / fs

Smoothing Filter
1
• Order of the filter
Filter out the high required is a
0.8 frequency content function of
associated with oversampling ratio
staircase shape of the
0.6 signal
• High oversampling
helps reduce filter
0.4
order requirement
0.2
0
0 0.5 1 1.5 2 2.5 3
f / fs
Summary
• Sampling theorem fs > 2fmax, usually dictates

anti-aliasing filter
• If theorem is met, CT signal can be recovered
from DT without loss of information
• ZOH and smoothing filter reconstruct CT
signal from DT vector
• Oversampling helps reduce order &
complexity of anti-aliasing & smoothing filters
Next Topic
Analog Input
Anti-Aliasing
• Done with "Quantization Analog
Preprocessing Filter
in time" A/D
Sampling
(+Quantization)
Conversion
000
• Next: Quantization in DSP

...001...
110
amplitude D/A D/A+ZOH

Conversion
Smoothing
Analog
Filter
Postprocessing
Analog Output
Ideal ADC ("Quantizer")

• Accepts & analog input &
generates it’s digital Ideal converter with infinite # of bits
representation ADC characteristics
Digital Output Code
7
• Quantization step: 6
5
Δ (= 1 LSB) 4
3
• Full-scale input range: 2
1
-0.5Δ … (2N-0.5)Δ 0
-1 0 1 2 3 4 5 6 7 8
VFS
• E.g. N = 3 Bits ADC Input Voltage [ Δ]
Æ VFS= -0.5Δ to 7.5Δ

Quantization Error
• Quantization errorÆ Difference between analog input and
digital output of the ADC converted to analog via an ideal
DAC
• Called:
Quantization error
Residue
Quantization noise
Residue
Vin .. Ideal - Σ εq (Vin )
ADC ..
. DAC +
Quantization Error
7 ideal converter with infinite bits
Quantization error [LSB] Digital Output Code
6 ADC characteristics
• For an ideal ADC: 5
4
• Quantization error is 3
2
bounded by –Δ/2 … +Δ/2 1
for inputs within full-scale 0
-1 0 1 2 3 4 5 6 7 8
range
0.5
ADC Model 0
Vin Dout -0.5
+
εq (Vin ) -1 0 1 2 3 4 5 6 7 8
ADC Input Voltage [Δ]

ADC Dynamic Range
• Assuming quantization noise is much larger
compared to circuit generated noise:
Full Scale Signal Power
D.R.Maximum = 10 log
Quantization Noise Power
• Crude assumption: Same peak/rms ratio for signal
and quantization noise!
Peak Full Scale
D.R.Maximum = 20 log
Peak Quantization Noise
V
= 20 log FS = 20 log 2 N = 6.02 × N [ dB ]
Δ
Question: What is the quantization noise power?
Quantization Error
Assume Vin is a slow ramp signal with amplitude equal to ADC full-scale
Vin_Ramp
VFS
Quantization
Time
error [LSB]
Δ/2
Time
0
−Δ/2
Note: Ideal ADC quantization error waveformÆ periodic and also ramp

Quantization Error Derivation
Need to find the rms value for quantization error waveform:
+T / 2 + Δ / 2k Quantization
1 2 Δ 2
ε eq2 =
T
∫ (k × t )
−T / 2
dt =
k
∫ (k × t )
−Δ / 2k
dt error
εq=k.t
2 + Δ / 2k
Δ×k Δ/2
=
k
∫
−Δ / 2k
t2 d t
Δ/2k
Δ2
→ ε eq2 = Æ Independent of k −Δ/2k 0 Time
12
Δ −Δ/2
→ ε eq =
12
In general above equation applies if:
• Input signal much larger than 1LSB
• Input signal busy
• No signal clipping
Quantization Error PDF

• Probability density function • Zero mean
(PDF) Uniformly distributed from • Variance
–Δ/2 … +Δ/2 provided that:
– Busy input
+Δ / 2 2
– Amplitude is many LSBs e Δ2
– No overload
e2 = ∫ de = 12
−Δ / 2 Δ
• Not Gaussian!
PDF 1/Δ
Ref: W. R. Bennett, “Spectra of quantized
signals,” Bell Syst. Tech. J., vol. 27, pp.
446-72, July 1988.
B. Widrow, “A study of rough amplitude
quantization by means of Nyquist
sampling theory,” IRE Trans. Circuit
-Δ/2 +Δ/2 error Theory, vol. CT-3, pp. 266-76, 1956.

Signal-to-Quantization Noise Ratio
• If certain conditions the quantization error can be viewed as being
"random", and is often referred to as “noise”
• In this case, we can define a peak “signal-to-quantization noise ratio”,

SQNR, for sinusoidal inputs:
2
1 ⎛ 2N Δ ⎞ e.g. N SQNR
⎜ ⎟ 8 50 dB
2 ⎜⎝ 2 ⎟⎠
SQNR = = 1.5 × 22N 12 74 dB
Δ2 16 98 dB
12 20 122 dB
= 6.02N + 1.76 dB Ac curate for N>3
• Real converters do not quite achieve this performance due to other

sources of error:
– Electronic noise
– Deviations from the ideal quantization levels
ADC
SNR Measurement
20log(SNR) SQN R peak = 6.02N + 1.76 dB

Ideal
Realistic
6dB/octave
0dB
Vin [dB]
Dynamic Range

Static Ideal Macro Models
DAC
Din Vout
ADC
Vin Dout Æ +-0.5LSB ambiguity
+ε
q
Cascade of Data Converters

ADC DAC
Vin Vout
+
εq
DAC ADC
Din
Dout
+
εq

Static Converter Errors
Deviation of converter characteristics
from ideal:
– Offset
– Full-scale error
– Differential nonlinearity Æ DNL
– Integral nonlinearity Æ INL
Offset Error
ADC DAC
Ref: “Understanding Data Converters,” Texas Instruments Application Report

SLAA013, Mixed-Signal Products, 1995.

Full-Scale Error
ADC Ideal full-scale
point DAC Ideal full-scale
Actual full-scale point point
Full-scale
error
Full-scale
error
Actual
full-scale
point
Offset and Full-Scale Error
Note: ADC characteristics

Æ For further 7 ideal converter
Digital Output Code
measurements 6
Full-scale
(DNL, INL) error
5
connecting the
endpoints & 4
deriving ideal 3
codes based on
2
the non-ideal
endpoints 1
Offset error
eliminates 0
offset and full-
scale error -1 0 1 2 3 4 5 6 7 8
ADC Input Voltage [LSB]

Offset and Full-Scale Errors
• Alternative specification in % Full-Scale = 100% * (#

of LSB value)/ 2N
• Gain error can be extracted from offset & full-scale
error
• Non-trivial to build a converter with extremely good
full-scale/offset specs
• Typically full-scale/offset error is most easily
compensated by the digital pre/post-processor
• More critical: Linearity measuresÆDNL, INL
ADC Differential Nonlinearity
DNL = deviation ADC Transfer Curve

8
Real
of code width from Ideal
7
Δ (1LSB) -0.4 LSB DNL error
Digital Output Code
1. Endpoints 5
connected
4
3
2. Ideal
characteristics 2 0 LSB DNL error
derived
eliminating offset 1
+0.4 LSB DNL error
& full-scale error 0
0 1 2 3 4 5 6 7 8
3. DNL measured
ADC Input Voltage [Δ]
• Ideal ADC transitions point equally spaced by 1LSB
• For DNL measurement, offset and full-scale error is

eliminated
• DNL [k] (a vector) measures the deviation of each

code from its ideal width
• Typically, the vector for the entire code is reported
• If only one DNL # is reported that would be the worst

case
Example
Offset, Full-Scale Error, Gain,& DNL
A 3bit ADC is designed to have an ideal: Ideal Real
LSB=0.1V Æ VFS=0.8V Transition
transition transition
#
The measured transitions levels for the end point [V] point [V]
product is shown in the table, compute offset, full-
scale, gain error, & DNL 1 0.05 0.02
1- Offset: (real transition-ideal)= -0.03V, 2 0.15 0.15
in LSBÆ -0.03/0.1= -0.3LSB
2- Full-scale error (real last transition-ideal) 3 0.25 0.2
= 0.68-0.65=0.03V
in LSBÆ 0.03/0.1=+0.3LSB 4 0.35 0.37
3- LSB after correcting for offset & full-scale 5 0.45 0.42
error:
LSB= (Last transition-first transition)/(2N-2) 6 0.55 0.5
LSB= (0.68-0.02)/6=0.11V
7 0.65 0.68

Example
Code Code Width DNL
VFS= 2Nx0.11V=0.88V
# Width [V] [LSB] [LSB]
4-Gain relative to ideal
Gain=0.8/0.88=0.9 0 - -
1 0.13 1.18 0.18

Find all code widths 2 0.05 0.45 -0.55
Width[k]=Transition[k+1]-
Transition[k] 3 0.17 1.55 0.55
-Divide code width by LSBÆW[k] 4 0.05 0.45 -0.55
5 0.08 0.73 -0.27

5- Find DNL:
6 0.18 1.64 0.64
DNL[k]=W[k]-LSB
7 - -

Example
Code DNL
1 Max.
# [LSB]
DNL
0 -
0.5
1 0.18
DNL [LSB]
0 2 -0.55
3 0.55
-0.5 4 -0.55
5 -0.27
-1
0 1 2 3 4 5 6 7 6 0.64
Code # 7 -

Examples
ADC characteristics Note: As input increases at a
8 Ideal Converter 8
point output decreases
7 7 instead of increase:
Digital Output Code

6 6 ÆNon-monotonic
Digital Output Code
5 5
4 4
3 3
2 Missing code 2
(+0.5/-1 LSB DNL) Non-monotonic
1 1 (> 1 LSB DNL)
0 0
-1 0 1 2 3 4 5 6 7 8 9 -1 0 1 2 3 4 5 6 7 8 9
ADC Input Voltage [Δ] ADC Input Voltage [Δ]
ADC DNL
• DNL=-1 implies missing code
• For an ADC DNL < -1 not possible Æ undefined
• Can show:
al l i
∑ DN L[i ] = 0
• For a DAC possible to have DNL < -1

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EE247

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 1

Material Covered in EE247

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 2

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 3

Data Converter Basics

• DSP can only process: D/A

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 4

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 5

• Stand alone data converters

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 6

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 7

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 8

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 9

D/A Converter Transfer Characteristics

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 10

Example: for N=3 and VFS=0.8V MSB LSB

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 11

Ideal 3-Bit D/A Transfer Characteristic

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 12

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 13

Ideal A/D Transfer Characteristic

• This error is 010

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 14

• So far data converter characterisitics studied

• For some applications to maximize dynamic

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 15

Example: Non-Linear A/D Converter

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 16

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 17

Typical Sampling Process

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 18

• Intermediate signal values not defined

• Mathematically convenient, non-physical

• We will use the term "sampled data" for related signals

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 19

• Samples spaced T seconds in time

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 20

• ADC/DACs need to sample/reconstruct to

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 21

• Undesired frequency interaction and

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 22

ÆSignals @ nfS ± fmax__signal fold back into band of interest Æ Aliasing

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 23

Brick Wall Anti-Aliasing Filter

Sampling at Nyquist rate (fs=2fsignal) Æ required brick-wall anti-aliasing filters

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 24

0 B fs/2 fs-B fs ... f

0 B/fs 0.5 f/fs

• Practical filter: Nonzero "transition band"

• fs >> 2fmax Oversampling

• fs < 2fmax Undersampling (sub-sampling)

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 26

Nyquist Data Converter Topics

• Characterization and testing

• Figures of merit and performance trends

EECS 247 Lecture 11: Introduction to Data Converters © 2008 H. K. Page 28

• We now know how to Analog Anti-Aliasing