Parasitics in VLSI Circuits

and the Role of Layout Verification

N.P. van der Meijs, A.J. van Genderen and T. Smedes
Delft University of Technology, Faculty of Electrical Engineering
P.O. Box 5031, 2600 GA Delft, the Netherlands

Abstract 2 IC Interconnection Modeling

Integrated circuits consist of active devices The electromagnetic behavior of IC intercon-
and an interconnection network fabricated on nections is governed by Maxwell’s equations.
a semi-conducting substrate. The properties Because of the complexity of solving these
of the interconnections and the substrate are equations, approximations are needed. An
increasingly important factors affecting the important approximation leads to the model-
performance and operation of the circuit as ing of IC interconnections as a set of lossy
a whole, amplifying the need for layout verifi- coupled transmission lines. They are usu-
cation. In this paper, we discuss the behavior ally considered otherwise ideal, i.e. linear,
of IC interconnections and substrates, their frequency-independent, without skin effect,
electrical significance, and what constitutes etc. Except for diffused conductors, this is
an effective model for them. We conclude by usually an accurate approximation of IC in-
reviewing the increased importance and new terconnections when the operating frequen-
requirements of post-layout design verifica- cies are below 1 Ghz. However, in many
tion. cases (depending on e.g. the source, load,
line length and frequency), much simpler ap-
proximations are also accurate. In this sec-
1 Introduction
tion, we will discuss the applicability of such
The properties of IC interconnections and the approximations.
substrate are increasingly important factors For that purpose, let us first introduce the fol-
affecting the performance and operation of lowing notation:
an IC. They must be considered in the IC de-
l Length of an interconnection.
sign loop. A failure to do so may result in
r, c, h Resistance, capacitance, induc-
lower than expected performance, higher than
tance of a line, per unit length.
expected dissipation and/or unreliable or in-
R, C , L Total resistance, capacitance, in-
correct circuit behavior.
ductance of a line.
In this paper, we will review appropriate
The following equations are useful for calcu-
models and scaling behavior of IC intercon-
lating the delay caused by a line. The RC
nections, based on the analysis in [1]. Then,
delay of a lossy line is given by:
we will discuss two examples of undesired
behavior caused by interconnect parasitics tRC = 21 rcl2 = 21 RC (1)
and the problem of substrate noise. We con-
In the case of lossless and homogeneous
clude by discussing the new requirements of
transmission lines, supporting TEM waves,
IC verification tools.
Table 1. Typical IC interconnect parameters. Table 2. Dominant circuit components for
rpoly 20
/m interconnections in typical technologies.
rmetal 20 m
/m technology, wire dominant
c 150 aF/m current level length circuit elements
h 0.5 pH/m FET short C
v 1.2 cm/ns low long C, R
Z0 60
FET short C, R, (L)
high long C, R, L
h and c are related as Bipolar short C
low long C, R, (L)
hc =  ; (2) Bipolar short C, L, (R)
with  and  the permittivity and permeabil- high long C, R, L
ity of the medium, respectively. Although
Equation (2) is only valid for a single line Current level. For power lines, supporting
and IC interconnections are neither lossless large currents with large spikes, Faraday’s
nor homogeneous, it is usually an acceptable law can determine the significance of line in-
approximation. ductance. The resulting noise is proportional
For TEM lines, the characteristic impedance to LdI =dT , and is called dI=dT noise [1].

q
Z0 and propagation speed v are given by

Signal rise time and driver impedance.
When the signal rise time tr tRC or
= L=C 
= 1=p = c0=prr
Z0 (3)
tr tLC , the RC or LC delay of the line
v (4) can be ignored, respectively. Furthermore,
with c0 the speed of light in vacuum and r while tr obviously depends on the circuit
and r the relative permittivity and perme- characteristics and speed of the signal that
ability of the medium, respectively. On sil- drives the line driver, it also depends on the
icon IC’s, v varies between 0:3c0 and 0:5c0 ratio between driver impedance Zs and line
[2]. Equations (2) and (4) can be combined impedance Z0 . It turns out that if Zs  Z0 ,
to give the transmission line delay tLC of a the line inductance can be ignored.
line:
tLC = l=v = l p
 =l
p hc =
p LC (5)
The results of this section are summarized in
Table 2, which is adapted from [3].

For standard technologies a value of 150

aF/m is a useful estimate for c. With 3 IC Interconnection Scaling
v = 0:4c0 , the above equations determine h The continuous improvement in the charac-
and Z0 as given in Table 1. This table also teristics of integrated circuits is the result of
contains typical values of other IC intercon- scaling. With scaling, physical dimensions
nect parameters, but not all types of parasitics are reduced. As a result, the speed of the
are always equally significant. This depends, devices and the circuits improve. In order
for example, on the following. to avoid problems caused by strong electrical
Length of the interconnection. For exam- fields, voltages should also be reduced and
ple, we can neglect the inductive behavior of doping levels increased. Since this would in-
signal lines when tRC 
tLC . By compar- troduce many other practical problems, pro-

p
ing Equations (1) and (5), we find that this is portional scaling of voltages and doping lev-
equivalent to RC LC or els is not strictly applied in practice. Yet, it
q
= rl 
is usually assumed in the analysis of scaling
R L=C = Z0 (6) to more clearly illustrate its trend.
Table 3. Ideal scaling of MOS devices [4]. Table 4. Scaling of interconnection delay.
parameter factor parameter ideal lateral
physical dimensions 1=S unity r S2 S
substrate doping S c 1 1
voltages 1=S local l 1=S 1=S
intrinsic device delay 1=S tRC /tDEV S 1
device area 1=S 2 global l SC SC
device power 1=S 2 tRC /tDEV S 3S 2 C S 2S 2C
tLC /tDEV SC S SC S

Because it ignores many second order effects,

uniform scaling as defined above is called plied. Instead, the lateral dimensions of the
ideal scaling [4]. Typical results are sum- interconnections are scaled more than the ver-
marized in Table 3. In what follows, we will tical dimensions.
present the scaling relations for interconnec- Another reason to maintain the thickness
tion parasitics. of the interconnections is the occurrence of
We first distinguish between local and global electromigration. When the current density
interconnections. Local interconnections are in a metal line exceeds a certain material-
between individual devices, and their length dependent value, material of the line is dis-
is proportional to 1=S . Global interconnec- placed and the line can break, resulting in
tions are between modules on a chip. Their an open circuit. Thus, the current conduc-
length is proportional to the size of the chip, tion capability of interconnections must be
which increases with every new technology maintained by (relatively) large vertical di-
generation. When SC is used to denote this mensions.
chip scaling factor, the length of the global For purposes of illustration, we will consider
interconnections is proportional to SC . the case in which vertical dimensions are not
Now, note that the unit-length interconnect scaled at all, which we will call lateral scal-
resistance r is inversely proportional to the ing. The results are also indicated in Table
interconnect cross-sectional area, and thus 4, assuming that c remains constant. While
scales as S 2 . Furthermore, the unit-length this is not strictly the case, it is justified for
interconnect capacitance c is, in the case of practical linewidths [5].
ideal scaling, constant. The scaling of IC’s also deteriorates crosstalk
Together with the scaling behavior of l, the and signal-to-noise ratios, and the detailed
RC
/
delay scaling of interconnections is thus behavior again depends on what type of scal-
described by RC = rcl2 l2 S 2. Since the ing is applied. For example, in the case
intrinsic gate delay scales as 1=S , the ratio of ideal scaling, cground =ccoupling is indepen-
between the local interconnect delay and the dent of S , but in the case of lateral scaling,
gate delay increases by a factor of S and the cground =ccoupling/ S because of the change
ratio of the global interconnect delay and the in cross-sectional shape of the conductors.
gate delay increases by a factor of S 3 SC 2 . Moreover, severe problems are also likely to
These results are summarized in Table 4 in occur with the on-chip power distribution.
the column labeled ‘ideal’. (The column la- Both the resistive and inductive noise volt-
beled ‘lateral’ is explained below.) age drops will increase because of the scal-
So, with ideal scaling, the performance of a ing properties of the interconnection parame-
chip is determined to an increasing extent by ters, but also because reduced voltages and
the interconnections. The problem is so se- increased frequencies both imply increased
vere that ideal scaling cannot strictly be ap- currents. The combined effect of increased
 Table 5. Scaling of signal-to-noise ratios.
parameter ideal lateral
cground =ccoupling 1 S
IR noise S 3 SC 2 S 2 SC 2
SN R (IR) 1 / S 4 SC 2 1 / S 3 SC 2
LdI=dt noise S 3 SC 2 S 3 SC 2
SN R (dIdt) 1 / S 3 SC 3 1 / S 3 SC 3

25fF
50fF

25fF
50fF Figure 2. SPICE analysis of the network and
25fF
50fF response
excitations in Figure 1.
25fF
50fF
vdd out
25fF
fast nominal slow crosstalk

Figure 1. Five-conductor bus illustrating the

effects of coupling capacitance.

noise and decreased operation voltages ac-

counts for severe deterioration of signal-to-
noise ratios, as summarized in Table 5.
in vss

4 Examples Figure 3. Example of a CMOS driver layout.

Consider the case of five parallel lines as
shown in Figure 1. Each line is driven by tance and 75
=2 diffusion resistance. The
an inverter and different input patterns (ex- signal rise time changes from 15.4 ns to 27.4
citations) are applied as shown. Each exci- ns.
tation has a label that indicates the resulting
behavior at the far end of the middle line,
and the result of SPICE simulations is pre-
5 Substrate Modeling
sented in Figure 2. The waveforms show the The traditional ‘ideal ground plane’ model
output of the middle line in Figure 1, labeled of the substrate of VLSI chips is becom-
‘response’. The timing and shape of the ex- ing invalid in a growing fraction of all the
citations is indicated by the signal ‘in 1’ in chips that are designed. Instead, its semi-
Figure 2. The simulation illustrates that the conducting nature must be taken into account
delay of a signal can depend on the wave- to predict various parasitic couplings between
forms of neighboring lines. distant subcircuits. For example, in mixed
Also consider the CMOS driver layout in Fig- signal IC’s, the digital parts can induce noise
ure 3. The parasitic drain and source resis- into sensitive analog parts.
tances severely limit its performance, as can A typical example of substrate coupling is il-
be seen from the SPICE simulation in Fig- lustrated in Figure 6. Because of the switch-
ure 4. This simulation compares the output ing actions in the digital part, a spike is intro-
waveform of the driver when interconnect re- duced on the interconnect between the bias
sistance is ignored to that when the driver is bondpad and the substrate contact. Via the
modeled as in Figure 5. This simulation as- resistive bulk, this spike reaches the feed-
sumes 15 nm gate oxide, 40pF load capaci- back resistor of the amplifier circuit, and de-
 The medium is the substrate itself. Depend-
ing on the fabrication technology, this can
consist of a number of layers such as bulk
layer, epi layer and channel-stopper layer,
with particular doping levels. For VLSI ver-
ification purposes, it will usually be accept-
able to neglect minority carriers and to only
consider the resistive nature of the substrate.
With very high frequencies, however, the
substrate must be treated as a lossy dielec-
tric [2]. The receivers are the sensitive nodes
Figure 4. SPICE simulation of the CMOS of the circuit. For example, the MOS drain-
driver. source current can be modulated by the sub-
vdd vdd strate noise via the body effect.
While substrate noise has been a practical
problem before [6]. it will become a far
greater problem with scaling because of the
following. (1) The senders will become
in out
stronger. For example, the RI +LdI=dt noise
in Figure 6 scales as indicated in Table 5. (2)
The receivers will be more sensitive. For ex-
ample, with thin gate oxides the body effect
increases. (3) The devices will be closer to-
vss vss
gether, giving stronger transmission.
Figure 5. Equivalent network of the CMOS
driver. 6 Conclusion
The analysis in Section 2 clearly demon-
grades its signal-to-noise ratio. The problem
strates the growing significance of IC inter-
can lead to rather unexpected system behav-
connect parasitics. While it can be argued
ior if the digital noise is concentrated in a
that the presented examples are somewhat
narrow frequency band, for example around
extreme1, it can also be argued that many
the digital clock frequency.
circuits cannot tolerate even a fraction of the
The problem can be seen as a sender- parasitics assumed in that analysis. Such
medium-receiver problem. The senders are circuit examples are easily found in analog
the sources of ‘substrate pollution’. These circuits, digital circuits employing precharge
senders can, for example, be the substrate schemes and/or tri-state buffers, memory ar-
contacts or the collector substrate junctions. rays employing sense amplifiers and so on.
For example, a discussion of the capacitive
RI + LdI/dT
Analog
Output coupling problem for bit lines in DRAM’s
L
L R
Diffused
can be found in [7].
VSS Resistor
In particular, the crosstalk example showed
DIGITAL
-
that large coupling capacitances between par-
Substrate Contact +

Silicon 1However, the CMOS driver example corresponds

to a real industrial design that after fabrication did not
Figure 6. Illustration of a substrate coupling perform as expected, because the interconnect resis-
tance was neglected during design and simulation.
problem.
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