1

Understanding the Regenerative Comparator Circuit

Asad Abidi and Hao Xu
Electrical Engineering Department
University of California, Los Angeles

AbstractThe regenerative comparator circuit which lies at VDD

the heart of A/D conversion, slicer circuits, and memory sensing, 1
1
VO

Voltage(V)
is unstable, time-varying, nonlinear, and with multiple equilibria. M3 M4
That does not mean, as this paper shows, that it cannot VO1 VO2 0.5
be understood with simple equivalent circuits that reveal its M1 M2 VO
dynamics completely, and enable it to be designed to specications CL CL 2
0
on static and dynamic offset and noise. The analysis is applied 0 2 4 6
t(ns)
to the StrongArm latch. (b)
(a)
Fig. 1. (a) Schematic of a static latch; (b) Voltage waveforms in a static latch.
I. I NTRODUCTION regenerative waveform: Why do VO1 and VO2 fall together, and
Flip-ops used as regenerative ampliers are found every- then at some critical time, they peel away and separate? To
where in electronic circuits. It is well-understood that they nd the answer we create a phase portrait of this circuit [1,
have two stable states, and that given sufcient time, the circuit Ch. 11]. The independent capacitors dene two state variables,
will regenerate an input voltage unbalance to reach one of but using the capacitor voltages as state variables can obscure
these states. the essential properties. Instead, we take the average of the
The latched comparator must be symmetric by its very capacitor voltages as one state variable, the common-mode
nature, since its binary states are symmetrical. Practical unbal- voltage VOC , and their difference VOD as the other. These are
ances in the circuit arising from transistor and load mismatch orthogonal quantities, in the sense that one can change while
lead to uncertainty in the regenerated binary output when a the other remains constant. The phase plane has been used
small analog input is applied. This problem of offset is well- before to investigate latch dynamics [2], [3], but not dened
known to circuit designers, and since the observed offsets by the circuit modes. As will soon be clear, this choice makes
can be much larger than in simple linear ampliers, a certain all the difference.
mystery attends to dynamic offsets that appear only in a
latched comparator. A. Phase Plane
This paper clears much of the mystery by visualizing regen- The phase plane is dened by axes VOC vs. VOD (Fig. 3).
eration. By using one trajectory as a frame of reference, circuit It is covered by a vector eld that is signied at every point
unbalances can in most cases be modelled by a sequence of (VOD ,VOC ) on the plane by an arrow with the magnitude and
linear, time-varying equivalent circuits that capture, piecewise, direction of the ratio (dVOC /dt) (dVOD /dt), where each time
the variation of the circuit with time. Thus, simple expressions derivative at that point is obtained from the circuit equations.
are obtained for all offsets, and a straightforward method Starting from any initial condition in the plane, there develops
emerges to null them to a desired accuracy at very small cost by connecting the vector eld a unique integral curve which
in power or chip area. depicts graphically how the state variables will change with
time.
II. T HE S TATIC L ATCH The vector eld that lls the phase plane can equally well
Any discussion of a regenerative amplier must start with describe a nonlinear differential equation, or a linear one.
the CMOS static latch (Fig. 1). This is a classic circuit: simple, Sometimes linearity will apply in a limited region of the plane.
uncluttered, and therefore easily understood. The only choice In that region any integral curve can be decomposed into a
lies in the method whereby a small analog input is coupled superposition of two eigenvectors. In turn, each eigenvector
into the latch without disturbing regeneration. Here, the two can be associated with the natural response of some linear
load capacitors CL are pre-charged to a common voltage, on circuit. For the static latch, as it turns out, linearity is a very
which is superposed a small differential voltage. That is, the good assumption over much of the excursion of VO1 , VO2 ,
voltage VO1 is slightly larger than VO2 , while their average particularly over the one integral curve that will interest us.
voltage, in this example, is chosen slightly lower than VDD . If N = P where  Cox  W /L for the CMOS inverters,

The pre-charged capacitors are switched into the latch (it will then the overall Gm of the inverter remains almost constant
be seen that there are only two nodes in the circuit), and except near VDD . At low VDD this appears a small local
the circuit regenerates this difference to the voltage rails. The deviation. The equivalent circuit that is produced by replacing
regeneration waveform (Fig. 1) is familiar to almost everyone each CMOS inverter with a constant Gm voltage-controlled
who designs circuits. The existing literature does not give a current source Fig. 2 resembles a differential amplier, but the
satisfactory explanation for the one striking feature of every cross-coupled controlling voltages identify it as a ip-op. Cp

978-1-4799-3286-3/14/$31.00 2014 IEEE

2

VO1 CP VO2 Each mode will be stimulated by its own initial condition.
Therefore the time response to any initial condition V (0) =
CL GmVO2 GmVO1 CL VOC (0) + VOD (0) may be expressed as a superposition of the
common and differential modes that are stimulated:
(a)
CP
VO1,2 (t)
VOC VOC
VOC    
Gm t 1 Gmt
GmVOC 1 = VOC (0) exp VOD (0) exp + (1)
CL CL CL
CL 2 CL + 2CP
GmVOC Gm
This expression lends understanding to the example integral
(b) curves plotted on the phase plane. The vertical trajectories start
2CP 2CP
+VOD/2 -VOD/2 VOD from an initial condition VO1 = VO2 that does not stimulate the
1 differential mode. The trajectories lead into an equilibrium
-GmVOD/2 - CL+2CP
CL CL Gm point at the coordinates (0, VDD ). On the other hand if the
+GmVOD/2 output nodes are initialized so that VOD = 0 but VOC = VDD ,
(c) that is, the circuit is released from an initial condition that
Fig. 2. (a) Equivalent circuit of a static latch; (b) Common-mode equivalent is in purely differential mode, the horizontal trajectory in
circuit; (c) Differential mode equivalent circuit. the phase plane accelerates away from this equilibrium point.
If the circuit were truly linear this trajectory head towards
1.2 VOD . But in the actual circuit the node voltages cannot
Separatrix
Trajectories exceed the supply or ground, so as these trajectories approach
1 the coordinates (+VDD , VDD ) and (VDD , VDD ) they slow
down to come to rest at one of these two equilibrium points.
0.8 These last two equilibria are stable. However, the equilibrium
VO,CM(V)

at (0, VDD ) is metastable: only if the circuit is initialized

0.6 along the common-mode axis will it approach the equilibrium;
otherwise, for any other initial condition, it will be deected
0.4 away from it towards one of the two stable equilibria. In phase
plane terminology, the metastable equilibrium denes a saddle
0.2 point.
Using the phase plane, we are able to understand the
0 characteristic time-domain waveforms of a static latch. In a
-1 -0.5 0 0.5 1 typical use, the latch is initialized with both nodes connected
VO,DM(V) to, or biased close in voltage to, the power supply. This denes
Fig. 3. Phase plane plot of a static latch. VDD =1.1 V. a large initial common mode. A small differential voltage is su-
is a net cross-coupling capacitor between the two nodes arising perimposed to direct the latch regeneration. On the phase plane
from FET capacitance. We have deliberately left out the output this may correspond to the initial condition of the trajectory on
conductance gds of the FETs since it makes little difference the upper right. The large initial common mode will decay to-
to the analysis that now follows. wards the metastable point, but the small differential mode will
grow exponentially. The resulting trajectory is a superposition
B. Equivalent Circuits for Modes of the stable eigenvector which lies on the vertical axis, and
the unstable eigenvector on the horizontal axis. Because of the
A decomposition into common-mode and differential mode
large initial condition, the stable eigenvector dominates at rst
will also guide the search for meaningful equivalent circuits.
causing VO1 and VO2 to decay together. Then, as the unstable
Since these modes are independent, any response of this linear
eigenvector grows, the differential voltage becomes dominant,
circuit can be decomposed into a superposition of the two
causing the two voltages to split apart until the circuit reaches
modes. If the symmetric equivalent circuit (Fig. 2) is operating
a stable equilibrium point. The turnaround point in the VO1 (t)
purely in common mode, then VO1 (t) = VO2 (t). Since by
waveform, dened by its minimum value, corresponds to that
symmetry no currents will ow through C p , the circuit can
point on the phase plane trajectory where the slope of the
be bisected into two half circuits. It is clear that the natural
vector eld is 0.5 in magnitude.
response of the two halves of the circuit in common mode
is stable, with a pole located at sC = Gm /CL . On the other
hand, if the symmetric circuit is operating purely in differential C. Circuit Imbalances
mode, then VO1 (t) = VO2 (t). Symmetry now dictates that the Offsets are important when the latched comparator is used
mid-plate potential in the capacitor CP remains zero. After in analog-to-digital conversion. Indeed, even in memory sense
bisection into half circuits, each half consists of a capacitance applications, offsets in the sense amplier can be so large as
CL +2CP across a negative conductance Gm . Now the natural to pose a threat to reliable readout. In a nominally symmetric
response of the two halves is unstable, dened by a pole circuit, offsets arise from parameter mismatch in correspond-
located at sD = +Gm /(CL + 2CP ). ing pairs of elements, such as in the threshold voltage Vt of
 3

CP Trajectories
1.2
VO1 VO2 Separatrix

Gm(VO2+VT) 1
CL CL
Gm(VO1-VT)
0.8

VO,CM(V)
(a)
CP
0.6
VOC VOC
VOC

GmVOC 1 0.4
CL CL CL
GmVOC Gm
0.2
(b)
GmVT GmVT 0
+VOD/2 2CP 2CP -VOD/2 VOD
-1 -0.5 0 0.5 1
1 VO,DM(V)
-GmVOD/2 - CL+2CP
CL CL Gm
Fig. 5. Phase plane of a static latch with VT mismatch
+GmVOD/2
2GmVT
(c) is released from an initial condition with any common-mode
Fig. 4. (a) Equivalent circuit of a static latch with VT ; (b) Common-mode voltage but a differential voltage of 2VT , the common mode
equivalent circuit; (c) Differential mode equivalent circuit. will decay into the metastable point and the differential voltage
will remain constant for all time. In short, the separatrix that in
the NMOS pair, or in the capacitance of the loads CL . All
the balanced circuit was vertical and coincident with the axis
unbalances appear as an input-referred offset voltage, which
VOD = 0 is now, in the presence of mismatched trip points,
we now seek to estimate by simple analysis.
translated by 2VT . An offset of this amount has appeared in
As we investigate the effects of unbalances, it is desirable to the circuit.
continue analysis in terms of half circuits. Middlebrook shows 2) Mismatch in Gm : Random spreads in FET will cause
how to treat parameter unbalances in static symmetric circuits mismatch in the transconductance of the two inverters. Writing
[4] as equivalent half circuits; we extend this to dynamic the transconductances as Gm Gm , we use equivalent
circuits. circuits to examine the effects of this mismatch. We will
1) Mismatched Trip Points: Let us denote the nominal trip assume that the trip points are matched, which means that the
point of each inverter as VT . This is the point on its static I/O metastable point remains at the same location on the phase
characteristic at which the input and output voltages are equal. plane as for the balanced circuit.
In a well-designed inverter, VT = VDD . Suppose that due to In the common-mode equivalent circuit (Fig. 6), this mis-
random spreads in threshold voltages, the trip points of the two match introduces an error current GmVOC (t) connected in
inverters are unequal. Without loss of generality, we ascribe a way that is itself clearly not in common-mode. The error cur-
a deviation +VT to the trip point of one inverter and VT rent source belongs in the differential mode circuit. Removing
to the other. The latch comprising these mismatched inverters this current source restores symmetry to the common-mode
has its metastable point at VOC = VDD but |VOD | = 2VT . circuit, and it is readily seen that if the circuit is initialized
That is, the metastable point is translated from its nominal with some common mode voltage VOC (0), this will decay into
position on the phase plane. Next we show how this mismatch the metastable equilibrium value with a time constant set by
will affect the vector eld on the entire phase plane. First we the real pole sC = Gm /CL .
identify the separatrix trajectory that leads into the metastable The current owing to the mismatch Gm appears in the
point. This we can do with the aid of equivalent circuits. To differential mode equivalent circuit as an independent source
the rst order the transconductance Gm of the two inverters because it is not affected by any of the variables in this circuit.
remains matched for small VT . Now the linear equivalent It acts to cross-couple the modes [4]. The source waveform
circuit is as shown in Fig. 4. If the outputs are separated into must follow the decay of the common mode. We ignore the
modes, this circuit is equivalent to two circuits, one for the small perturbation of Gm on Gm . The differential modes
common mode and the other for the differential mode. The natural response is unstable, caused by a negative conductance
main point is that 2VT appears only in the circuit for the charging the shunt capacitance CL + 2CP . However if at every
differential mode an independent current source. By denition, instant the independent current source carries exactly the sum
the separatrix is that trajectory on the phase plane along which of the currents through these two elements, then they will not
the unstable mode is not stimulated. The unstable mode, which interact and the unstable mode will not be excited. The states
results in a growing exponential, arises in this circuit when the of the circuit will follow the separatrix into the metastable
negative resistor (1/Gm ) exchanges energy, or interacts, with point. This requires that the differential voltage is initialized
a capacitor. But suppose the capacitors CL were precharged to a VOD (0) such that
(with the appropriate sign) to 2VT . Then the independent
current source would nd a return path through the two (Gm sC (CL + 2CP ))VOD (0)esC t = GmVOC (0)esC t . (2)
negative resistors, and no current ows through the capacitors.
The unstable mode is not excited. Therefore, if the circuit Assuming 2C p  CL , this condition relates the initial condi-
4

CP
CP VO1 VO2
VO1 VO2
GmVO2
(Gm+Gm/2)VO2 CL+CL/2 CL-CL/2
CL CL GmVO1
(Gm-Gm/2)VO1
(a)
(a) CP
CP VOC VOC
VOC
VOC VOC
VOC
GmVOC 1
CL CL CL
GmVOC 1 GmVOC Gm
CL CL CL
GmVOC Gm
(b)
(b) CP
CP
+VOD/2 sCLVOC/2 -VOD/2 VOD

+VOD/2 GmVOC/2 -VOD/2 VOD 1

-GmVOD/2 - CL+2CP
1 CL CL Gm
-GmVOD/2 - CL+2CP +GmVOD/2
CL CL Gm
sCLVOC
+GmVOD/2 (c)
GmVOC
(c) Fig. 8. (a) Equivalent circuit of a static latch with CL ;(b) Common-mode
Fig. 6. (a) Equivalent circuit of a static latch with Gm ; (b) Common-mode equivalent circuit;(c) Differential mode equivalent circuit with coupled source
equivalent circuit; (c) Differential mode equivalent circuit with coupled source from common mode circuit.
from common mode circuit.
VDD
1.2 Trajectories CLK M5 M6 CLK
Separatrix VO1 VO2
1 M3 M4
VC1 VC2
0.8
CLK
VO,CM(V)

CL CC M1 M2 CC CL
Vin1 Vin2
0.6
CLK MCLK
0.4

0.2 Fig. 9. Schematic of the StrongARM latch.

0 the initial value of the common-mode voltage as determined

-1 -0.5 0 0.5 1
by the reset action:
VO,DM(V) VOD (0) CL
 (4)
Fig. 7. Phase plane of a static latch with Gm mismatch VOC (0) 2CL + 2CP
This is another dynamic offset. (4) is consistent with [5], but
tions: here this result is arrived at much more straightforwardly.
VOD (0)  (Gm /2Gm )VOC (0) (3)

If the output nodes are initially pulled up to the supply voltage, III. S TRONG A RM L ATCH
then VOC (0) = VDD . For the latch not to regenerate to 1 or This widely used latching comparator circuit in Fig. 9 was
0, an initial differential voltage given by (3) must be applied originally presented as part of a suite of low-power digital
at the same time. This is the offset caused by mismatch in circuits [6]. It offers a convenient method to couple a voltage
Gm . It is called a dynamic offset because it changes with the to be regenerated into a pair of cross-coupled invertersthe
initial common mode forced at reset, which here depends on main weakness of the CMOS static latchwhile guaranteeing
the supply voltage. On the phase plane, this means that the zero static power consumption when regeneration is complete.
separatrix is rotated from a vertical line (Fig. 7). It gained widespread attention after it was used in the Stron-
3) Mismatch in Capacitors: Suppose all corresponding gARM microprocessor.
pairs of FETs are matched, but the load capacitors are mis- A survey of the literature suggests that in spite of
matched. This is modelled by unequal capacitors CL CL widespread use, the detailed action of the StrongARM latch is,
connected to the two outputs. even now, poorly understood. Without a full understanding it
Again, this capacitor unbalance will introduce a cross- cannot be used properly as a low offset comparator. Therefore,
coupling current source that cross-couples the common mode we will rst explain how, in correct operation, the circuit
waveform into the differential mode with a magnitude of traverses two phases over which the applied voltage is am-
sCLVOC (s). Its effect, just like for Gm unbalance, is to rotate plied before regeneration will start. When poorly designed,
the separatrix, and to introduce an offset which depends on an internal regeneration can be triggered as early as in the
 5

second phase, but with the undesired consequence of a larger gm3(VC+VO)

offset.
gm3vin CC VC VO CL
A. Overall Operation
We will describe the circuit in terms of how its operation
Fig. 10. Differential half circuit during propagation phase of the StrongARM
is most widely understood. latch.
The difference between two input voltages, as measured voltage across the capacitors CC of
with respect to ground, is coupled into the latch through the
NMOS pair M1-M2. The pair is activated by the tail FET, vsmp = (gm1VID Tsmp ) (CC ) (6)
MCLK , which is assumed to act like a switch. The input voltage This differential voltage serves as the initial condition for the
common-mode (VIC ) must lie above the threshold voltage of next phase, propagation.
M1,M2 to set the bias current. 3) Propagation Phase: In propagation phase, M3 and M4
The bias current also ows through the cross-coupled invert- will turn ON, and by the end of this phase the common mode
ers, M3-M5 and M4-M6, that are stacked in series. Differential (bias) current owing through them will have discharged both
current produced by M1-M2 unbalances the inverter, causing output voltages VO1 and VO2 by VtP to turn on the cross-coupled
it to regenerate on this unbalance. Regeneration forces one PMOS pair M5, M6. During this phase M1,M2 and M3,M4
FET in each inverter to turn OFF, thus choking off a current are ON. The voltages on capacitors CC and CL will ramp down
ow path through both M1 and M2. Thus M1, M2, and the tail together, separated by the constant difference of VGS3 (= VGS4 ).
current FET are all forced into deep triode with VDS = 0 where Thus,
they no longer conduct current. The comparator consumes no Tprp = (CL +CC )|VtP |/I (7)
static power in its regenerated state.
This description is sufcient to see why the StrongARM Although the gates of M3,M4 are cross-coupled to the
latch is popular today. A closer analysis is needed to under- drains, in common mode the pair of gates follows the same
stand aspects such as the circuits inherent latency before it voltage waveform as the pair of drains, as if each FET
regenerates, and how unbalances in the circuit elements will was diode connected. The cross-coupling becomes evident in
cause static and dynamic offsets. differential mode. A cross-coupled pair of transistors will only
regenerate if the loop gain is greater than one. This is not
so when, as we have assumed, M1,M2 remain in saturation
B. Operational Phases through the propagation phase, and CC < CL . This is readily
The circuits operation should be divided into three discrete proved by replacing M3,M4 with a transconductance gM3 in
phases, with regeneration understandably taking place in the the linearized equivalent circuit of Fig. 10, and representing
last phase. In the rst two phases, sampling and propagation, M1,M2 with a constant current source. The cross-coupling
the circuit amplies the applied differential voltage on to shows in the control variable of gM3 , which instead of being
internal nodes, as we now explain. the familiar difference of two voltages, each measured with
1) Reset State: The phases are most clearly identied when respect to ground, is now their sum. The voltages vC and vO
the comparator is released from a well-dened state. The are the differential voltages across CC and CL , respectively.
circuit is dened by four state variables, the voltages on two The two capacitors in this equivalent circuit are in series and
grounded capacitors CC and on two load capacitors CL . But it is it has a single pole in the left half s-plane at
a time-varying circuit, and in the second and third phases the
s prp,dm = gM3 ((CLCC )/(CL CC )) (8)
capacitors exchange charge, collapsing the number of states
to two. Be that as it may, the circuit must be initialized When CC < CL , this cross-coupled NMOS pair will act as a
with all four states at a predetermined and xed value so as stable amplier. This simple circuit of Fig. 10 can amplify
to erase memory of the previous regeneration. A convenient because the cross-coupling introduces a controlled amount of
initialization is to precharge all four capacitor voltages through positive feedback, which, as we have just shown, stops short
FET switches to the supply voltage VDD . This initializes the of outright regeneration.
source and drain terminals of M3-M6 all to the same potential. Provided M1,M2 remain in saturation, the dominant effect
2) Sampling Phase: The input voltages Vin1 and Vin2 are be- over the propagation phase arises from the transimpedance that
ing applied when the tail current transistor MCLK is initialized. converts the input pair current, gM1 vin , to the output voltage
The average input voltage sets the bias current (I) through vO . This is dened by integration of a current on to the load
M1 and M2. This common-mode current will be forced to capacitor CL over a time window dened by Tprp , with a boost
discharge CC1 and CC2 . M3 and M4 will remain OFF until the provided by the cross-coupled NMOS pair M3,M4. In addition
capacitors have discharged by an amount equal to the threshold there is a redistribution of the charge acquired at the end of
voltage VtN . This period of time denes the sampling phase, the sampling phase, through the cross-coupled M3.M4 into
CL . This last effect accounts for the coefcient of 2 in the
Tsmp = CCVtN /I (5)
numerator of the expression for output voltage:
  
Over this period the difference in the input voltages VID , which CL + 2CC VtN
creates a differential current gm1VID , integrates a differential VOD = gM1 VID (9)
CL CC I
6

4) Regeneration Phase: At the end of the propagation a cutset of capacitors only, which forms a dissipation-less
phase, the cross-coupled PMOS pair, M5,M6, turns ON and, conservative system. Conservative circuits are fully specied
since the sources are shorted, it will regenerate the differential by the initial and nal state, without regard to how the state
voltage present at the output nodes. This voltage is, to a very changes in time. Thus, at the end of the sampling phase,
good estimate, given by (9). The pole for PMOS pair lies in because mismatch in the internal capacitors CC introduces
the right-half s-plane, and is given by coupling between common and differential modes, a differ-
ential offset voltage appears across the CC s of (CC /CC )VtN .
sreg = +gM5 /CL (10)
Then, during propagation, charge will exchange with the CL
The regenerated output voltages will grow to control all the capacitors through the cross-coupled pair M3,M4, and when
FETs in the entire latch. At one of the two stable equilibria, CC < CL (as is usual), the output will settle stably to a voltage
one output voltage will reach VDD and the other ground. No that is amplied by (1 CC /CL )1 > 1, while total charge, of
static current will ow on either side of the circuit. If the course, is conserved.
PMOS pair were to dwell at the metastable equilibrium and Thus, assuming VtN = |VtP | = Vt , the nal offset due to
the supply voltage was large enough, then the output voltages capacitor mismatch alone is
would be equal VO1 = VO2 = VDD VGS (M5, 6).  
Vt CL + 2CC
5) StrongARM Latch in Summary: This detailed analysis vOD = (12)
(1 CC /CL ) CL
shows that the StrongARM latch, with all internal nodes
initialized to VDD , undergoes two phases of common-mode The term Vt at the head of the left-hand side reminds us that
discharge before it regenerates. These phases amount to a this is a dynamic offset induced by a common-mode excursion
delay of (Tsmp + Tprp ) before the circuit regenerates with the across an unbalanced circuit. The term 2CC arises because CC
time constant given by the inverse of the pole frequency (10). undergoes a common-mode voltage excursion of VtN + |VtP |,
Others have noticed that the StrongARM latch regenerates af- almost twice the excursion of the voltage on CL . Fortunately
ter some latency, or waiting period [7]. But our analysis shows this circuit rejects typical bounce in supply voltage, so its
that over this period of latency a useful internal amplication regeneration time, static offset, and dynamic offset all remain
will take place. For the applied input voltage VID , the gain to independent of VDD .
the point of onset of regeneration is
VOD CL +CC VtN E. Offset Compensation
=2 (11)
VID CL CC VP1,2 With this background, we can explain comprehensively,
where VP1,2 is the pinchoff, or overdrive, gate voltage on and for the rst time, how the offset calibration strategies
M1,M2. By substituting typical values into the two terms rst proposed in [8] for latched comparators will work. We
above, this gain is about 5 10. have established that with zero differential input, mismatch in
the threshold voltage and of the pair M1,M2 will usually
C. FET Mismatch create the offset voltage at the output nodes according to (9),
dominating contributions from mismatch in all other FETs.
The internal gain is important for estmating offset because it
Now if the capacitances CC and CL are ne tuned in closed
amplies unbalances in the input differential pair most, usually
loop under digital control to create an almost equal offset but
to the point that they will dominate all other FET imbalances in
opposite in sign according to (12), the algebraic sum of the
the circuit. This helps to identify the principal source of offset,
two offsets will cancel. So by introducing a deliberate and
and then to focus design effort for its mitigation. Both Vt and
measured mismatch in the capacitors, the comparator may be
mismatch in the input pair will appear at the comparator
made to appear offset-free even with random mismatch in the
input as an effective VID .
FETs .
The process is readily automated by applying a common-
D. Capacitor Mismatch mode voltage to the two inputs of the comparator (zero
CC and CL , both grounded capacitors, are vulnerable to differential input), which, due to inherent mismatches will
mismatch. To model their contribution to dynamic offset in the cause the comparator to repeatedly produce either a 0 or
simplest way, we follow the method shown in the static latch a 1, then searching through binary-weighted arrays of small
analysis where capacitor mismatch induces a coupling from capacitors attached to CC and CL until the output of the latch
common-mode to differential-mode. Since the StrogArm latch changes state. That setting can be held in a register dedicated
operates by discharging both CC from their reset condition to each latch.
by VtN over the sampling mode, and then, by discharging CL The expression (12) also shows a benet of resetting the
and CC by |VtP | over the propagation phase, we expect small initial voltages across CC to VDD . In many practical cases the
mismatch between corresponding pairs of these capacitors internal nodes at the drains of M1,M2 are not reset, but are
to induce signicant (differential) mismatch over the large instead pulled up to VDD VtN by the output nodes when they
excursions of common mode. are reset. Indeed, resetting these nodes to VDD prolongs the
The analysis is simplied considerably if the FETs M1,M2 latency period by Tsmp (see (5)), which seems undesirable.
are assumed to act like current sources throughout the propa- But (12) reveals that as a result of this delay CC is twice
gation phase, because then we are dealing with a circuit with as effective in compensating offset. Thus, at the expense of
 7

a larger latency, a lighter capacitor loading may be used for gm3(VC+VO) gm3(VC+VO)
offset compensation.
But doesnt the greater latency annul the benet of a lighter I0 CC VC VO CL R CC VC VO CL
capacitor loading? To answer this question, we examine the
critical comparator in an A/D converter. A comparator is in ID ID
critical condition when it is resolving an input so close to a
threshold that regeneration may not complete in the allotted
clock phase; that is, the converter would make a metastability VDS VDS
error. This is limited by the regeneration time constant, seldom
latency. In the StrongARM latch it is the PMOS pair M5,M6 Fig. 11. Equivalent differential circuit during propagation phase when M1 & 2
that regenerates, and in the initial part of the regeneration transit from saturation to triode region.
transient it is loaded only by CL . When CC shoulders the larger will add signicantly to the mismatches of M1,M3, causing
burden of compensating latch offset, the latch regeneration the total offset to double or more.
time constant is essentially unchanged. When the offsets are
large, a better balance between latency and regeneration may IV. T HERMAL N OISE
require that the calibration arrays are more evenly distributed
Comparators are mainly limited by random or systematic
between the CC and CL nodes.
offsets. But long-standing methods to circumvent offsets, such
as overranging and digital error correction in multi-step A/D
F. Range of Input Common Mode converters, are now running up against limits posed by low
Our survey of the published uses of the StrongARM latch supply voltages. And although it might not be apparent today
shows that in most circuit realizations, the input common that thermal noise poses a bottleneck to performance, we
mode voltage is chosen poorly. This can degrade offset quite expect it to be so once offset compensation in comparators
considerably for the reasons that we will now explain. This is better understood and being widely practiced.
was observed experimentally in an early use of the latch as an There is some published work to model noise in the Stron-
SRAM sense amplier [7]. gARM latch [9], [10]. [10] identies the operational phases
Over the sampling and propagation phases, the input of this circuit correctly, but it uses a method of noise analysis
common-mode voltage (VIC ) sets the bias current through that is too indirect to yield some key insights: for instance,
M1-M4, but also determines whether or not these FETs that the input common mode must be chosen correctly (see
operate in saturation. This is best understood in a perfectly Section III-F above) in order to minimize noise.
balanced, offset-free latch with zero differential input, which Our analysis of offset in the StrongARM latch, on the other
upon release from reset should travel into its metastable state. hand, extends straightforwardly to a prediction of thermal
It is sufcient to examine the state of the circuit when the noise. But rst we must describe how noise will randomly
regenerative pair M5,M6 starts to conduct, i.e. when VO1 = VO2 trigger regeneration around the metastable point. In a perfectly
reach VDD |VtP |. Since this excursion is purely in common balanced comparator with zero input applied, the noise current
mode, M3,M4 will behave as if they are diode connected and in the input pair M1,M2 will integrate on CC during the
therefore they will operate in their saturation region. But for sampling phase, and continue to integrate and amplify on CL
the input pair M1,M2 to operate in saturation, VIC must not during the propagation phase. The random voltage integrated
exceed the upper limit on CL will trigger regeneration to 0 or 1. Now integration
of a white noise current with single-sided spectral density Sin
Vt < VIC < VDD VGS (M3,M4) (13) on a capacitor C over a known time window T , for example
Tprp , produces a voltage with variance [11, p. 331]
What if VIC is larger? Then at some point during the
 
propagation phase M1,M2 will be pushed into their triode v2n = Sin T /2C2 (14)
region. Now consider that an input differential voltage, VID , is
being appliedthis may well represent an equivalent offset If the input common-mode does not exceed the limit in
and divide the propagation phase into two sub-phases: over (13), the noise of the input pair will experience the largest
the rst sub-phase M1,M2 appear like a differential current amplication and it will account for most of the input-referred
source gmVID ; and over the second sub-phase they appear like noise. Otherwise, for two reasons, the input-referred noise will
a resistor 1/gm . This is a piecewise simplication of a circuit grow larger: rst, because of the lower gm of M1,M2 since
that, over time, is pushed from saturation into deep triode, they are in triode region; and second, because M3,M4 will
and it is captured by two different equivalent circuits over the now contribute substantially to the total noise.
sub-phases (Fig. 11). They show that the benets of an internal
amplication in the latch, as we have argued above, are now V. C OMPARISON WITH M EASURED DATA
eroded in two ways: the integration window while M1,M2 All the expressions relating to static and dynamic offsets
remain in saturation is now only a fraction of Tprp , which closely match the offset derived from transient simulations
lowers the amplication; and the integrated voltage stored on of the StrongARM latch as its input is swept. On the other
CC , also shared by CL , leaks away through the resistor during hand, it is surprisingly difcult to nd measured data in the
the second sub-phase. Now mismatches in M3,M4 and M5,M6 many publications on this comparator in a form that could
8

VDD VIC = 1.05V VIC = 1.5V

Measured Offset 8.5 mV 19.0 mV
1.5/0.24 Calculated Offset 9.5 mV 19.1 mV
CLK CLK
VO1 VO2 Due to Vt1,2 5.8 mV 5.8 mV
1/0.12 1/0.12 Due to 1,2 7.4 mV 14.0 mV
1.5/0.24 Due to Vt3,4 2.0 mV 11.6 mV
1.5/0.24
Vin1 Vin2
TABLE I
CLK 1/0.3 M EASURED RMS OFFSET VS . CALCULATED . FET MISMATCH
PARAMETERS : AV t = 3.5mVm, A = 2.5%m.

Fig. 12. Test circuit in [7]. All dimensions in m, VDD =1.5 V.

identied, with the role of pairs of FETs. An internal am-
be used to validate the analysis developed in this paper: [7] plication is revealed, and from it follows the need to choose
is the exception, because it provides histograms measured the input common-mode voltage correctly, for uses where the
across 45 samples of a latch realized in 130-nm CMOS. offset and noise should be kept very small. Most importantly,
Notably the measured offset grows by more than 2 when it is shown how by using a small array of switched capacitors,
the input common-mode exceeds the limit specied by (13). a dynamic offset can be made to cancel the static offset
The circuit in question is shown in Fig. 12. Table I shows that with little penalty on speedt. This calibration is robust against
the measured RMS offset at two common-mode levels agrees supply uctuations.
very well with predictions from our analysis. This is more Predictions from the analysis are validated against mea-
than a matter of making the numbers come out close; our surements taken on a prototype StrongArm comparator. The
predictions were made to verify certain hypotheses. Although measurements illustrate the major design considerations to
Inneon fabricated the circuit being measured, we use publicly emerge from the analysis. Our analysis of offset and its
available mismatch coefcients taken from the TSMC 130 nm implications on design is much more direct than previous work
process. on the topic, such as [12].
For VIC = 0.7VDD which lies within the range in (13), we We are grateful to Professor Bernhard Wicht of Reutlingen
assume that offset arises only from Vt mismatch and mis- University, Germany, who shared sizes of the FETs in the
match in M1,M2. Since our prediction is very close (for this SRAM sense amplier that he had reported in a perceptive
size of population) to the total measured offset, it veries the early work.
hypothesis that due to internal amplication, M3-M6 will not
contribute appreciably to mismatch. For VIC = VDD the analysis R EFERENCES
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