TEXAS Latest Fresher Placement Sample Question Paper 5

TEXAS INSTRUMENTS: TECHNICAL TEST

Date: 20th Feb 2004

1. For a CMOS inverter, the transition slope of Vout vs Vin

DC characteristics can be increased (steeper transition)
by:

a. Increasing W/L of PMOS transistor

b. Increasing W/L of NMOS transistor
c. Increasing W/L of both transistors by the same factor
d. Decreasing W/L of both transistor by the same factor

TEXAS Latest Fresher Engineer Placement Sample Question

Paper 5

2. Minimum number of 2-input NAND gates that will be

required to implement the function: Y = AB + CD + EF is
a. 4
b. 5
c. 6
d. 7

Ans 6

3. Consider a two-level memory hierarchy system M1 & M2. M1

is accessed first and on miss M2 is accessed. The access of
M1 is 2 nanoseconds and the miss penalty (the time to get
the data from M2 in case of a miss) is 100 nanoseconds. The
probability that a valid data is found in M1 is 0.97. The
average memory access time is:
a. 4.94 nanoseconds
b. 3.06 nanoseconds
c. 5.00 nanoseconds
d. 5.06 nanoseconds

Ans 5
4. Interrupt latency is the time elapsed between:
a. Occurrence of an interrupt and its detection by the CPU
b. Assertion of an interrupt and the start of the
associated ISR
c. Assertion of an interrupt and the completion of the
associated ISR
d. Start and completion of associated ISR
5. Which of the following is true for the function (A.B +
A’.C + B.C)
a. This function can glitch and can be further reduced
b. This function can neither glitch nor can be further
reduced
c. This function can glitch and cannot be further reduced
d. This function cannot glitch but can be further reduced

6. For the two flip-flop configuration below, what is the

relationship of the output at B to the clock frequency?
a. Output frequency is 1/4th the clock frequency, with 50%
duty cycle
b. Output frequency is 1/3rd the clock frequency, with 50%
duty cycle
c. Output frequency is 1/4th the clock frequency, with 25%
duty cycle
d. Output frequency is equal to the clock frequency

A B

7. The voltage on Node B is:

a. 0
b. 10
c. –10
d. –5

+ +
10V 20V
_ _

GND B

8. A CPU supports 250 instructions. Each instruction op-

code has these fields:
· The instruction type (one among 250)
· A conditional register specification
· 3 register operands
· Addressing mode specification for both source operands

The CPU has 16 registers and supports 5 addressing modes.

What is the instruction op-code length in bits?
a. 32
b. 24
c. 30
d. 36

9. In the iterative network shown, the output Yn of any

stage N is 1 if the total number of 1s at the inputs
starting from the first stage to the Nth stage is odd.
(Each identical box in the iterative network has two inputs
and two outputs). The optimal logic structure for the box
consists of:
a. One AND gate and one NOR gate
b. One NOR gate and one NAND gate
c. Two XNOR gates
d. One XOR gate

I 1 I 2 I n I n +1 I n + 2

0
Y1 Y2 Yn Yn+1 Yn+2

10. Consider a circuit with N logic nets. If each net can

be stuck-at either values 0 and 1, in how many ways can the
circuit be faulty such that only one net in it can be
faulty, and such that up-to all nets in it can be faulty?
a. 2 and 2N
b. N and 2^N
c. 2N and 3^N-1
d. 2N and 3N

ans n and..2^n

11. In the circuit shown, all the flip-flops are identical.

If the set-up time is 2 ns, clock->Q delay is 3 ns and hold
time is 1 ns, what is the maximum frequency of operation
for the circuit?

D1 Q1 D2 Q2 D3 Q3

CLOCK SIGNAL

a. 200 MHz
b. 333 MHz
c. 250 MHz
d. None of the above
ans a
12. Which of the following statements is/are true?
I. Combinational circuits may have feedback, sequential
circuits do not.
II. Combinational circuits have a ‘memory-less’ property,
sequential circuits do not.
III. Both combinational and sequential circuits must be
controlled by an external clock.

a. I only
b. II and III only
c. I and II only
d. II only
ans d
13. Consider an alternate binary number representation
scheme, wherein the number of ones M, in a word of N bits,
is always the same. This scheme is called the M-out-of-N
coding scheme. If M=N/2, and N=8, what is the efficiency of
this coding scheme as against the regular binary number
representation scheme? (As a hint, consider that the number
of unique words represent able in the latter representation
with N bits is 2^N. Hence the efficiency is 100%)
a. Close to 30%
b. Close to 50%
c. Close to 70%
d. Close to 100%
ans a
14. A CPU supports 4 interrupts- I1, I2, I3 and I4. It
supports priority of interrupts. Nested interrupts are
allowed if later interrupt is higher priority than previous
one. During a certain period of time, we observe the
following sequence of entry into and exit from the
interrupt service routine:
I1-start---I2-start---I2-end---I4-start---I3-start---I3-
end- --I4-end---I1-end
From this sequence, what can we infer about the interrupt
routines?
a. I3 > I4 > I2 > I1
b. I4 > I3 > I2 > I1
c. I2 > I1; I3 > I4 > I1
d. I2 > I1, I3 > I4 > I2 > I1
ans c

15. I decide to build myself a small electric kettle to

boil my cup of tea. I need 200 ml of water for my cup of
tea. Assuming that typical tap water temperature is 25 C
and I want the water boiling in exactly one minute, then
what is the wattage required for the heating element?
[Assume: Boiling point of water is 100 C, 1 Calorie (heat
required to change 1 gm of water by 1 C)= 4 joules, 1 ml of
water weighs 1 gm.]
a. Data given is insufficient
b. 800 W
c. 300 W
d. 1000 W
e. 250 W
ans d

16. The athletics team from REC Trichy is traveling by

train. The train slows down, (but does not halt) at a small
wayside station that has a 100 mts long platform. The
sprinter (who can run 100 mts in 10 sec) decides to jump
down and get a newspaper and some idlis. He jumps out just
as his compartment enters the platform and spends 5 secs
buying his newspaper that is at the point where he jumped
out. He then sprints along the platform to buy idlis that
is another 50 mts. He spends another 5 secs buying the
idlis. He is now just 50 mts from the other end of the
platform where the train is moving out. He begins running
in the direction of the train and the only other open door
in his train is located 50 mts behind the door from where
he jumped. At what(uniform) speed should the train be
traveled if he just misses jumping into the open door at
the very edge of the platform?
Make the following assumptions
· He always runs at his peak speed uniformly
· The train travels at uniform speed
· He does not wait (other than for the idlis & newspaper)
or run baclwards

a. Data given is insufficient

b. 4 m/s
c. 5 m/s
d. 7.5 m/s
e. 10 m/s
ans d

17. State which of the following gate combinations does not

form a universal logic set:
a. 2-input AND + 2-input OR
b. 2-to-1 multiplexer
c. 2-input XOR + inverter
d. 3-input NAND

18.For the circuit shown below, what should the function F

be, so that it produces an output of the same frequency
(function F1), and an output of double the frequency
(function F2).

IN OUT INVERTER

a. F1= NOR gate and F2= OR gate

b. F1=NAND gate and F2= AND gate
c. F1=AND gate and F2=XOR gate
d. None of the above

19. The FSM (finite state machine) below starts in state

Sa, which is the reset state, and detects a particular
sequence of inputs leading it to state Sc. FSMs have a few
characteristics. An autonomous FSM has no inputs. For a
Moore FSM, the output depends on the present state alone.
For a Mealy FSM, the output depends on the present state as
well as the inputs. Which of the statements best describes
the FSM below?

a. It has two states and is autonomous

b. The information available is insufficient
c. It is a Mealy machine with three states
d. It is a Moor machine with three states

0 1 0 1 0

20. In the circuit given below, the switch is opened at

time t=0. Voltage across the capacitor at t=infinity is:
a. 2V
b. 3V
c. 5V
d. 7V

+
+

_
_

21. What is the functionality represented by the following

circuit?
a. y= ! (b+ac)
b. y= ! (a+bc)
c. y= ! (a(b+c))
d. y= ! (a+b+c)
Vcc

B
Y

22. The value (0xdeadbeef) needs to stored at address

0x400. Which of the below ways will the memory look like in
a big endian machine:

0x403 0x402 0x401 0x400

a. be ef de ad
b. ef be ad de
c. fe eb da ed
d. ed da eb fe

23. In a given CPU-memory sub-system, all accesses to the

memory take two cycles. Accesses to memories in two
consecutive cycles can therefore result in incorrect data
transfer. Which of the following access mechanisms
guarantees correct data transfer?
a. A read operation followed by a write operation in the
next cycle.
b. A write operation followed by a read operation in the
next cycle.
c. A NOP between every successive reads & writes
d. None of the above

24. An architecture saves 4 control registers automatically

on function entry (and restores them on function return).
Save of each registers costs 1 cycle (so does restore). How
many cycles are spent in these tasks (save and restore)
while running the following un-optimized code with n=5:

Void fib(int n)
{
if((n==0) || (n==1)) return 1;
return(fib(n-1) + fib(n-2));
}
a. 120
b. 80
c. 125
d. 128

25. The maximum number of unique Boolean functions F(A,B),

realizable for a two input (A,B) and single output (Z)
circuit is:

a. 2
b. 6
c. 8
d. None of the above

Ans 16

Here is Texas paper for you.

in this paper there was 20 questions as follows in 60 minutes .
second part consists of 36 que. in 30 minutes all questions are
diagramatical.(figurs)..

1. if a 5-stage pipe-line is flushed and then we have to execute 5 and

12
instructions respectively then no. of cycles will be
 a. 5 and 12
b. 6 and 13
c. 9 and 16
d.none

2. k-map

ab
----------
c 1 x 0 0
1 x 0 x

solve it

a. A.B
B. ~A
C. ~B
D. A+B
Ans c
3.CHAR A[10][15] AND INT B[10][15] IS DEFINED
WHAT'S THE ADDRESS OF A[3][4] AND B[3][4]
IF ADDRESS OD A IS OX1000 AND B IS 0X2000

A. 0X1030 AND 0X20C3

B. OX1031 AND OX20C4
AND SOME OTHERS..
Ans 1031 204c

4. int f(int *a)

{
int b=5;
a=&b;
}

main()
{
int i;
printf("\n %d",i);
f(&i);
printf("\n %d",i);
}

what's the output .

1.10,5
2,10,10
c.5,5
d. none

5. main()
{
int i;
fork();
fork();
fork();
printf("----");
}

how many times the printf will be executed .

a.3
b. 6
c.5
d. 8

6.
void f(int i)
{
int j;
for (j=0;j<16;j++)
{
if (i & (0x8000>>j))
printf("1");
else
printf("0");
}
}
what's the purpose of the program

a. its output is hex representation of i

b. bcd
c. binary
d. decimal

7.#define f(a,b) a+b

#define g(a,b) a*b

main()
{

int m;
m=2*f(3,g(4,5));
printf("\n m is %d",m);
}

what's the value of m

a.70
b.50
c.26
d. 69

8.
main()
{
char a[10];
strcpy(a,"\0");
if (a==NULL)
printf("\a is null");
else
printf("\n a is not null");}

what happens with it .

a. compile time error.
b. run-time error.
c. a is null
d. a is not null.

9. char a[5]="hello"

a. in array we can't do the operation .

b. size of a is too large
c. size of a is too small
d. nothing wrong with it .

10. local variables can be store by compiler

a. in register or heap
b. in register or stack
c .in stack or heap .
d. global memory.

11. average and worst time complexity in a sorted binary tree is

12. a tree is given and ask to find its meaning (parse-tree)

(expression tree)
ans. ((a+b)-(c*d)) ( not confirmed)
13. convert 40.xxxx into binary .

14. global variable conflicts due to multiple file occurance

is resolved during
 a. compile-time
b. run-time
c. link-time
d. load-time

15.
two program is given of factorial.
one with recursion and one without recursion .
question was which program won't run for very big no. input because
of stack overfow .
a. i only (ans.)
b. ii only
c. i& ii both .
c. none

16.
struct a
{
int a;
char b;
int c;
}

union b
{
char a;
int b;
int c;
};
which is correct .
a. size of a is always diff. form size of b.(ans.)
b. size of a is always same form size of b.
c. we can't say anything because of not-homogeneous (not in ordered)
d. size of a can be same if ...

bye..
p.sreenivasa rao

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> > > TEXAS INSTRUMENTS PAPER

> > > ------------------------
>>>
>>>
> > > 1.THE CURRENT IN 4-OHM RESISTOR IS (CIRCUIT IS
> > > GIVEN)
> > > ANS:1A
>>>
> > > 2.WHAT IS THE BELOW CIRCUIT
> > > A)MEMORY ELEMENT
> > > B)LATCH
> > > C)AND GATE
> > > D)OSCILLATOR
> > > ANS:NOT SURE
>>>
> > > 3.KARNAUGH MAP
> > > ANS:B'(B-BAR)
>>>
> > > 4.HOW MANY 2:1 MUX ARE REQUIRED TO IMPLEMENT 8:1 MUX
> > > ANS:7
>>>
> > > 5.TWO N_MOS FETS ARE THERE .WHAT IS THE OUTPUT=20
> > > ANS:3VOLTS
>>>
> > > 6.#DEFINE SUM (A,B) A+B
> > > FIND THE VALUE OF X
> > > X=3DSUM(2,3)*SUM(3,2)
> > > ANS:13(NONE OF THE ABOVE)
>>>
> > > 7.FIND VALUE OF SIGMA B[i] =B7(-2)POWER I
> > > WHERE B[i] IS THE VALUE AT THE ITH PLACE
> > > WHAT IS RESULT IF INPUT IS 0 1 1 0 0 1 1 0
> > > ANS:+34
>>>
> > > 8.(A EX-OR B)EX-OR B=3D
> > > ANS:A
>>>
> > > 9.AB+CD+EF HOW MANY TWO I/P NAND GATES ARE REQUIRED
> > > TO IMPLEMENT THE ABOV=
> > > E FUNCTIION
> > > ANS:6
>>>
> > > 10.HOW MANY BOOLEAN FUNCTIONS WE CAN REALIZE WITH
> > > ONE INPUT
> > > ANS:4
>>>
> > > 11. WHAT IS THE TOTAL POWER DISSIPATION IF EACH BULB
> > > RATED AT 20 W ,120V=
> > > OLTS(IN THE GIVEN FIGURE)
> > > ANS:12W
>>>
> > > 12. TO INCREASE THE SLOPE OF C-MOS .WHAT IS TO BE
> > > DONE.
> > > ANS:INCREASE W/L RATIO OF P-MOS
>>>
> > > 13.IF THERE ARE W PEOPLE STANDING IN THE QUEUE AT
> > > FIRST IF THE RATE OF RE=
> > > MOVAL IS PROPORTIONAL TO REMAINING PERSONS IN THE
> > > QUEUE.
> > > ANS:DECREASES EXPONENTIALLY
>>>
> > > 14.SIMLIFY THE FOLLOWING BOOLEAN EXPRESSION=20
> > > A'+A'C+AB'
>>>
> > > 15.AB'+BC IN THE FOLLOWING ANSWERS WHICH ARE
> > > EQUILENT TO GIVEN FORM FUNCT=
> > > IONALLY
> > > ANS:ALL OF THE ABOVE
>>>
> > > 16.CIRCUIT CONSISTS OF 6 FETS IS GIVEN. O/P IS
> > > ANS:(A+BC)'
>>>
> > > 17. IN THE FOLLOWING IF 8 I/P 'S IS GIVEN TO AND
> > > GATE .WHICH IS THE FASTE=
> > > ST IMPLEMENTATION=20
> > > ANS: ((( AB)(CD))((EF)(GH)))
>>>
> > > 18. IF PROBABILITY OF EACH INPUT HIGH IS 0.5
> > > AND LOW IS 0.5.WHAT IS THE PROBABILITY OF O/P AS
> > > HIGH.
> > > CIRCUIT IS GIVEN)OUTPUT Y=3D(AB)+(CD)'
> > > ANS:13/16.
>>>
> > > 19.OUT PUT OF THE GIVEN CIRCUIT(WHEAT STONE BRIDGE
> > > WITH DIODES)
> > > ANS:0 VOLTS
>>>
> > > 20.IF C IS THE CAPACITENCE AND V IS THE APPLIED
> > > VOLTAGE AND F IS THE SWIT=
> > > HING FREQUENCY THEN POWER DISSIPATION IS
> > > ANS: F*C*V*V
>>>