JFET tester

FET matching and testing made simple

Many designers
shy away from
using JFET tran-
sistors although
numerous circuits
would benefit
from using these
devices. When-
ever very high
input impedance,
high operating
frequency and rel-
atively low noise
are paramount
design require-
ments, a JFET
may be a good
choice. This arti-
cle aims at
removing some of
the general hesitation Although the staggering amount of
data you can obtain from a FETs
channel version. Although the symbol
of a JFET is different from that of a
about using JFETs by datasheet may cause the odd apoplec- bipolar transistor, it may help you
tic fit with some of you, it can be think of the D (drain) electrode as the
describing a simple upheld that there are two absolutely collector, the S (source) electrode as the
tester that allows you vital selection criteria (or electrical emitter, and the G (gate) electrode as
parameters) which help to identify an the base. Unlike an n-p-n transistor,
to measure two cru- unknown JFET, or find so-called however, the operating range of the
matched devices from a batch of JFETs parameter called gate-source voltage
cial electrical parame- (more about this further on). (VGS) is negative. In other words, the
ters of these devices. The present tester is only suitable gate is made negative with respect to
for n-channel small-signal JFETs (junc- the source.
tion field-effect transistors). This does Now, lets first take a moment to
not detract from its usefulness how- explain the notation of the various
ever because chances are pretty small parameters symbols you will find in
that you will ever encounter a p-chan- the datasheets and this article. The
nel JFET in your lifetime! above example, VGS, should be read as
follows: Voltage (V) between Gate and
MEETING THE JFET Source (GS). Note that the index GS is
Although most of the background the- printed smaller and lower than the
ory relevant to JFETs may be found in capital letter V. Similarly, the symbol ID
any reasonable electronics textbook, it means current (I) in drain (D) chan-
may still be useful to present a brief nel, and VDS means voltage (V)
recap in this article. between drain (D) and source (S).
The circuit symbol of the n-channel Once you are comfortable with the
JFET is shown in the basic connection basics of this notation system, you will
diagram in Figure 1. The in-going have little difficulty in unravelling the
Design by M. Frankowski arrow at the G (gate) denotes the n- meaning of the various symbols used

Elektor Electronics 2/98

12
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ID DRAIN SATURATION
1 CURRENT 2
The second important JFET parameter
D is the value of the current through the
drain-source channel when VGS is at
G 0 V, and VDS, at 15 V (usually!). When
these two conditions are satisfied, the
VGS S
drain current will remain practically
VDS
constant at a certain maximum value.
In other words, the drain-source chan-
970075 - 11
nel is saturated; it will not pass more
current. The symbol used for the drain
saturation current is ID(ss). Like ID,
Figure 1. Basic JFET ID(ss) derates (worsens) with increasing
connection circuit. temperature, as illustrated in Figure 3.

PRACTICAL CIRCUIT
to describe the electrical parameters of Admittedly, that was rather a lot of Figure 2. The pinch-off
JFETs (and other transistors). theory to wade through. High time to voltage VGS(P) and the drain satu-
discuss how the two measurements ration current, ID, are easily deter-
P I N C H - O F F V O LTA G E mentioned above are performed in mined if you have a transfer charac-
The first vital JFET parameter is called practice. Lets look at the circuit dia- teristic graph like this available
the pinch-off voltage, symbol VGS(p) or gram in Figure 4. (example: BF256C JFET; source:
simply V(p). Unfortunately, due to fab- Philips Components).
rication techniques, this parameter is Pinch-off voltage measurement (S1
subject to relatively large tolerance. In not pressed)
other words, the actual VGS(p) spec This measurement is performed when
of the JFET you have available may S1 is not actuated. The pinch-off volt- 3
differ considerably from the value age is indicated on the DVM (digital
specified in the datasheets. The pinch- voltmeter) connected to the output of
off voltage is the gate-source voltage at the tester. Imagine a JFET is inserted in
which negligible drain current flows. the D.U.T. (device under test) sockets.
Hence the name: this voltage pinches A reference voltage of 100 mV is cre-
off the current flow in the drain-source ated with R1-D2-P1-R2, and connected
channel to virtually nought. The to the non-inverting input of opamp
remaining current is due to leakage, IC2. The inverting input is connected
and usually defined as 1 nA, 10 nA or to the positive supply rail by a 10-M
even 10 A by the manufacturer. The resistor (R3), as well as to the FET
pinch-off voltage is stated assuming under test, which is included in the
that VDS is held constant. Here, too, feedback path to the opamp output.
opinions differ: some manufacturers Since the gate of the JFET is at ground
state VGS(p) at VDS = 10 V, others at potential, the voltage at the source is
VDS = 15 V. It makes little difference, controlled to make the gate more neg-
however, at long as you know that ative than the source (VGS). Because
VDS is a constant value, or nearly so. the opamp will attempt to make the
The JFET tester described here mea- voltages at its inputs equal, it supplies
sures VGS at IDS = 10 nA, and does a gain at which the voltage across R3
not use a constant voltage for VDS. Yes, will equal 100 mV. Resistor R5 then
it can be done! Referring back to the drops 10 nA 100 k = 1 mV. In this
graph in Figure 2, you can see that the way, VDS of the JFET is controlled Figure 3. Drain current (ID) derating
ID curve for values of VGS approach- until IDS equals 100 mV/10 M = as a function of junction tempera-
ing the VGS(p) value (like VGS = 10 nA. The result is that VGS(p) ture (Tj).
4 V) runs virtually straight from VDS = appears on the DVM. The error
2 V onwards. In other words, ID sources in this measurement are ID3
remains virtually constant as long as (10 pA), the input bias current of the
VDS is between, say, 3 V and 15 V. So, TL071 opamp (<200 pA) and its input with 15 V rather than 12 V (as the rest
the error caused by the non-constant offset voltage (<10 mV). of the circuit), the range of VGS is
value of VDS in the test circuit is neg- Some JFETs have a pinch-off volt- extended to about +2 V.
ligible, because VDS is always in the age between 0 and 2 V. To enable
range where ID is virtually constant. these devices to be tested also, a volt- Drain saturation current measure-
Thats why JFETs make great constant- age regulator is used in the negative ment (S1 pressed)
current sources! supply rail. By supplying the opamp This is a much simpler measurement.

Elektor Electronics 2/98 13

 D1 A

4 A 12V 1N4001 D2 D3
R3

* zie tekst

10M
B C P1 D
B 0V65
5k
IC2
* see text

C 0V1 1N4148
1N4148
1 * siehe Text
voir texte
D 0V1 / 0V7
3 7
5
6
E *
R2 TL071
2
E 4V6 / 11V3

22k
4
C4

D.U.T. D 1n R5
D.U.T. D
K2

100k
D
T2 C1
G
S
G S
100
16V
K3 S1

S G
D 0V / DVM
S M1

K4 R4
K1 G
C2 C3 C5 G 100k
R1 R6
S

5k6

10
100n 100n 10
63V
D * DVM

15V
5mA
79L12
IC1
970075 - 14

Figure 4. Circuit dia- Figure 5. Copper track

gram of the JFET layout and component
tester. mounting plan of the
PCB designed for the
JFET tester (board not
Pressing S1 causes the source to be inexpensive mains adaptor with available ready-
connected to the gate, so that VGS = an output voltage of about 5 made).
0 V. Although the reference voltage at 15 VDC. Because the tester will
the +input of IC2 remains 100 mV, D3 only draw a few tens of mA when
now drops its normal forward bias S1 is pressed to perform a drain C1
C5
HOEKEN3

voltage of about 0.7 V. Consequently saturation current measurement,

HOEKEN

the opamp pulls its output to (practi- D1

cally) the positive supply level. Resis- K1 C2
0
C3
tor R5 then carries (120.7) V/100 k + IC1

R2

R1
or a little more than 100 A. This cur-
D2
COMPONENTS LIST D3
rent also flows through R6, where it is P1
R3
added to the drain saturation current. Resistors: 970075-1

As this will be in the mA region, the R1 = 5k6 1-570079

IC2

error is, we feel, insignificant for all R2 = 22k T

R3 = 10M S1
practical intents and purposes. C4 DVM
R4,R5 = 100k
Because R6 has a value of 10 , the R6 = 10 (1% if necessary)
K3 OUT

gds
ID(ss) indication on the DVM is in P1 = 5 k 10-turn cermet pre-
K4

R6
R5

gsd
R4

(mA10). Mind you, you are measur- set, vertical

dgs
ing a voltage that indicates a current!
K2
HOEKEN1

True, a value of 1 would have been

HOEKEN2

Capacitors:
more logical because then the readout C1 = 100F 16V
is simply in mA. A higher output volt- C2,C3 = 100nF
C4 = 1nF
age is used, however, to enable the
C5 = 10F 63V
DVM to be switched to a higher range
with resultant higher accuracy (in gen- Semiconductors:
eral!). Owners of 4.5-digit DVMs may D1 = 1N4001
use a 1- resistor in position R6. What- D2,D3 = 1N4148
ever DVM you use, the accuracy of the T1 = device under test (JFET)
tester will benefit from the use of a 1% IC2 = TL071CP
(close-tolerance) resistor for R6. IC1 = 79L12
970075-1

Miscellaneous:
The voltages indicated in the circuit M1 = digital voltmeter (DVM).
are typical. The first voltage applies K2K3,K4 = 3 rows of 3 IC
when S1 is not pressed, the second, socket pins, turned sockets.
when S1 is pressed. Unless otherwise S1 = Digitast press-key, 1
indicated, measurements are with make contact (ITT-Schadow).
respect to the ground rail, i.e., the 0 V K1 = mains adaptor supply
socket, flat model.
input of the DVM.
The circuit may be powered by an

14 Elektor Electronics 2/98

even very low power adaptors may be HINTS AND KINKS
used. Any small adapter rated at 6
12 VDC should be suitable because it If you want to do some testing on
will typically supply at least 15 V when known JFETs, we recommend the
only a few milli-amps are drawn. BF245 and BF256 series to start with .
When S1 is not pressed, the current Another commonly used JFET (partic-
consumption is about 5 mA. ularly outside Europe) is the 2N5486.
The highest drain saturation current
that can be measured by the circuit is
CONSTRUCTION AND about 40 mA. If you see anything
ADJUSTMENT above this value on your DVM display,
A ready-made printed circuit board is, the measurement is probably not valid.
unfortunately, not available for this Take the internal resistance of your
project. The artwork to make your DMM into account when measuring
own board is, however, shown in Fig- the voltages indicated in the circuit; at
ure 5. Look carefully at the compo- some junctions, even 10 M may be a
nent overlay to make sure each and relatively heavy load.
every polarized part is fitted the right
way around. There are three D.U.T.
sockets on the board to accommodate MATCHING ,
different pin-outs of the JFETs you WHATS IT FOR?
want to test. Make sure you know the Some (audio) amplifier stages of the
pin-out from a datasheet, else neither differential type use JFETs which have
measurement will make any sense at to be matched for optimum perfor-
all, and you may destroy the device mance. The two elementary tests car-
under test. ried out with the aid of the present
Preset P1 is adjusted until it drops tester should enable you to pick two
exactly 100 mV (use a 10-M DMM for JFETs with almost equal electrical Figure 6. Suggested
this adjustment). properties from a batch of, say, ten. front panel layout for
Finally, a suggested front panel lay- (970075-1) the JFET tester.
out is shown in Figure 6.