2.1. About The Functions Figure 2.1. Cortex-M3 Block Diagram

2.1.
About the functions
Figure 2.1. Cortex-M3 block diagram
The Cortex-M3 processor features:

A low gate count processor core, with low latency interrupt processing that has:
o A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual.
o Banked Stack Pointer (SP).
o Hardware divide instructions, SDIV and UDIV.
o Handler and Thread modes.
o Thumb and Debug states.
o Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency.
o Automatic processor state saving and restoration for low latency Interrupt
Service Routine (ISR) entry and exit.
o Support for ARMv6 big-endian byte-invariant or little-endian accesses.
o Support for ARMv6 unaligned accesses.
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor
core to achieve low latency interrupt processing. Features include:
o External interrupts, configurable from 1 to 240.
o Bits of priority, configurable from 3 to 8.
o Dynamic reprioritization of interrupts.
o Priority grouping. This enables selection of preempting interrupt levels and
non preempting interrupt levels.
o Support for tail-chaining and late arrival of interrupts. This enables back-to-
back interrupt processing without the overhead of state saving and
restoration between interrupts.
o Processor state automatically saved on interrupt entry, and restored on
interrupt exit, with no instruction overhead.
o Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep
mode support.
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
o Eight memory regions.
o Sub Region Disable (SRD), enabling efficient use of memory regions.
o The ability to enable a background region that implements the default
memory map attributes.
Bus interfaces:
o Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode,
DCode, and System bus interfaces.
o Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB)
interface.
o Bit-band support that includes atomic bit-band write and read operations.
o Memory access alignment.
o Write buffer for buffering of write data.
o Exclusive access transfers for multiprocessor systems.
Low-cost debug solution that features:
o Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is
asserted.
o Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)
debug access, or both.
o Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
and code patches.
o Optional Data Watchpoint and Trace (DWT) unit for implementing
watchpoints, data tracing, and system profiling.
o Optional Instrumentation Trace Macrocell (ITM) for support of printf style
debugging.
o Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port
Analyzer (TPA), including Single Wire Output (SWO) mode.
o Optional Embedded Trace Macrocell (ETM) for instruction trace.
Cortex-M3 Processor
The ARM Cortex-M3 is the industry-leading 32-bit processor for low power, cost-sensitive, highly
deterministic real-time embedded applications. The processor is highly configurable enabling a wide
range of implementations from those requiring memory protection and powerful trace technology to
cost sensitive devices requiring minimal area.
Key Benefits
Design the most optimal System-On-Chip with a processor that has the perfect balance between area,
performance and power with comprehensive system interfaces and integrated debug and trace
components
Develop solutions for a large variety of markets with a full-featured ARMv7-M instruction set that has
been proven across a broad set of embedded applications
Capture a worldwide experienced developer base to accelerate adoption of new Cortex-M3 powered
products and leverage the available extensive knowledge base to reduce support costs
Achieve exceptional 32-bit performance with low dynamic power, delivering leading system energy
efficiency due to integrated software controlled sleep modes, extensive clock gating and optional state
retention
Applications
The Cortex-M3 has been specifically developed for partners to develop high-performance low-cost
devices for a broad range of embedded market segments including:

2.1. About The Functions Figure 2.1. Cortex-M3 Block Diagram

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2.1.

About the functions

Figure 2.1. Cortex-M3 block diagram

The Cortex-M3 processor features:

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