74HC164
74HC164
74HC164
400
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Q0 3 12
pins can be tied together or the unused input can be tied HIGH.
Q1 4 11 Q5
10
DATA ENTRY Q2 5 Q4
Data is shifted into Q0 from the serial input pins on each LOW to Q3 6 9 MR
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HIGH transition of the CP pin. Also during the CP edge the data is
GND 7 8 CP
transferred from each Qn to Qn+1. The serial data on pins DSA and
DSB must be stable before and after the CP rising edge to meet the
SO-14 / TSSOP-14 / PDIP-14
set-up and hold timing requirements.
RESET
When asserted LOW the Master Reset ( MR ) pin sets all Qn to LOW.
This action does not depend on the condition of serial input or clock
pins. The MR must be asserted HIGH for a recovery time before the
next CP positive edge pulse.
Features Applications
Wide Supply Voltage Range from 2.0V to 6.0V General Purpose Logic
Sinks or Sources 4mA at VCC = 4.5V Wide Array of Products Such as:
CMOS Low Power Consumption PCs, Networking, Notebooks, Netbooks
Schmitt Trigger Action at all Inputs Computer Peripherals, Hard Drives, CD/DVD ROM
ESD Protection Exceeds JESD 22 TV, DVD, DVR, Set-Top Box
200-V Machine Model (A115)
2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Range of Package Options SO-14 and TSSOP-14
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. Green Device (Note 3)
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporateds definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
6 Q3 Data Output
7 GND Ground
8 CP Clock Pulse Positive Edge Triggered
9 MR Master Reset - Asynchronous
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10 Q4 Data Output
11 Q5 Data Output
12 Q6 Data Output
13 Q7 Data Output
14 VCC Supply Voltage
Logic Diagram
1
DSA D Q D Q D Q D Q D Q D Q D Q D Q
2 C C C C C C C C
DSB
R R R R R R R R
8
CP
9
MR
3 4 5 6 10 11 12 13
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CP
DSA
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DSB
unknown
Q0
unknown
Q1
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unknown
Q2
unknown
Q3
unknown
Q4
unknown
Q5
unknown
Q6
unknown
Q7
Reset
Reset All Q=0
All Q=0
Notes: 5. All Q values are reset to LOW when MR goes low. MR is asynchronous and overrides all other signals.
6. Serial data supplied at DSA and DSB is ANDED and transferred to Q0 on positive edge of CP.
.
VCC = 6.0V 85
TA Operating Free-Air Temperature -40 +125 C
Note: 9. Unused inputs should be held at VCC or Ground.
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Switching Characteristics
2.0 V 60 17 75 90
Pulse Width
4.5 V 12 6 15 18
R LOW Figure 1 ns
6.0 V
10 5 13 15
2.0 V 60 8 75 90
tSU DSA or
Figure 1 4.5 V 12 3 15 18 ns
Set-up Time DSB to CP
6.0 V 10 2 13 15
2.0 V 4 -6 4 4
tH DSA or
Figure 1 4.5 V 4 -2 4 4 ns
Hold Time DSB to CP
6.0 V 4 -2 4 4
2.0 V 41 170 215 255
tPD
Figure 1 4.5 V 15 34 43 51
Propagation CP to Qn ns
5.0 V 12
Delay
6.0 V 12 29 37 43
2.0 V 60 17 75 90
trec
R to CP 4.5 V 12 6 15 18 ns
Recovery Time
6.0 V 10 5 13 15
tPHL 2.0 V 39 140 175 210
HIGH to LOW
Figure 1 4.5 V 14 28 35 42
Propagation R to Qn ns
5.0 V 11
Delay
6.0 V 11 24 30 36
tT
2.0 V 19 75 95 110
Figure 1
Transition All signals 4.5 V 7 15 19 22 ns
Time 6.0 V 6 13 16 19
VCC = 6V
Parameter Test Conditions Unit
Typ
Power Dissipation Capacitance per
Cpd f = 1 MHz 40 pF
Gate
CI Input Capacitance VI = VCC or GND 3.5 pF
From Output
Under Test
C L
(see Note A)
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Inputs
VCC VM CL
VI tr/tf
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MR trec
Voltage Waveform Voltage Waveform
Pulse Duration and Recovery Time Set-up and Hold Times
Vl
Input VM VM
0V
tPLH tPHL
VOH
Output VM VM
VOL
tPHL tPLH
VOH
Output VM VM
VOL
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
74 HC 164 XXX - 13
74 : Logic Prefix 164 : 8-Bit Serial In S14 : SO-14 -13 : 13" Tape & Reel
HC : 2.0V to 6.0V Parallel Out T14 : TSSOP-14
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Packing
Device Package Code Packaging
Quantity Part Number Suffix
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Marking Information
(1) SO-14, TSSOP-14, PDIP-14
( Top View )
14 8
YY : Year : 08, 09,10~
Logo
WW : Week : 01~52; 52
Part Number 74HC164 represents 52 and 53 week
YY WW X X X X : Internal Codes
1 7
SO-14
Dim Min Max
E H Gauge Plane A 1.47 1.73
A1 0.10 0.25
A2 1.45 Typ
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L
Detail A
B 0.33 0.51
D 8.53 8.74
E 3.80 3.99
D
7 A2 A e 1.27 Typ
(4
x) H 5.80 6.20
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L 0.38 1.27
0 8
B e
Detail A All Dimensions in mm
A1
TSSOP-14
Dim Min Max
a1 7 (4X)
0.25
a2 0 8
Pin# 1 Indent Gauge Plane A
B L 4.9 5.10
Seating Plane
F1 B 4.30 4.50
a2
C 1.2
F D 0.8 1.05
Detail A F 1.00 Typ
F1 0.45 0.75
G K G 0.65 Typ
A K 0.19 0.30
a1 L 6.40 Typ
D
All Dimensions in mm
C
Detail A
PDIP-14
A2 c Dim Min Max
A
A 3.710 4.310
A1 0.510 -
A1
L A2 3.200 3.600
B 0.380 0.570
B1 B e B1 1.524 (BSC)
E2
c 0.204 0.360
D D 18.800 19.200
E 6.200 6.600
E1 7.320 7.920
E2 8.400 9.000
e 2.540 (BSC)
E1 L 3.000 3.600
All Dimensions in mm
C1 Y 1.50
C1 5.4
C2 C2 1.27
Y
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LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
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