3.

CIRCUIT DIAGRAMS
3.1. Circuit Diagram-1
VCORE VMEM

VCORE VMEM VCORE VRTC

C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U R101 33K
C112
0.1U
+ BAT101
ML414R-F9A

D[0..15]
D[0..15] [4,7]
ADD[0..21]
[4,7] ADD[0..21]

N1 3
K14

B14
B10
H1

C8

N5
N9

C6
D5
P7

E3

A2
L9

L2
U101
ADD0 D0

VCC1
VCC2
VCC3
VCC4

VSIM

VMEM1
VMEM2
VMEM3
VMEM4

VEXT1
VEXT2
VEXT3
VEXT4

VPEG1

VDDRTC
H4 ADD0 DATA0 N6
ADD1 J3 P6 D1
ADD2 ADD1 DATA1 D2
J2 ADD2 DATA2 M6
ADD3 J4 N7 D3
ADD4 ADD3 DATA3 D4
K3 ADD4 DATA4 M7
ADD5 K2 L7 D5
ADD6 ADD5 DATA5 D6
K4 ADD6 DATA6 P8
ADD7 L4 N8 D7
ADD8 ADD7 DATA7 D8
L1 ADD8 DATA8 M8
ADD9 L3 P9 D9
ADD10 ADD9 DATA9 D10
L5 ADD10 DATA10 M9
ADD11 M1 P10 D11
ADD12 ADD11 DATA11 D12
M2 ADD12 DATA12 N10
ADD13 N1 M10 D13
ADD14 ADD13 DATA13 D14
P1 ADD14 DATA14 P11
ADD15 N2 N11 D15
ADD16 ADD15 DATA15
P2 ADD16
ADD17 N3
ADD18 ADD17
M3 ADD18 RD M11 RD [4]
ADD19 P4 N12
ADD20 ADD19 HWR HWR [4]
N4 ADD20 LWR P13 LWR [4]
ADD21 M4 P14
ADD21 WE WE [4,7]
ROMCS M13 ROMCS [4]
RAMCS M14 RAMCS [4]
[7] KEYROW_0 A6 KEYPADROW0
[7] KEYROW_1 F4 KEYPADROW1
[7] KEYROW_2 D4 KEYPADROW2 TXPA (GPO_2) G13 TRSW3 [9]
[7] KEYROW_3 B5 KEYPADROW3 PA_NEGBIAS (GPO_4) H12 RXEN1 [8]
[3] KEYROW_4 A5 KEYPADROW4 TXPHASE (GPO_7) F14 PA_EN [9]
[7] KEYCOL_0 C4 KEYPADCOL0 DCS_SW_SYNC (GPO_8) F13 TRSW2 [9]
[7] KEYCOL_1 E4 KEYPADCOL1 DCS_SW_DRV (GPO_9) H11 TRSW1 [9]
[7] KEYCOL_2 B4 KEYPADCOL2
[7] KEYCOL_3 A4 KEYPADCOL3
[7] KEYCOL_4 C3 KEYPADCOL4 TX_GSM (GPO_16) E13 GSMEN [8,9]
ADD23(TX_DCS)GPO_17 G11 DCSEN [8]
(OTH_EN)GPO_18 E12 S XE N [8] TP124
[3] BBCLK L12 CLKIN (OTH_VLO_EN)GPO_19 D14 LE [8] RXEN
[3] CLKON G14 CLKON (OTH_DATA)GPO_20 D13 DATA [8]
B3 OSCOUT (OTH_CLK)GPO_21 F11 CLK [8]
X101 R102 A3 B1
10M OSCIN (RXON)GPO_0 RXEN [2]
MC-146 [3] POWER_ON B2 C2
PWRON (TXON)GPO_1 TXEN [2,8,9]
[3] SYS_POWERON E14 GSM_SW_DRV (GPO_11) GPO_3 G12 RFEN [9] TP101
TP_CLKOUT
[3,4,5] NRESET N14 RESET
CLKOUT D1 CLK_OUT [2,5]
[3] END_OF_CHARGE D11 GPIO_0 CLKOUT_GATE D2 CLKOUT_GATE [2]
[3] CHARGER_GATEIN D10 GPIO_1 (VBCRESET)GPO_24 E1 VBC_RESET [2]
[3] CHARGER_EN B12 GPIO_2 (ARSM)GPO_5 A1 ARSM [2]
TP102 C11 C1
TP_GPIO3 GPIO_3 (ATSM)GPO_6 AT SM [2] VMEM
[3] CHARGER_DET D9 GPIO_4 ASDI E2 ASDI [2]
B11 GPIO_5 ASDO F1 ASDO [2]
TP103 PT T
[6] HANDFREE_IN A11 GPIO_6 ASFS F2 ASFS [2]
TP_GPIO7 C10 GPIO_7
[5] YMU_IRQ D8 GPIO_8
TP104 A10 F3 R103 R104
GPIO_9 BSDO BSDO [2]

2
4

8
7
6
5
TP_GPIO9 C9 G4 TBD TBD VMEM
[6] HPOUT_ON GPIO_10 BSOFS BSOFS
C7 GPIO_11 BSDI G2 BSDI [2]
TP105 B9 G1
TP_GPIO9 [7] VIBRATOR_ON GPIO_12 BSIFS BSIFS [2]
[6] AUDIO_ON A9 GPIO_13 VSDI G3 VSDI [2] TP106
B8 H3 TP_USC0
[5] YMU_SCLK GPIO_14 VSDO VSDO [2]
TP107 A8 H2 R105

1
3

1
2
3
4
TP_GPIO11 [5] YMU_AVCC_ON GPIO_15 VSFS VSFS [2] 100K
[5] YMU_SYNC D6 GPIO_16 TP108
B7 TP_USC1
[5] YMU_SDIN GPIO_17
TP109 H14 C14 USC0
TP_GPIO18 GPIO_18 USC0 USC1
H13 GPIO_19 USC1 D12 TP110
J12 A14 USC2 TP_USC2
TP111 GPIO_20 USC2 USC3
J11 GPIO_21 USC3 A13
TP_GPIO19 E11 USC4 TP112
USC4 USC5 TP_USC3
USC5 C12
TP113 C5 B13 USC6
TP_GPIO20 BACKLIGHT1 (GPO_23) USC6
[7] BACKLIGHT A7 BACKLIGHT0 (GPO_22) TP114
TP_USC4
TP115 J13 R107 R108
SIMDATAOP SIM_IO [4]

2
4

8
7
6
5
TP_GPIO21 M5 K12 TBD TBD R106 TP116
[7] LCDCTL LCDCTL (nDISPLAYCS) SIMCLK SIM_CLK [4] 100K
P5 L10 TP_USC5
[7] LCDCS nDISPLAYCS (ADD22) SIMRESET (GPIO_23) SIM_RESET [4]
T117 F12 K13
TP_GPO23 [7] NRESET_LCD SM_SW_SYNC (GPO_10) SIMSUPPLY (GPIO_24) SIM_ON [3]
L13 GPCS1 SIMVPROG (GPIO_22) J14 TP118
M12 TP_USC6
VSSRTC
GND1 0
GND1 1

TP119 GPCS0
1

1
3

1
2
3
4
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

TP_GPCS1 TP120
L14 GPIO_32(WAIT) JTAGEN K11 TP_GPIO22

TP121 AD6522
C1 3

1
P12

A12
L11

TP122
D7

D3
K1
P3

B6

TP_GPCS0
L6
L8
J1

TP_JTAGEN

T123
TP_GPIO32

3-1
3.2. Circuit Diagram-2 VANA VCORE

D201 VANA VCORE

VMEM
TBD
R213
100K
C201 C202 C203 C204 C205 C206 C207
2.2U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U

2
4
R201
100K

F10

G1
1
3

A9

A1

K5
U201

J8
AVDD1

AVDD2

AVDD3

DVDD1

DVDD2

DVDD3
[1] ASDO H1 ASDI ITXP F9 TXIP [8]
[1] ASFS H2 ASFS ITXN E9 TXIN [8]
[1] ASDI J1 ASDO QTXN C9 TXQN [8]
QTXP D9 TXQP [8]

[1] VSFS D2 VSFS IRXP E10 RXIP [8]

[1] VSDI D1 VSDO IRXN D10 RXIN [8]
[1] VSDO E1 VSDI QRXP C10 RXQP [8]
TP207 B10
BSIFS QRXN RXQN [8]
TP205 [1] BSIFS E2 BSOFS AFCDAC A10 AFC [3]
BSDI [1] BSDI F1 H9
BSDO RAMPDAC RAMP [9]
BSOFS F2 BSIFS
[1] BSDO G2 R206
TP208 BSDI 100K
BSOFS
TP206 [1] ATSM K3 ATSM
BSDO [1] ARSM J3 ARSM
REFOUT A7 VREFOUT
REFCAP A8
[1] CLKOUT_GATE K2 MCLKEN
[1,5] CLK_OUT J2 MCLK C212 C218
C213
0.1U 0.1U 2.2U

[1,8,9] TXEN K4 TXON

[1] RXEN J4 RXON

VINNORP J10 VINNORP [6]

[1] VBC_RESET K1 RESET VINNORN K10 VINNORN [6]

VINAUXP H10 VINAUXP [6]

TP201 B2 TDI VINAUXN G10 VINAUXN [6]
B1 TP202
TP_VBCRST TDO TP_BUZZER
C2 TMS VOUTNORP K8 VOUTNORP [5]
C1 TCK VOUTNORN K7 VOUTNORN [5]

VOUTAUXP K9 VOUTAUXP [5]

B4 IDACOUT VOUTAUXN K6 VOUTAUXN [5]
2
4

A3 IDACREF
R207 J6
100K BUZZER BUZZER [6,7]
1
3

A6
AUXADC1 BAT_VIOLTAGE [3]
C214 VANA
0.1U
R208
200K/1%

A5
AUXADC2

R209

NTC
C215 100K
0.1U
VANA VBAT CON301
100K/1%
1
R210

VBAT
TP301
TP_VBAT
B5 BAT_TEMP 2
AUXADC3 BAT_TEMP
TP302
TP_GND
C216
0.1U

3
GND
TP203
ADC5
B6 BAT_CON
AUXADC5
VANA
TP204
ADC6
R211 TBD

B7
AUXADC6 R211
NC(REFCAP20)

TBD
NC(MICCAP)

A4 PCB_ID
DGND1
DGND3
AGND4
AGND3
AGND2
AGND1

AUXADC4
C217 TBD

R212 TBD

AD6521
G9
B9

B3

B8

A2
J9

J7

J5

3-2
3.3. Circuit Diagram-3

VBAT

C301 C302
4.7U 0.1U
VRTC VANA VCORE

VBAT
TP303 C303 C304 C305
U301

24
32
17
POWERON_KEY 0.1U 4.7U 4.7U
22 5

NC
NC
NC
VBAT MVBAT BAT_VOLTAGGE [2]
R301 19
100K/0402R VBAT2
R302 4
100K BATSNS
U302 DAN222 2 VRTCIN VRTC 3 VRTC VMEM SIMVCC VTCXO
[1] POWER_ON 2 POWERON_IN 29 23
3 PWRONIN VANA VANA
[1] SYS_POWERON 1
[7] POWER_KEY 30 PWRONKEY VCORE 21 VCORE

[1] KEYROW_4 31 ROWX VMEM 20 VMEM C306 C307 C308

4.7U 2.2U 1U
[1] SIM_ON 1 SIMEN VSIM 18 SIMVCC

[1] CLKON 28 TCXOEN VTCXO 25 VTCXO

[1] CHARGER_EN 14 CHGEN EOC 13 END_OF_CHARGE [1]

[1] CHARGER_GATEIN 8 GATEIN CHRDET 6 CHARGER_DET [1]
7 CHRIN RESET 16 NRESET [1,4,5]
R313 TBD 12 ISENSE RESCAP 15

DGND

DGND
9 26

AGND
GATEDIR REFOUT C311 0.1U
R312
F301 TBD
ADP3408

27

10

11
R311 TBD C309
TBD 10N R303
CON302 U307 0.3
F302 FULSE FDC640P - B
1 4 1
1 2
5
2

6 U309
T301

2 C310 U308 U310

U306 C319 SI3443DV
2 2.2U/25V BLM55C9V1 - B 1 6 1 2
4 1
VBAT
0.01U - B 2
1

5
P_JACK 2 22K 5 6 RB491D
1

22K
R310 4 3

3
10K - B C312 C323
EMD2 - B C321 10N 0.1U
0.1U
R309 C322
10K - B 0.1U

VTCXO

R304
0
[1] CLKON

U304
R305 27K
[2] AFC 1 AFC VCC 6

2 GND GND 5 1 D VCC 5

C314 10P
C313 10N 3 4 2 A
GND OUT
R308 0R R306 100R
TG-2820CB 3 Y 4
C316 GND BBCLK [1]
1U C317 10N
U305 NC7SZU00P5X

C318
TBD

R307 1M

[8] 13 M H z

TO RF BLOCK

3-3
3.4. Circuit Diagram-4

VMEM

D[0..15]
[1,7] D[0..15]
C401
0.1U

ADD[0..21]
ADD[0..21] [1,7]

J5
J6
U401
VMEM D0 J3 G2 ADD1

VCCf
VCCs
D1 DQ0 A0 ADD2
G4 DQ1 A1 F2
D2 K4 E2 ADD3
D3 DQ2 A2 ADD4
H5 DQ3 A3 D2
D4 H6 F3 ADD5
D5 DQ4 A4 ADD6
K7 DQ5 A5 E3
D6 G7 D3 ADD7
D7 DQ6 A6 ADD8
J8 DQ7 A7 C3
D8 K3 C7 ADD9
D9 DQ8 A8 ADD10
H4 DQ9 A9 E7
D10 J4 F7 ADD11
DQ10 A10
8
7
6
5

D11 K5 C8 ADD12 SIMVCC

R401 D12 DQ11 A11 ADD13
J7 DQ12 A12 D8 TP401
100K D13 H7 E8 ADD14 TP_SIMVCC
D14 DQ13 A13 ADD15
K8 DQ14 A14 F8
D15 H8 D9 ADD16
DQ15/A-1 A15 ADD17
G9
1
2
3
4

A16 ADD18
A17 F4
E4 ADD19
WP-ACC A18 ADD20 R405 R403
C5 WP/ACC A19 D7
CIOs K6 E6 ADD21 100K 10K
CIOf CIOs A20
H9 CIOf
CE2s D6 CE2s
TP403 TP402
TP_SIMCLK TP_SIMRST
NC0 E9
NC1 F9
H3
[1]
[1]
RD
HWR D4
OE
M10 J401
UB MB16
[1] LWR C4 LB MB15 L10
[1,7] WE C6 WE MB14 G10 R404 5 VCC GND 6
[1] ROMCS H2 CEf MB13 F10 150R/1%
[1] RAMCS J2 CE1s MB12 B10 [1] SIM_RESET 3 RST VPP 4
MB11 A10
MB10 L6 [1] SIM_CLK 1 CLK I/O 2 SIM_IO [1]
[1,3,5] NRESET D5 RESET MB9 B6
MB8 L5
MB7 B5
E5 M1 SIM SOCKET
RY/BY MB6 C402 C403 C404
MB5 L1 TBD 0.1U 33pF
MB4 G1
MB3 F1
G8 SA MB2 C1 TP404
MB1 B1 TP_SIMIO
VSS
VSS

MB0 A1
G3
J9

MC-222243AF9-B85XBT3(FBGA)

3-4
3.5. Circuit Diagram-5

TP502 TP501
TP_SPK-N TP_SPK-P

R503
0R
[2] VOUTNORP
LS502
C522
TBD
R504
0R RECEIVER - B
[2] VOUTNORN

2
C524 C523

T503 - B

T504 - B
33P 33P

1
R520
0R
[2] VOUTAUXN VOICEOUT [6]

[2] VOUTA U XP

VBAT
R521 100K
C520
TBD
R522 YMU_AVCC
0R U505 YMU_AVCC VM EM
[1] YMU_AVCC_ON 1 5 R510
N O TBD
2 I
3 C G 4

SC1563ISK-3.0 C512 C513

C527 C525 C526 0.1U 0.1U
4.7U C517 R508
TBD 2.2U 22N C521 0.1U
22K R514 20K
BUZZER [2,6]

14

16
U504
9

6
7
AVDD

DVDD

/TESTI

EQ1
ER2

1 R509 C518 120P

[1] YMU_SYNC SYNC 82K
[1] YMU_SCLK 2 SCLK
[1] YMU_SDIN 20 SDIN
EQ3 8

[1] YMU_IRQ 15 IRQ

17 11
LS501
[1,3,4] NRESET RST SPOUT1
19 12 C511 TBD
[1,2] CLK_OUT CLK_I SPOUT2
4 VREF SPEAKER
TESTO
SPVSS

5
DVSS
AVSS

HPOUT

2
C515 C516

T501

T502
C519 33P 33P
0.1U
13

10

18

YMU757B
3

1
HPOUT [6]

3-5
3.6. Circuit Diagram-6

VBAT MIC_PWR MIC_PWR

U601
R626 2.4K
1 5 MIC_PWR
N O
2
I TP601
[1] AUDIO_ON 3 4 TP_MIC
C G C621 R602 C603
LP2985AIMX5-2.5 0.1U 4.7K 0.1U
C629 C601 C602 C626 C627
2.2U 10N 10U 10U 0.1U
R621
0R
[2] VINNORP MIC601
1
C623 C606 C605 2
100P R624 TBD TBD
0R
[2] VINNORN MICROPHONE

2
T602

T603
R628
C607 C608 TBD R603
33P 33P 0

1
VANA MIC_PWR
R631 R630
TBD 0R

C622 VMEM
C620 R606 0.1U
0.1U 4.7K

R620
0R
R632
[2] VINAUXP 100K
C624
100P R623
0R [1] HANDFREE_IN
[2] VINAUXN

R629
C610 C611 TBD C612 R634
33P 33P TBD 0R

J601
1
4
EXT_SPK 6
5
EXT_MIC 3
2

2
T605 - B
T604 -B

T606 -B
R633
YMU_AVCC 0R PHONEJACK-B

1
R609
1M

R615 R610
47K 1M C630
2.2uF

C614 R611 C616

0.1uF 0R 10uF
[5] HPOUT
R625
C628 0R
10uF
R608
[5] VOICEOUT C615 TBD
33P

3-6
3.7. Circuit Diagram-7

VM EM

KEYCOL_0 [1]
KEYCOL_1 [1]
KEYCOL_2 [1]
KEYCOL_3 [1] C701
R701 C704 4.7U
KEYCOL_4 [1] C702 C703 1M C710
0.47U 0.47U 0.47U

C733 1U/0805 -B
SW70 1 SW7 02 SW70 3 SW7 04 SW7 05 0.1U
1 2 1 2 1 2 1 2 1 2 U701
C705
KEY [*] KEY [7] KEY [4] KEY [1] KEY_[UP] C706 C707 C708 0.47U
1U 1U 1 C86
0.47U
KEYROW_0 [1] 2 VSS
3 V5
4 V4
SW70 6 SW7 07 SW70 8 SW7 09 SW7 10
5 V3
1 2 1 2 1 2 1 2 1 2 6
C709 V2
KEY [0] KEY [8] KEY [5] KEY [2] KEY_[DOWN] 7 V1
1U
8 CAP2+
KEYROW_1 [1] 9 CAP2-
10 CAP1-
11 CAP1+
SW71 1 SW7 12 SW71 3 SW7 14 SW7 15
12 CAP3-
1 2 1 2 1 2 1 2 1 2 C734 0.1U 13
D[0..15] VOUT
KEY [#] KEY [9] KEY [6] KEY [3] SOFTKEY_LEFT [1,4] D[0..15] 14 VSS
15 VDD
D15 16
KEYROW_2 [1] ADD[0..21] D14 D7
[1,4] ADD[0..21] 17 D6
D13 18
SW71 6 SW7 17 D12 D5
19 D4
1 2 1 2 VM EM D11 20
D10 D3
21 D2
SOFTKEY_RIGHT KEY [SEND] D9 22
D8 D1
KEYROW_3 [1] 23 D0
R708 24
100K [1] LCDCTL RD/E
[1,4] WE 25 WR/R/W
SW71 8 R707 ADD0
10K 26 A0
1 2 [1] NRESET_LCD 27 RES
[4] LCDCS 28 CS1
POWERKEY
&
END POWER_KEY [3]
C732 C731 C730 C729 C728 C727 C726 C725 C724 C723 C722 C721 C720 LCD interface
Connect to LCM
TBD 0.1UF TBD TBD TBD TBD 33pF 33pF 33pF 33pF TBD TBD TBD

VBAT VBAT

D701 D702 D703 D704 D705 D706 D709 D710

LED - B LED - B LED - B LED - B LED - B LED - B HT-110NB5CT - B HT-110NB5CT - B

1
M 701
+

Samsung(AY010300035) D713
A 1SS355

2
8
7
6
5

2
4

R702 R703
150 33R
1
2
3
4

1
3

R704
0R

U702

6 C1 C2 3
R705 R706
1K 100R
2 B1 B2 5
[1] BACKLIGHT VIBRATOR_ON [1]
1 E1 E2 4

FFB2222A

3-7
3.8. Circuit Diagram-8

TP4 TP3 TP2 TP1

[9] VRF RXIP [2]

L1202 27n RXIN [2]
[9] VTX RXQP [2]
C1288 C1283 C1284 RXQN [2]
33p 33p 10p L1262
C1285 C1286 VRF
12n
100n 22p R1275 R1281
L1261 JP JP
C1203 33p R1277 JP 12n
[9] GSMTX C1269 100n
C1210 R1276 B1261
2.7p JP BEAD
VSYN [9]
C1215 18p C1272 10u C1271 B1262
C1273 22p BEAD
[9] DCSTX 0.1U
C1268 220p
C1274
R1264 2K 100n
R1204 R1205 C1208 C1207 C1209 R1266
510/1% 390 2.2n 39p 39p C1267 10

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
U1234 R1265 5k6 C1266 8n2
680p

TX/G
NC
NC
NC
VCCTXVCO
VCC4
RXIP
RXIN
RXQP
RXQN
LON
LOP
VCC3
VCCLO
LOTUNE
TP5 TP8 R1203 L1201 TP9 TP6 TP7 TP10
R1202
510/1% 220/1% 180n/0603 1 49
Tx/D BYP
2 TXTUNE VDD 48
[1] RXEN1 3 RXEN LE 47 LE [1]
[1,2,9] TXEN 4 TXEN CLK 46 CLK [1]
[1,9] GSMEN 5 PCO1 DATA 45 DATA [1]
[1] DCSEN 6 PCO2 LD_MUX 44
R1269 10 7 VTXCP SXEN 43 SXEN
8 42 [1]
[9] VRF VCC1 VCCFN_CP
9 TXCP LOCP 41
10 TXFB GNDCP 40
C1281 C1262 10P
100p 11 LNA/G GNDFN 39
12 GNDLNA/G FREF 38 13MHz [3]
R1279 13 37
51 C1211 LNA/D VCCF
14 FEEN VCCD 36
15p 15 35 R1290 C1290
LNA/P GNDD 10k 5p
16 34

LPFADJ
NC NC

CAPQN
CAPQP
CAPIN
CAPIP
17 33

TXIFN
TXIFP
FILTN

TXQN
FILTP

TXQP

VCC2
NC NC

TXIN
TXIP
U1231

T/H
1 4 C1234 15p L1235
[9] GSMRX IN G 3n3
2 G OUT 3 CX74017 VTCXO

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1279
EPCOS B7707 L1234 22p
8n2 L1237 L1266 82n
2n2 C1277 C1276 R1291
22p 100n NM
R1232 B1263
C1278 BEAD
39k/1% 100n
U1232 C1235 R1267 10
VRF [9]
1 4 C1237 C1238 C1280
G OUT 470p 470p R1268 10
2 3 C1204 22p 100n R1271 JP
[9] DCSRX IN G 18p
SRF1842NHC31K R1201 JP
C1212 8 1
0p5 R1-2 R1-1 TXQN [2]
7 R2-2 R2-1 2 TXQP [2]
6 R3-2 R3-1 3 TXIN [2]
5 R4-2 R4-1 4 TXIP [2]
U1233 R1231 JP
1 G OUT 4
C1202 C1201
[9] PCSRX 2 IN G 3 100p 100p
SRF1960NMC31K
C1213
0p5

3-8
3.9. Circuit Diagram-9

VBAT
AN1131

C1109 C1110 C1111

33p 100n 220U

J1131 M M 8430-2600

L1144 1.8nH L1139 JP

2 1
OUT IN

4
R1114

10

12
GND

GND

GND

GND
U1101

8
180
L1140 R1101

VCC OUT

VCC2

VCC2
L1131 C1132 DNI 2 1
6.8nH GSM IN 7 GSMTX [8]
C1179 39p

3
1pF
VRAMP 6 RAMP
C1107 C1140 [2]
L1136 R1111 R1112
DNI VREG 5 110K
C1145 DNI TP13 49.9K
6.8p C1146 0 C1147 1n8 RF3110 4 1nF
VBATT
11 DCS OUT
PA ENABLE 3 PA_EN [1]

BAND SELECT 2 GSMEN [1,8]

C1141 33p L1132 8n2 L1101 JP
9 1 2 1
GSM OUT DCS IN DCSTX [8 ]

13
12
11
U1133 R1102
G_TX C1178 C1106 C1105 R1113 R1115
GND
VC1
6 GND GND 1
DNI DNI 2.7p 180 100K
L1135

4
7 D/P_TX ANT 2
DNI
8 GND GND 3
C1142 12p
9 4 C1136
[8] PCSRX P_RX VC3 33p
G_TX
GND

U1132
VC2

[8] DCSRX 10 D_RX GND 5

6 2 TRSW3 [1]
C1120 18p SHS-L090TL 4.7K
16
15
14

L1143
DNI 1 5 TRSW1 [1]
4.7K U1103 C1112 1u
3 4 5 OUT VCC 1
GND 2
C1144 33p 6 2 EM B 3 4 3
BYP CTL TXEN [1,2,8]
[8] GSMRX 4.7K
LDO/MAX8878EUK-2.9
C1137 1 5 C1177
L1133 C1138 C1113
10p 4.7K 10p 4.7U 10n
DNI
3 4

EM B 3 U1131
TRSW2 [1]
U1173

1 8
[8] VTX OUTA OUTB VRF [8]
2 7
[8] VSYN OUTC VCC
3 6
[1] RFEN ENBC GND
4 5
ENA VREF
C1175 C1174
1U 1U M AS9122 C1172 C1173 C1176
10n 10U 0.1U

3-9
4. LAYOUT DIAGRAMS

E13.000
U304
U1173
9122
MC-222243AF9
-B85X-BT3 U1234
AD6521ACA CX74017
ACBM

U601
LAUA
5

AD6522N
U1101
Y757B

RF3110
U504

U505
U301 6330
ADP3408
U309
43FCX

4-1