Laboratory Exercise #11

A Simple Digital Combination Lock

ECEN 248: Introduction to Digital Design

Department of Electrical and Computer Engineering
Texas A&M University
2 Laboratory Exercise #11

1 Introduction
A classic approach to access control is the password, which can be found on safes, doorways etc. This
typical approach requires that a person wishing to gain access to a particular entryway enter the password.
If the password is correct, the entryway will unlock; otherwise, the entryway will remain locked, while
conveying no information about the required sequence. In lab this week, we will attempt to recreate this
conventional mechanism in digital form on the ZYBO board. To accomplish such a feat, we will introduce
the Moore machine, which is a type of Finite State Machine (FSM). To prototype our combination-lock, we
will make use of the push buttons and and LEDs on the ZYBO board. The exercises in this lab serve to
reinforce the concepts covered in lecture.

2 Background
Background information necessary for the completion of this lab assignment will be presented in the next
few subsection. The pre-lab assignment that follows will test your understanding of the background material.

2.1 The Moore Machine

A Finite State Machine (FSM) is an abstract way of representing a sequential circuit. Often times the terms,
FSM and sequential circuit, are used interchangeably; however, an FSM more formally refers to the model
of a sequential circuit and can model higher-level systems, such as computer programs, as well. An FSM
can be broadly classified into one of two types of machines, namely Moore or Mealy. Simply put, a Moore
machine is an FSM such that the output depends solely on the state of the machine, whereas a Mealy machine
is an FSM such that the output depends not only on the state but also the input.
Figure 1 differentiates between the Moore and Mealy machines with a dotted wire, which on the Mealy
machine, connects the input to the output logic. Other than the dotted wire, the two machines are identical.
As shown, combinational logic generates the next state based on the current state and input to the machine,
while the flip-flops store the current state. The output logic is purely combinational as well and depends on
the state in both machine. For this weeks lab, we will design a Moore machine because it fits our application
quite well; however, for the sake of comparison, we will design a Mealy machine next week.

2.2 State Diagrams and Behavioral Verilog

The operation of an FSM can be described with a directed graph such that the vertices represent the states
of the machine and the edges represent the transitions from one state to the next. This sort of graphical
representation of an FSM is known as a state diagram. Figure 2 depicts the state diagram for a 2-bit

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(a) Moore Machine

(b) Mealy Machine

Figure 1: Moore vs. Mealy Machine

saturating counter. If you recall from previous labs, a saturating counter is one that will not roll over but
rather, will stop at the minimum or maximum counter value. Let us examine the state diagram and convince
ourselves that this is the case.

Figure 2: 2-bit Saturating Counter State Diagram

Each transition or edge of the graph in Figure 2 is marked by are particular input value that causes that
transition. For this simple machine, there is only one input (with the exception of Rst) so we are able to
explicitly represent all input combinations in the diagram. As we will see later on, this is not always the
case. For each vertex, the state is clearly labeled (i.e. S0, S1, S2, and S3); likewise, the output for each state
can be found under the state label. Remember that this is a Moore machine so the outputs are dependent

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only on the state of the machine. Given the state diagram of an FSM, the question to be answered now is
how to go from a state diagram to a Verilog description? The next few paragraphs will demonstrate that
exact process.
In lecture, you have learned how to implement an FSM by mapping the design into state tables. Then
by performing logic minimization on the next-state and output expressions, you are able to realize your
FSM with gates and flip-flops. In lab, however, we will take a different approach to implementing an FSM.
Because we will be describing our final circuit in Verilog and synthesizing it for the ZYBO FPGA, the
process would be much more efficient and less error-prone if we simply described the functionality of our
FSM directly in Verilog using behavioral constructs. The flip-flops for holding the state of the machine can
be described with a positive-edge triggered always block as done in previous labs, while the next-state and
output logic can be eloquently described with case statements contained within always@(*) blocks. The
code below demonstrates the use of these behavioral constructs to describe the FSM in Figure 2.
1 t i m e s c a l e 1 ns / 2 ns
d e f a u l t n e t t y p e none
3
/ This i s a behavioral Verilog description of
5 a 2 b i t s a t u r a t i n g c o u n t e r . /
module s a t u r a t i n g c o u n t e r (
7 / o u t p u t and i n p u t a r e w i r e s /
o u t p u t w i r e [ 1 : 0 ] Count ; / / 2 b i t o u t p u t
9 i n p u t w i r e Up ; / / i n p u t b i t a s s e r t e d f o r up
i n p u t w i r e Clk , R s t ; / / t h e u s u a l i n p u t s t o a s y n c h r o n o u s c i r c u i t
11
/ we haven t t a l k e d a b o u t p a r a m e t e r s much b u t a s you can s e e
13 t h e y make o u r c o d e much more r e a d a b l e ! /
parameter S0 = 2 b00 ,
15 S1 = 2 b01 ,
S2 = 2 b10 ,
17 S3 = 2 b11 ;

19 / intermeidate nets /
r e g [ 1 : 0 ] s t a t e ; / / 4 s t a t e s r e q u i r e s 2 b i t s
21 r e g [ 1 : 0 ] n e x t S t a t e ; / / w i l l be d r i v e n i n a l w a y s b l o c k !

23 / describe next s t a t e logic /

always@ ( ) / / p u r e l y c o m b i n a t i o n a l !
25 case ( s t a t e )
S0 : b e g i n
27 i f ( Up ) / / c o u n t up
n e x t S t a t e = S1 ;
29 else // saturate
n e x t S t a t e = S0 ;
31 end
S1 : b e g i n
33 i f ( Up ) / / c o u n t up
n e x t S t a t e = S2 ;

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35 e l s e / / c o u n t down
n e x t S t a t e = S0 ;
37 end
S2 : b e g i n
39 i f ( Up ) / / c o u n t up
n e x t S t a t e = S3 ;
41 e l s e / / c o u n t down
n e x t S t a t e = S1 ;
43 end
S3 : b e g i n
45 i f ( Up ) / / s a t u r a t e
n e x t S t a t e = S3 ;
47 e l s e / / c o u n t down
n e x t S t a t e = S2 ;
49 end
/ / do n o t n e e d a d e f a u l t b e c a u s e a l l s t a t e s
51 / / have been t a k e n care o f !
endcase
53
/ d e s c r i b e t h e synchronous l o g i c t o hold our s t a t e ! /
55 always@ ( p o s e d g e Clk )
i f ( Rst ) / / r e s e t s t a t e
57 s t a t e <= S0 ;
else
59 s t a t e <= n e x t S t a t e ;

61 / d e s c r i b e t h e o u t p u t l o g i c , which i n t h i s case
h a p p e n s t o j u s t be w i r e s /
63 a s s i g n Count = s t a t e ;

65 endmodule / / t h a t s i t !

2.3 Digital Combination Lock on the ZYBO

For interacting with the user, we will utilize of the push buttons, switches and LEDs on the ZYBO board.

3 Pre-lab

The objective of the pre-lab assignment is to describe in Verilog the FSM that you will load onto the ZYBO
board during the lab. Therefore, the following subsections will describe the design we are attempting to
create in detail. The pre-lab deliverables at the end will state what it is you are required to have prior to
attending your lab session.

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3.1 Digital Combination-Lock

In lab this week, we will design a digital combination-lock that can be used on a safe or access-controlled
doorway. You will be responsible for describing the combination-lock FSM in Verilog. The easiest way to
describe the combination-lock FSM is via a state diagram. Switches on the ZYBO board will be used to
enter input to the lock. You will configure switches with a number(password) in binary format. Since we
have only 4 switches on the ZYBO board, the password will only be 4 bits wide i.e 0-15. However, before
delving into the diagram, let us take a high-level look at how our digital combination-lock is expected to
operate.

1. Set up the switches with 13 in binary format.

2. Press the button BTN0 which is connected to the signal Key0

3. Set up the switches with 7 in binary format.

4. Press the button BTN1 which is connected to the signal Key1

5. Set up the switches with 9 in binary format.

6. Finally press the button BTN0 which is connected to the signal Key0 to unlock.

Now that we understand how we want our combination-lock to operate, we can represent the FSM for
our combination-lock in a succinct manner with a state diagram. Figure 3 depicts the state diagram of the
combination-lock with some transition labels missing. Let us take a moment to examine the incomplete
diagram so that you can determine how to complete it.
The reset state is S0. This is indicated by the arrow labeled Reset == 1 pointing to the S0 node. This
arrow differs from the other arrows in the diagram in that it does not represent a transition from one state
to the next. Rather, it signifies the fact that no matter what state the machine is in, it will return to S0 when
reset is asserted (i.e. Reset == 1). We can see that the FSM will remain in state S0 until the Password
input is equal to 13 and Key0 is equal to 1 . When this happens, the FSM will transition to S1, where it
will remain until the the Key1 is pressed. When the Key1 is pressed, if the Password is equal to 7, the FSM
will move to S2, else it will move back to S0 indicating a wrong password. When FSM reaches S3, Lock
goes high indicating a correct password entry.
Hopefully, it is now clear how the FSM continues until the entire combination has been entered correctly.
The final event that moves the FSM into the unlocked state, S3, is when the Key0 button is pressed, at which
point the FSM will remain in that state until the lock is reset by pressing the Reset button. The output
logic of this FSM is quite simple. If the current state equals anything other than S3, Lock == 0. This
can be described with a simple assign statement. Complete the state diagram by adding the missing labels,
including the output designations for states S2 and S3.
Now that you have a completed state diagram, use it and the example FSM implementation in the
Background section to describe the combination-lock FSM in behavioral Verilog. The module interface

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Key0=1 Key1=1 Key0=1

Reset==1 && && &&
Password=13 Password=7 Password=9

S0 S1 S2 S3
Otherwise
Lock=0 Lock=0 Lock=0 Lock=15

Key1=1 Otherwise
&&
Password!=7

Reset==1
Figure 3: Rotary Combination-Lock State Diagram

below should get you started. Notice that we are exposing the state nets in the module interface. This is to
aide in debugging! Hint:Next state logic should be triggered when Key is pressed

/ T h i s module d e s c r i b e s t h e c o m b i n a t i o n l o c k
FSM d i s c u s s e d i n t h e p r e l a b u s i n g b e h a v i o r a l
Verilog /
module c o m b i n a t i o n l o c k f s m (

/ f o r ease o f debugging , o u t p u t s t a t e /
output reg [ 1 : 0 ] s t a t e ,
o u t p u t w i r e [ 3 : 0 ] Lock , / / a s s e r t e d when l o c k e d
i n p u t w i r e Key0 , / / u n l o c k b u t t o n 0
i n p u t w i r e Key1 , / / u n l o c k b u t t o n 1
i n p u t w i r e [ 3 : 0 ] Password , / / i n d i c a t e number
input wire Reset , / / r e s e t
i n p u t w i r e Clk , / / c l o c k
);

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3.2 Pre-lab Deliverables

Include the following items in you pre-lab submission in addition to those items mentioned in the Policies
and Procedures document for this lab course.

1. Binary numbers for 13, 7 and 9.

2. The completed state diagram for the combination-lock FSM.

3. The combination-lock FSM Verilog module.

4 Lab Procedure
The experiments below will take you through a typical design process in which you describe your design in
Verilog, simulate it in Vivado, and synthesize it for the ZYBO board.

4.1 Experiment 1
The first experiment in the lab will involve simulating the combination-lock FSM module you described in
the pre-lab to ensure it works properly before attempting to load it on the ZYBO board.

1. The following steps will guide you through the process of simulating the FSM that you created in the
pre-lab.

(a) Create a new Vivado project called lab11 and add your combination-lock FSM module to that
project.
(b) Copy the test bench file, combination lock fsm tb.v, from the course directory into your lab11 di-
rectory.
(c) Add the test bench file you just copied over to your Vivado project and simulate its operation.
(d) Examine the console output of the test bench and ensure all of the tests passed.
(e) Likewise, take a look at the simulation waveform and take note of the tests that the test bench
performs. Is this an exhaustive test? Why or why not?

4.2 Experiment 2
For the final experiment, you will integrate the modules you simulated in the previous experiment with the
synchronizer into a top-level module. You will then synthesize and implement the top-level module and load
it onto the FPGA.

1. Synthesize and implement the combination-lock top-level module with the following steps:

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(a) Copy over the following files from the course directory into you lab10 directory:
combination lock.v, the top-level Verilog module
combination lock.xdc, the XDC for the top-level
synchronizer.v, the synchronizer module for our asynchronous inputs
(b) Add the aforementioned files along with your combination-lock FSM module to your Vivado
project.
(c) Set the combination lock module as the top-level module and kick off the synthesis process.
Correct any errors with your design.
(d) Once your design builds without errors and warnings, load it onto the FPGA board.

2. With the combination-lock design loaded onto the FPGA, test its operation.

(a) Run through the combination sequence shown in the pre-lab with the switches. All the LEDs
should glow when the correct combination has been entered. Ensure the design operates as
expected. If it does not, you may want to connect the logic analyzer up to JB and walk through
the state transitions of your design.
Note: When your design works properly, demonstrate your progress to the TA.

3. At this point, we have demonstrated our prototype to our customer, and they liked what they saw.
However, they mentioned that they would like to use the lock to secure sensitive company information
and would require a more secure combination. Thus, we will modify our existing design to accept a
four number combination instead of just three.

(a) Modify the Verilog source to require the input of a fourth number of your choosing in the com-
bination. This will require the addition of one more state in your FSM. Use BTN1 to enter the
new added password.
(b) Re-synthesize and implement your design in Vivado.
(c) Load the design on the FPGA and ensure that it works properly. As with the previous test, you
may want to use the logic analyzer to aide in debugging. Note: When your modifications work
properly, demonstrate your progress to the TA.

5 Post-lab Deliverables
Please include the following items in your post-lab write-up in addition to the deliverables mentioned in the
Policies and Procedures document.

1. Include the source code with comments for all modules you simulated and/or implemented in lab.
You do not have to include test bench code that was provided! Code without comments will not be
accepted!

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2. Include screenshots of all waveforms captured during simulation in addition to the test bench console
output for each test bench simulation.

3. Answer all questions throughout the lab manual.

4. A possible attack on your combination-lock is a brute-force attack in which every possible input
combination is tried. Given the original design with a combination of three numbers between 0 and 15,
how many possible input combinations exist? How about for the modified design with a combination
of four numbers?

5. (Honors) Include a state diagram for the modified combination-lock FSM with the four number com-
bination.

6. (Honors) Another way to improve the security of our rotary combination-lock is to increase the range
of input numbers. If we wanted to allow the user to enter numbers from 0 to 45, what changes would
we have to make to our current design? In this case, what would be the total number of possible input
combinations assuming a four number combination?

6 Important Student Feedback

The last part of the lab requests your feedback. We are continually trying to improve the laboratory exercises
to enhance your learning experience, and we are unable to do so without your feedback. Please include the
following post-lab deliverables in your lab write-up.
Note: If you have any other comments regarding the lab that you wish to bring to your instructors attention,
please feel free to include them as well.

1. What did you like most about the lab assignment and why? What did you like least about it and why?

2. Were there any sections of the lab manual that were unclear? If so, what was unclear? Do you have
any suggestions for improving the clarity?

3. What suggestions do you have to improve the overall lab assignment?

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