8 7 6 5 4 3 2 1

Layout notes.
1.Separate Xout and Xin traces U1
by at least 3 x the trace width. VFG3P3A 6V41337
2.Do not share crystal load 31 17 PCIE_T0
VFG3P3 VDDA3.3 PCIE_T0 16 PCIE_C0
capacitor ground via with PCIE_C0
other components. 5
6 VDDXTAL3.3 20 PCIE_T1
3.Route power from bead through VDD_SATA PCIE_T1
bulk capacitor pad then 12 19 PCIE_C1
D
48 VDDDIG3.3 PCIE_C1 D
through 0.1uF capacitor pad VDD_ASIC
then to clock chip Vdd pad. 26 PCIE_T2
13 PCIE_T2 25 PCIE_C2
4.Do not share ground vias. One VDD_PCIE PCIE_C2
ground pin one ground via. 21
32 VDD_PCIE 34 PCIE_T3
5.Exposed pad should be VDD_PCIE PCIE_T3
grounded but is not required. 39 33 PCIE_C3
VDD_PCIE PCIE_C3
FG_X1 3 36 PCIE_T4
FG_X2 4 X1_25 PCIE_T4 35 PCIE_C4
X2 PCIE_C4
Y1
1 3 SCLK_3.3 10 38 PCIE_T5
SDATA_3.3 11 SCLK_3.3 PCIE_T5 37 PCIE_C5
4 2 SDATA_3.3 PCIE_C5
GND GND FG_SS_EN 1
SS_EN_TRI PCIE_T6
42 PCIE_T6
1

25 MHz 8 pF 1 PCIE_C6
41 PCIE_C6
C11 C12 FG_OE_0 15
6.8 pF 6.8 pF FG_OE_3 18 OE0# 44 PCIE_T7
2

GND OE3# PCIE_T7 43 PCIE_C7

C C
2 PCIE_C7
8 GNDXTAL 24 PCIE_LVDS_T8
9 GNDREF PCIE_LVDS_T8 23 PCIE_LVDS_C8
30 GNDDIG PCIE_LVDS_C8
14 GNDA 28 PCIE_LVDS_T9
SCLK_3.3 22 GND_PCIE PCIE_LVDS_T9 27 PCIE_LVDS_C9
SCLK_3.3 GND_PCIE PCIE_LVDS_C9
SDATA_3.3 29
SDATA_3.3 GND_PCIE
40 47 CKRASIC R35 1 2 33 CK_ASIC

EPAD1
EPAD2
EPAD3
EPAD4
45 GND_PCIE ASIC
46 GND_PCIE 7 CKRSATA 1 2 CK_SATA
R1 33
GND_PCIE SATA_50

49
50
51
52
s2:1: 1 = Stop low/low, 0 = Running

s8: 1 = -0.5% Spread, MID = -.25%, 0 = No Spread

B B
Vdd3P3 SW1
Vdd3P3 VFG3P3
1 16 FGROE_0 R3 1 2 10K FG_OE_0 FB4 R6 VFG3P3A
VCC s1 15 FGROE_3 R4 1 2 10K FG_OE_3 1 2 VFG3P3 1 2 VFG3P3A
s2 14
s3 BLM18AG601SN1

1
13 1.0
s4 12 C19 C20 C21 C22 C23
s5 11 10 uF .1uF .1uF 1uF .1uF

2
s6 10
8 s7 9 FGRSS_EN R11 1 2 10K FG_SS_EN
VEE s8

DIP_SW8

1
C24 C25 C26 C27 C30 C31
.1uF .1uF .1uF .1uF .1uF .1uF

2
A A

Integrated Device Technology

San Jose, CA
Size Document Number Rev
A 6V41337 0.1

Date: Friday, September 02, 2016 Sheet 1 of 2

8 7 6 5 4 3 2 1