ARM Instruction Set

Quick Reference Card

Key to Tables
{cond} Refer to Table Condition Field {cond}
<Oprnd2> Refer to Table Oprnd2
{field} Refer to Table Field
S Sets condition codes (optional)
B Byte operation (optional)
H Halfword operation (optional)
T Forces address translation. Cannot be used with pre-indexed addresses
<a_mode2> Refer to Table Addressing Mode 2
<a_mode2P> Refer to Table Addressing Mode 2 (Privileged)
<a_mode3> Refer to Table Addressing Mode 3
<a_mode4L> Refer to Table Addressing Mode 4 (Load)
<a_mode4S> Refer to Table Addressing Mode 4 (Store)
<a_mode5> Refer to Table Addressing Mode 5
#32bit_Imm A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits
<reglist> A comma-separated list of registers, enclosed in braces ( { and } )

Operation Assembler S updates Action Notes

Move Move MOV{cond}{S} Rd, <Oprnd2> N Z C Rd:= <Oprnd2>
NOT MVN{cond}{S} Rd, <Oprnd2> N Z C Rd:= 0xFFFFFFFF EOR <Oprnd2>
SPSR to register MRS{cond} Rd, SPSR Rd:= SPSR Architecture 3, 3M and 4 only
CPSR to register MRS{cond} Rd, CPSR Rd:= CPSR Architecture 3, 3M and 4 only
register to SPSR MSR{cond} SPSR{field}, Rm SPSR:= Rm Architecture 3, 3M and 4 only
register to CPSR MSR{cond} CPSR{field}, Rm CPSR:= Rm Architecture 3, 3M and 4 only
immediate to SPSR flags MSR{cond} SPSR_f, #32bit_Imm SPSR:= #32-bit_Imm Architecture 3, 3M and 4 only
immediate to CPSR flags MSR{cond} CPSR_f, #32bit_Imm CPSR:= #32-bit_Imm Architecture 3, 3M and 4 only
ALU Arithmetic
Add ADD{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= Rn + <Oprnd2>
with carry ADC{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= Rn + <Oprnd2> + Carry
Subtract SUB{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= Rn - <Oprnd2>
with carry SBC{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= Rn - <Oprnd2> - NOT(Carry)
reverse subtract RSB{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= <Oprnd2> - Rn
reverse subtract with carry RSC{cond}{S} Rd, Rn, <Oprnd2> N Z C V
Rd:= <Oprnd2> - Rn - NOT(Carry)
Multiply MUL{cond}{S} Rd, Rm, Rs N Z Rd:= Rm * Rs Not in Architecture 1
accumulate MLA{cond}{S} Rd, Rm, Rs, Rn N Z Rd:= (Rm * Rs) + Rn Not in Architecture 1
unsigned long UMULL{cond}{S} RdLo, RdHi, Rm, Rs N Z RdHi:= (Rm*Rs)[63:32] Architecture 3M and 4 only
RdLo:= (Rm*Rs)[31:0]
unsigned accumulate long UMLAL{cond}{S} RdLo, RdHi, Rm, Rs N Z RdLo:= (Rm*Rs)[31:0] + RdLo Architecture 3M and 4 only
RdHi:=(Rm*Rs)[63:32] + RdHi + CarryFrom
((Rm*Rs)[31:0] +RdLo))
signed long SMULL{cond}{S} RdLo, RdHi, Rm, Rs N Z RdHi:= signed(Rm*Rs)[63:32] Architecture 3M and 4 only
RdLo:= signed(Rm*Rs)[31:0]
signed accumulate long SMLAL{cond}{S} RdLo, RdHi, Rm, Rs N Z RdLo:= signed(Rm*Rs)[31:0] + RdLo Architecture 3M and 4 only
RdHi:= signed(Rm*Rs)[63:32] + RdHi +
CarryFrom ((Rm*Rs)[31:0] +RdLo))
Compare CMP{cond} Rd, <Oprnd2> N Z C V CPSR flags:= Rn - <Oprnd2>
negative CMN{cond} Rd, <Oprnd2> N Z C V CPSR flags:= Rn + <Oprnd2>
Logical
Test TST{cond} Rn, <Oprnd2> N Z C CPSR flags:= Rn AND <Oprnd2>
Test equivalence TEQ{cond} Rn, <Oprnd2> N Z C CPSR flags:= Rn EOR <Oprnd2>
AND AND{cond}{S} Rd, Rn, <Oprnd2> N Z C Rd:= Rn AND <Oprnd2>
EOR EOR{cond}{S} Rd, Rn, <Oprnd2> N Z C Rd:= Rn EOR <Oprnd2>
ORR ORR{cond}{S} Rd, Rn, <Oprnd2> N Z C Rd:= Rn OR <Oprnd2>
Bit Clear BIC{cond}{S} Rd, Rn, <Oprnd2> N Z C Rd:= Rn AND NOT <Oprnd2>
Shift/Rotate See Table Oprnd2
ARM Instruction Set
Quick Reference Card

Operation Assembler Action Notes

Branch Branch B{cond} label R15:= address of label Address calculated pc-relative
with link BL{cond} label R14:=R15-4, R15:= address of label
and exchange instruction set BX{cond} Rn R15:=Rn, T bit:= Rn[0] Architecture 4 with Thumb only
to Thumb state; Rn[0] = 1
to ARM state; Rn[0] =0

Load Word LDR{cond} Rd, <a_mode2> Rd:= [address]

with user-mode privilege LDR{cond}T Rd, <a_mode2P>
Byte LDR{cond}B Rd, <a_mode2> Rd:= [byte value from address]
Loads bits 0 to 7 and sets bits 8-31 to 0
with user-mode privilege LDR{cond}BT Rd, <a_mode2P>
signed LDR{cond}SB Rd, <a_mode3> Rd:= [signed byte value from address] Architecture 4 only
Loads bits 0 to 7 and sets bits 8-31 to bit 7
Halfword LDR{cond}H Rd, <a_mode3> Rd:= [halfword value from address] Architecture 4 only
Loads bits 0 to 15 and sets bits 16-31 to 0
signed LDR{cond}SH Rd, <a_mode3> Rd:= [signed halfword value from address] Architecture 4 only
Loads bits 0 to 15 and sets bits 16-31 to bit 15
Multiple
Block data operations
Increment Before LDM{cond}IB Rd{!}, <reglist>{^} ! sets the W bit (updates the
Increment After LDM{cond}IA Rd{!}, <reglist>{^} base register after the transfer)
Decrement Before LDM{cond}DB Rd{!}, <reglist>{^} ^ sets the S bit
Decrement After LDM{cond}DA Rd{!}, <reglist>{^}
Stack operations LDM{cond}<a_mode4L> Rd{!}, <reglist> Stack manipulation (pop) ! sets the W bit (updates the
and restore CPSR LDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^ base register after the transfer)
User registers LDM{cond}<a_mode4L> Rd, <reglist>^

Store Word STR{cond} Rd, <a_mode2> [address]:= Rd

with user-mode privilege STR{cond}T Rd, <a_mode2P>
Byte STR{cond}B Rd, <a_mode2> [address]:= byte value from Rd
with user-mode privilege STR{cond}BT Rd, <a_mode2P>
Halfword STR{cond}H Rd, <a_mode3> [address]:= halfword value from Rd Architecture 4 only
Multiple
Block data operations
Increment Before STM{cond}IB Rd{!}, <reglist>{^} ! sets the W bit (updates the
Increment After STM{cond}IA Rd{!}, <reglist>{^} base register after the transfer)
Decrement Before STM{cond}DB Rd{!}, <reglist>{^} ^ sets the S bit
Decrement After STM{cond}DA Rd{!}, <reglist>{^}
Stack operations STM{cond}<a_mode4S> Rd{!}, <reglist> Stack manipulation (push)
User registers STM{cond}<a_mode4S> Rd{!}, <reglist>^

Swap Word SWP{cond} Rd, Rm, [Rn] Not in Architecture 1 or 2

Byte SWP{cond}B Rd, Rm, [Rn] Not in Architecture 1 or 2

Coprocessors Data operations CDP{cond} p<cpnum>, <op1>, CRd, CRn, CRm, <op2> Not in Architecture 1
Move to ARM reg from coproc MRC{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move to coproc from ARM reg MCR{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Load LDC{cond} p<cpnum>, CRd, <a_mode5>
Store STC{cond} p<cpnum>, CRd, <a_mode5>

Software SWI 24bit_Imm Causes a software interrupt processor 24-bit immediate value encoded within
Interrupt exception the instruction.
ARM Addressing Modes
Quick Reference Card

Addressing Mode 2 Addressing Mode 4 (Load)

Immediate offset [Rn, #+/-12bit_Offset] Addressing Mode Stack Type
Register offset [Rn, +/-Rm] IA Increment After FD Full Descending
Scaled register offset [Rn, +/-Rm, LSL #5bit_shift_imm] IB Increment Before ED Empty Descending
[Rn, +/-Rm, LSR #5bit_shift_imm] DA Decrement After FA Full Ascending
[Rn, +/-Rm, ASR #5bit_shift_imm] DB Decrement Before EA Empty Ascending
[Rn, +/-Rm, ROR #5bit_shift_imm]
[Rn, +/-Rm, RRX]
Pre-indexed offset Addressing Mode 4 (Store)
Immediate [Rn, #+/-12bit_Offset]! Addressing Mode Stack Type
Register [Rn, +/-Rm]! IA Increment After EA Empty Ascending
Scaled register [Rn, +/-Rm, LSL #5bit_shift_imm]! IB Increment Before FA Full Ascending
[Rn, +/-Rm, LSR #5bit_shift_imm]! DA Decrement After ED Empty Descending
[Rn, +/-Rm, ASR #5bit_shift_imm]! DB Decrement Before FD Full Descending
[Rn, +/-Rm, ROR #5bit_shift_imm]!
[Rn, +/-Rm, RRX]!
Post-indexed offset Oprnd2
Immediate [Rn], #+/-12bit_Offset Immediate value #32bit_Imm
Register [Rn], +/-Rm Logical shift left Rm LSL #5bit_Imm
Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm Logical shift right Rm LSR #5bit_Imm
[Rn], +/-Rm, LSR #5bit_shift_imm Arithmetic shift right Rm ASR #5bit_Imm
[Rn], +/-Rm, ASR #5bit_shift_imm Rotate right Rm ROR #5bit_Imm
[Rn], +/-Rm, ROR #5bit_shift_imm Register Rm
[Rn, +/-Rm, RRX] Logical shift left Rm LSL Rs
Logical shift right Rm LSR Rs
Addressing Mode 2 (Privileged) Arithmetic shift right Rm ASR Rs
Immediate offset [Rn, #+/-12bit_Offset] Rotate right Rm ROR Rs
Register offset [Rn, +/-Rm] Rotate right extended Rm RRX
Scaled register offset [Rn, +/-Rm, LSL #5bit_shift_imm]
[Rn, +/-Rm, LSR #5bit_shift_imm] Field
[Rn, +/-Rm, ASR #5bit_shift_imm] Suffix Sets
[Rn, +/-Rm, ROR #5bit_shift_imm] _c Control field mask bit (bit 3)
[Rn, +/-Rm, RRX] _f Flags field mask bit (bit 0)
Post-indexed offset _s Status field mask bit (bit 1)
Immediate [Rn], #+/-12bit_Offset _x Extension field mask bit (bit 2)
Register [Rn], +/-Rm
Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm
[Rn], +/-Rm, LSR #5bit_shift_imm Condition Field {cond}
[Rn], +/-Rm, ASR #5bit_shift_imm Suffix Description
[Rn], +/-Rm, ROR #5bit_shift_imm EQ Equal
[Rn, +/-Rm, RRX] NE Not equal
CS Unsigned higher or same
Addressing Mode 3 - Signed Byte and Halfword Data Transfer CC Unsigned lower
Immediate offset [Rn, #+/-8bit_Offset] MI Negative
Pre-indexed [Rn, #+/-8bit_Offset]! PL Positive or zero
Post-indexed [Rn], #+/-8bit_Offset VS Overflow
Register [Rn, +/-Rm] VC No overflow
Pre-indexed [Rn, +/-Rm]! HI Unsigned higher
Post-indexed [Rn], +/-Rm LS Unsigned lower or same
GE Greater or equal
Addressing Mode 5 - Coprocessor Data Transfer LT Less than
Immediate offset [Rn, #+/-(8bit_Offset*4)] GT Greater than
Pre-indexed [Rn, #+/-(8bit_Offset*4)]! LE Less than or equal
Post-indexed [Rn], #+/-(8bit_Offset*4) AL Always