EDITED BY BRAD THOMPSON

AND FRAN GRANVILLE

designideas
READERS SOLVE DESIGN PROBLEMS

Precision full-wave signal rectifier

needs no diodes

D Is Inside
82 1-Hz to 100-MHz VFC features
160-dB dynamic range

Jos M Blanes and Jos A Carrasco,

University Miguel Hernndez, Elche, Spain

Rectifier circuits based on semiconductor diodes typically handle voltage levels that greatly exceed
the diodes forward-voltage drops,

which generally dont affect the accuracy of the rectification process. However, the rectified signals accuracy suffers when the diodes voltage drop ex-

R3
2k

R4
2k
R2
1k

VIN

2 _

6 _
V

IC1A OUT

3 +
R5
1k

VCC

VCC

R1
1k

IC1B OUT
1

LMC6482AIN
4 V

VOUT

LMC6482AIN
4 V

VHALF

Figure 1 This precision full-wave-rectifier circuit uses two op amps and no

diodes. When altering the basic design, note that resistors R3 and R4 are both
twice the value of R2 and that R1 and R5 are equal.

Figure 2 From bottom to top, the waveforms show VIN (CH1), VHALF (CH2), and
VOUT (CH3).

86 Cascode MOSFET increases

boost regulators input- and
output-voltage ranges

ceeds the applied voltage. Precision rectifier circuits combine diodes and operational amplifiers to eliminate the
effects of diode voltage drops and
enable high-accuracy, small-signal rectification. By taking advantage of modern operational amplifiers that can handle rail-to-rail inputs and outputs, the
circuit in Figure 1 dispenses with
diodes altogether, provides full-wave
rectification, and operates from a single power supply.
The circuit operates as follows: If
VIN0V, then IC1As output, VHALF,
equals VIN/2, and IC1B operates as a subtracter, delivering an output voltage,
VOUT, equals VIN. In effect, the circuit
operates as a unity-gain follower. If
VIN0V, then VHALF0V, and the circuit behaves as a unity-gain inverter
and delivers an output of VOUTVIN.
Figure 2 shows the circuits input signal at VIN; its intermediate voltage,
VHALF; and its output voltage, VOUT.
The circuit uses a single National
Semiconductor LMC6482 chip and
operates in the linear regions of both
operational amplifiers. Suggested applications include low-cost rectification
for automatic gain control, signal
demodulation, and process instrumentation. The circuit relies on only one
device-dependent property: The amplifiers must not introduce phase inversion when the input voltage exceeds
the negative power supply; the LMC6482 meets this requirement.EDN

SEPTEMBER 1, 2005 | EDN 81

designideas
1-Hz to 100-MHz VFC features
160-dB dynamic range
Jim Williams, Linear Technology Corp

The VFC (voltage-to-frequency-converter) circuit in Figure 1

achieves a wider dynamic range and a
higher full-scale output frequency
100 MHz with 10% overrange to 110
MHzby a factor of 10 over any commercially available converter. The circuits 160-dB dynamic range spans
eight decades for a 0 to 5V input range
and allows continuous operation down
to 1 Hz. Additional specifications
include 0.1% linearity, a 250-ppm/C

which in turn drives IC4, a 74HC4060

configured as a divide-by-16 counter.
After undergoing a total division by
64 in IC3 and IC4, the oscillator cores
output drives a charge pump comprising IC5, an LTC6943, and its associated components. The averaged difference between the charge pumps output
and the applied input voltage appears
at the summing node and biases IC1,
thereby closing the control loop
around the wide-range oscillator core.

gain/temperature coefficient, a 1Hz/C zero-point shift, and a 0.1% frequency shift for a 10% power-supplyvoltage variation. A single 5V supply
powers the circuit.
Chopper-stabilized amplifier IC1, an
LTC-1150, controls a crude but widerange oscillator core comprising bipolar transistors Q1 and Q2 and inverters
IC2A and IC2B. In addition to delivering a logic-level output, the oscillator
core clocks divide-by-four counter IC3,

5V
R3
120
R4
120

R2
12k

R1
7.5k

Q1
2N3906
D1

FOUT
1 Hz TO 100 MHz

OSCILLATOR
CORE
Q2
C2
2N3904
0.1 F NC

5V

D1
IC2A
C1
20 pF

IC2B

74AHC14

CLK1
D2
74AHC14

VBIAS
3V DC
GENERATOR
R16
D3
D2
510k

SERVO
AMPLIFIER

C10 +
10 F

C9
10 F

P1 CLR1
IC3
74AHC74 CLK2
Q2
P2 CLR2
Q1

5V
R14
2k

R13
510k
5V

R15
33

CLK

IC1
LTC1150_

R10
10k

R12
20

R9
2k
LINEARITY
(60 MHz)
VIN
0 TO 5V

Q4

12

R8
6.19k

IC4
74HC4060
CLR

FEEDBACK
DIVIDER

CHARGE
PUMP

SUMMING
NODE

R11
10k
C8
1 F

IC5
LTC6943

C4
100 pF
11
4

R5
100

C7
C5
0.22 F 100 pF
100 MHz
R7
1k

14

15

13

C6
1 F

IC6
LT1460
2.5V

5V

R6
1.5k

NOTES:
1. D1: JPAD-500, D2, D3: BAT-85, R5, R6, R8: TRW-IRC TYPE MAR-6, 1% METAL-FILM, C4, C5: WIMA TYPE FKP-2 CAPACITORS,
AND C7, C8: WIMA TYPE MKS-2 CAPACITORS.
2. CONNECT ALL COMPONENTS AT Q1'S COLLECTOR WITH A MINIMUM-AREA AIR-INSULATED "FLOATING" JUNCTION
OVER A RELIEVED AREA OF GROUND TO MINIMIZE STRAY CAPACITANCE.
3. ENCLOSE R11 AND ITS CONNECTIONS TO R9, R10, IC1'S INVERTING INPUT, C7, AND PINS 5 AND 12 OF IC5 WITHIN SOLDER- AND
COMPONENT-SIDE GUARD TRACES TO INTERCEPT ANY BOARD-SURFACE LEAKAGE CURRENTS.
(NOTE THAT THE DASHED LINE DEFINES THE GUARD TRACE.)
4. CONNECT IC2'S UNUSED INPUTS TO GROUND. THE SCHEMATIC OMITS POWER-SUPPLY CONNECTIONS TO MOST ICS FOR CLARITY

Figure 1 Featuring a 160-dB dynamic range corresponding to a 1-Hz- to 100-MHz-frequency span, this voltage-to-frequency converter operates from a single 5V power supply.

82 EDN | SEPTEMBER 1, 2005

designideas
The circuits extraordinary dynamic
range and high speed derive from the
oscillator cores characteristics, the
divider/charge-pump-based feedback
loop, and ICls low dc input errors. Both
IC1 and IC5 help stabilize the circuits
operating point by contributing to
overall linearity and stability. In addition, ICls low offset drift ensures the
circuits 50-nV/Hz gain-versus-frequency characteristic slope and permits
operation as low as 1 Hz at 25C.
Applying a positive input voltage
causes IC1s output to go negative and
alter Q1s bias. In turn, Q1s collector
current produces a voltage ramp on C1
(upper trace in Figure 2). The ramps
amplitude increases until Schmitt trigger inverter IC2As output (lower trace
in Figure 2) goes low, discharging
C1 through Q2 (connected as a lowleakage diode). Discharging C1 resets
IC1As output to its high state, and the
ramp-and-reset action continues.
The leakage current of diode D1, a
Linear Systems JPAD-500, dominates
all other parasitic currents in the oscillator core, but its 500-pA maximum
leakage ensures operation as low as 1
Hz. The two sections of charge pump
IC5 operate out of phase and transfer
charge at each clock transition. Components critical to the charge pumps
stability include a 2.5V LT-1460 voltage reference, IC6; two Wima FKP-2
polypropylene film/foils; 100-pF capacitors, C4 and C5; and the low chargeinjection characteristics of IC5s internal switches.
The 0.22-F capacitor, C7, averages
the difference signal between the inputderived current and the charge pumps
output and applies the smoothed dc signal to amplifier IC1, which in turn controls the bias applied to Q1 and thus the
circuits operating point. As noted, the
circuits closed-loop-servo action reduces the oscillators drift and enhances
its high linearity. A 1-F Wima MKS2 metallized-film-construction capacitor, C8, compensates the servo loops
frequency response and ensures stability. Figure 3 illustrates the loops wellbehaved response (lower trace) to an
input-voltage step (upper trace).

84 EDN | SEPTEMBER 1, 2005

1V/DIV
(AC COUPLED)

2V/DIV

5 nSEC/DIV

Figure 2 On a 700-MHz real-time oscilloscope, the oscillator-core waveforms at

a 40-MHz operating frequency show the ramp-and-reset waveform at Q1s collector (upper trace) and Q2s emitter (lower trace).

2V/DIV
(ON 0.05 VDC)

1V/DIV

10 mSEC/DIV

Figure 3 In response to an input-voltage step (upper trace), the voltage at the

circuits summing junction shows a 30-msec settling time.

For the circuit to achieve its design

goals, certain special techniques and
considerations apply. Diode Dls leakage
current dominates all other parasitic
leakage currents at IC2As input, and
thus Q1 must always supply sufficient
source current to sustain oscillation and
ensure operation as low as 1 Hz.
The circuits 100-MHz full-scale

upper frequency limit forces stringent

restrictions on the oscillator cores cycle
time, and only 10 nsec is available for
a complete ramp-and-reset sequence.
The reset interval imposes an ultimate
speed limit on the circuit, but the upper
trace in Figure 2 shows a 6-nsec reset
interval that falls comfortably within
the 10-nsec limit. A path from the cir-

designideas
cuits input to the charge pumps output allows for correction of small nonlinearities due to residual charge injection. This input-derived correction is
effective because the charge injections
effects vary directly with the oscillation
frequency, which the input voltage
determines.
Although you can use the component values given in Figure 1 to assem-

ble prototypes and small production

quantities of the circuit, you need to
consider component selection for optimum manufacturability and high-volume production. Table 1 lists certain
components target values and estimated selection yields. The notes in
Figure 1 list the key components that
the design uses.
To calibrate the circuit, apply 5V to

TABLE 1 SELECTION CRITERIA FOR COMPONENTS

Component
Q1
Q2
D1
IC2A
IC1
IC2A, IC2B

Selection parameter at 25C

ICER20 pA at 3V
IEBO20 pA at 3V
75 pA at 3V; IREV500 pA
IIN25 pA
IB5 pA at VCC5V
Must toggle with 3.6-nsec-wide (at-50%level) input pulse

Typical yield (%)

90
90
80
80
90
80

Cascode MOSFET increases

boost regulators input- and
output-voltage ranges
Scot Lester, Texas Instruments, Dallas, TX

Targeting use in portable-system

applications that require raising
a batterys voltage to a higher level, IC
boost regulators often include output
transistors that can drive storage
inductors. However, most boost regulators absolute-maximum input-voltage rating typically doesnt exceed 6V,
an adequate level for battery operation.
In addition, breakdown voltage of the
regulators output transistor limits the
regulators absolute-maximum output
voltage to 25 to 30V, which may be too
low for some applications.
You can extend a boost regulators
output-voltage range by adding an
external transistor that has a higher
breakdown voltage than the regulator.
However, the internal design of a typical boost regulators control circuitry
often prevents direct drive of an external transistors base or gate. As an alternative, you can add an external higher voltage transistor by connecting it in
a cascode configuration.

86 EDN | SEPTEMBER 1, 2005

Most boost regulators feature a peakcurrent-control method that reduces

the number of external components
and thus shrinks the overall pc-board

the input and adjust the 100-MHz trimmer, R7 for a 100-MHz output. Next,
connect the input to ground and adjust
trimmer R13 for a 1-Hz output. Allow
for an extended settling interval
because, at this frequency, the chargepump update occurs once every 32 sec.
Note that R13s adjustment range
accommodates either a positive or a
negative offset voltage because IC1s
clock output generates a negative bias
voltage for R13. Next, apply 3V to the
input and adjust R9 for a 60-MHz output. A certain amount of interaction
occurs among the adjustments, so
repeat the process until you arrive at
optimum values for the three calibration frequencies.EDN

area of the converter circuit. Figure 1

shows a boost regulator based on a
TPS61040 boost controller, IC1,
which uses peak-current control.
Applying input voltage VIN to IC1s
VCC pin and to one leg of inductor L1
turns on IC1s internal MOSFET
switch, Q1, allowing a gradually
increasing amount of current to flow
from VIN through L1, Q1, and internal
current-sense resistor R1. The circuits
internal controller monitors the volt-

L1

IC1
TPS61040

D1

SW

VOUT
28V

Q1
VIN
6V

VCC

+
C
1

PEAK-CURRENTMODE CONTROL

FB

R1
CFF

RF1

RF2

Figure 1 Based on the barefoot TPS61040, this dc/dc boost converter delivers output voltages only within IC1s ratings.

designideas
common-gate, configuration.
Q2 comprises a low-on-resistance,
low-gate-voltage-threshold MOSFET
with the addition of diode D2 between
Q2s gate and source. To ensure the circuits proper operation, VCC5V in
this examplemust exceed Q2s gatethreshold turn-on voltage. In operation, IC1s internal control circuit turns
on Q1, which pulls Q2s source close to
ground level and turns on Q2 with
almost 5V of gate-to-source potential.
Current flows through inductor L1,
external transistor Q2, internal transistor Q1, and sense resistor R1, and
IC1s control circuit sees no difference
with the installation of Q2. Once the
inductor current reaches its preset
limit, Q1 turns off, leaving Q2 with no
path for current to flow from its source.
The voltage on Q2s drain rises rapidly
to the desired output voltage plus the
voltage drop across D1. As the drain
voltage rises, Q2s drain-to-source
capacitance attempts to pull the
MOSFETs floating source above 5V,
which forward-biases D2, connects

age across sense resistor R1 and, upon

reaching a predetermined current
limit, turns off Q1.
Interrupting the current through L1
raises the voltage across the inductor
and applies forward bias to diode D1,
which conducts and charges output
capacitor C1 to a higher voltage than
would be available from the input voltage alone. The input voltage, L1s
inductance, and the preset peak current
through R1 all affect Q1s on-time, and
the output voltage sensed by IC1s FB
(feedback) pin and its external components determines Q1s off-time. To
maintain operation and set Q1s offtime, IC1s internal controller must
monitor current through L1 using Q1
and R1.
You can add a higher voltage MOSFET transistor, Q2 (Figure 2), for applications that require an output voltage
higher than the internal transistors
breakdown voltage. To maintain the
circuits current-flow path through L1
and IC1s SW pin, you connect the
external transistor in a cascode, or

D1
ES1G

L1

V+
9V
C1
10 F
CERAMIC

IC1s SW pin voltage to 5V plus one

diode drop, and clamps Q2s source to
the same voltage.
A boost converter delivers a 180V
output at 4 mA (VOUT) to bias a laser
circuit from a 9V power supply (V).
In this application, the 5V input supply need provide only enough currenttypically, a few milliamperesto
drive IC1s internal logic and the gate
of cascode MOSFET Q2. You can use a
dropping resistor and zener-diode voltage regulator (not shown) to supply the
5V requirement from the 9V supply.
You can drive the inductor and IC1
from a common power supply or from
a separate source thats within Q2s
breakdown-voltage rating. The cascode
circuit also can produce any output
voltage thats within Q2s drain-tosource breakdown-voltage rating.
Specify other components with an
appropriate voltage ratingfor example, breakdown-voltage ratings of
inductor L1 and capacitor C1 should
safely exceed the desired output voltage.EDN

47 H
CURRENT RATING >0.5A
HIGH-POTENTIAL RATING >200V

IC1
TPS61040

SI4464

SW

C4
+ 1 F
200V
CERAMIC
OR
ALUMINUM

Q2

D2
BAS21

VOUT
180V
4 mA

Q1
VCC
5V

VCC

C2
1 F
CERAMIC

PEAK-CURRENTMODE CONTROL

FB

R1

C3
22 pF
200V

R1
2.21M
200V
R2
15k

Figure 2 Adding an external cascode-connected MOSFET transistor, Q2, with higher breakdown-voltage ratings, enables
the circuit to produce higher output voltages.

88 EDN | SEPTEMBER 1, 2005