Chapter 1

Computer Abstractions and Technology

What is Computer Architecture?

The design of computer systems
Goal: improve performance:
Run programs faster
Execution time: e.g. less waiting time, more simultaneous tasks
Throughput: e.g. higher framerate, faster downloads

Use less power, last longer on battery power

Generate less or more uniformally-distributed heat
Handle more secure encryption standards
Software defined networking at higher line speeds
More scalable
Less expensive

Chapter 1 Computer Abstractions and Technology 2

Computer Architecture
Instruction Set Architecture (architecture)
The native programming language of a processor
Assembly language
Machine language

Openly published to users, licensed for chip makers

Microarchitecture
The internal organization of a processor
Executes programs
Trade secret

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Levels of Program Code

High-level language
Level of abstraction closer to problem
domain
Provides for productivity and portability

Assembly language
Textual representation of instructions

Hardware representation
Binary digits (bits)
Encoded instructions and data

Instruction Set Architecture (ISA):

Assembly code / machine code language

Microarchitecture:
ISA implementation

Chapter 1 Computer Abstractions and Technology 4

Abstraction
Abstration used to manage complexity of design
Hide details that are not important

Program code
Machine
Instructions

Datapaths
Logic gates
Devices
(Transistors)
CSCE 212 5

Why Study Computer Architecture

Compiling machine agnostic code:
Generally achieve ~1-20% of peak theoretical performance
Performance tuned code must be explicitly written for the
underlying architecture
Especially for embedded and special purpose processors
Understanding computer architecture allows for customization:
Multicore
More efficient use of registers, instructions

Device drivers must directly interface with peripherals

Uses CPU-specific, bit-level features to communicate
E.g. memory-mapped I/O, interrupts, DMA, double buffering,
bit fields in status/control registers, memory management,
virtual memory

Chapter 1 Computer Abstractions and Technology 6

Domains and Levels of Modeling

Functional

Structural

high level of
abstraction
low level of
abstraction

Geometric
Chapter 1 Computer Abstractions and Technology 7

Functional Abstraction
For i=0 to 10
C = C + A[i]
MAR <= PC, memory_read <= 1
PC <= PC + 1
wait until ready = 1
IR <= memory_data
memory_read <= 0

Chapter 1 Computer Abstractions and Technology 8

Structural Abstraction

Chapter 1 Computer Abstractions and Technology 9

Semiconductors
Silicon is a group IV element
Forms covalent bonds with
four neighbor atoms (3D cubic
crystal lattice)
Si is a poor conductor, but
conduction characteristics may
be altered
Add impurities/dopants
replaces silicon atom in lattice
Adds two different types of
charge carriers

Spacing = .543 nm
Chapter 1 Computer Abstractions and Technology 10

Layout
3-input NAND

Chapter 1 Computer Abstractions and Technology 11

Feature Size
Shrink minimum feature size

Smaller L decreases carrier time and increases current

Therefore, W may also be reduced for fixed current
Cg, Cs, and Cd are reduced
Transistor switches faster (~linear relationship)

Chapter 1 Computer Abstractions and Technology 12

Minimum Feature Size

Year

Processor

Performance

Transistor Size

Transistors

1982

i286

6 - 25 MHz

1.5 mm

~134,000

1986

i386

16 40 MHz

1 mm

~270,000

1989

i486

16 - 133 MHz

.8 mm

~1 million

1993

Pentium

60 - 300 MHz

.6 mm

~3 million

1995

Pentium Pro

150 - 200 MHz

.5 mm

~4 million

1997

Pentium II

233 - 450 MHz

.35 mm

~5 million

1999

Pentium III

450 1400 MHz

.25 mm

~10 million

2000

Pentium 4

1.3 3.8 GHz

.18 mm

~50 million

2005

Pentium D

2 threads/package

.09 mm

~200 million

2006

Core 2

2 threads/die

.065 mm

~300 million

2008

Nehalem

8 threads/die

.045 mm

~800 million

2009

Westmere

8 threads/die

.045 mm

~1 billion

2011

Sandy Bridge

12 threads/die

.032 mm

~1.2 billion

2013

Ivy Bridge

16 threads/die

.022 mm

~1.4 billion

Year

Processor

Speed

Transistor Size

Transistors

2008

NVIDIA Tesla (GT200)

240 threads/die

.065 mm

1.4 billion

2010

NVIDIA Fermi (GF110)

512 threads/die

.040 mm

3.0 billion

2012

NVNDIA Kepler (GK104)

1536 threads/die

.028 mm

3.5 billion

Chapter 1 Computer Abstractions and Technology 13

Inside the Processor

Apple A5

Chapter 1 Computer Abstractions and Technology 14

Geometric Abstraction

Chapter 1 Computer Abstractions and Technology 15

IC Fabrication

Chapter 1 Computer Abstractions and Technology 16

Si Wafer

Chapter 1 Computer Abstractions and Technology 17

8 Wafer

Chapter 1 Computer Abstractions and Technology 18

8 Wafer

8 inch (200 mm) wafer containing Pentium 4 processors

165 dies, die area = 250 mm2, 55 million transistors, .18mm

1.

Chapter 1 Computer Abstractions and Technology 19

Intel Core i7 Wafer

300mm wafer, 280 chips, 32nm technology

Each chip is 20.7 x 10.5 mm
Chapter 1 Computer Abstractions and Technology 20

Speedup / Relative Performance

Define Performance = 1/Execution Time
X is n time faster than Y

Performance X Performance Y
Execution timeY Execution timeX n

Example: time taken to run a program

10s on A, 15s on B
Execution TimeB / Execution TimeA
= 15s / 10s = 1.5
So A is 1.5 times faster than B
Chapter 1 Computer Abstractions and Technology 21

Integrated Circuit Cost

Cost per wafer
Cost per die
Dies per wafer Yield
Dies per wafer Wafer area Die area
1
Yield
(1 (Defects per area Die area/2))2

Nonlinear relation to area and defect rate

Wafer cost and area are fixed
Defect rate determined by manufacturing process
Die area determined by architecture and circuit design

Chapter 1 Computer Abstractions and Technology 22

Example
Assume C defects per area and a die area of D. Calculate
the improvement in yield if the number of defects is
1
reduced by 1.5.
2

Cost per die

Cost per wafer

Dies per wafer Yield

Dies per wafer Wafer area Die area

Yield

1
(1 (Defects per area Die area/2))2

1.5 2 =
1
2
1+ 2

1+

2
1+ 2
2
1+
1.5 2
2 2
1 + + 4
=
2 2
1+
+ 9
1.5
CSCE 212 23

Cost per die

Example

Cost per wafer

Dies per wafer Yield

Dies per wafer Wafer area Die area

Yield

1
(1 (Defects per area Die area/2))2

Assume a 20 cm diameter wafer has a cost of 15, contains 100 dies, and
has 0.031 defects/cm2.

1. If the number of dies per wafer is increased by 10% and the defects per area unit
increases by 15%, find the die area and yield.

die area20cm = wafer area / dies per wafer = pi*10^2 / (100*1.1) = 2.86 cm2
yield20cm = 1/(1+(0.03*1.15* 2.86/2))^2 = 0.9082
2.

Assume a fabrication process improves the yield from 0.92 to 0.95. Find
the defects per area unit for each version of the technology given a die
area of 200 mm2.
defects per area0.92 = (1-y^.5)/(y^.5*die_area/2) =
(1-0.92^.5)/(0.92^.5*2/2) = 0.043 defects/cm2
defects per area0.95 = (1-y^.5)/(y^.5*die_area/2) =
(1-0.95^.5)/(0.95^.5*2/2) = 0.026 defects/cm2

CSCE 212 24

Response Time and Throughput

Response time
How long it takes to do a task

Throughput
Total work done per unit time
e.g., tasks/transactions/ per hour

How are response time and throughput affected by

Replacing the processor with a faster version?
Adding more processors?

Well focus on response time for now

Chapter 1 Computer Abstractions and Technology 25

Measuring Execution Time

Elapsed time
Total response time, including all aspects
Processing, I/O, OS overhead, idle time

Determines system performance

CPU time
Time spent processing a given job
Discounts I/O time, other jobs shares

Comprises user CPU time and system CPU time

Different programs are affected differently by CPU and
system performance

Chapter 1 Computer Abstractions and Technology 26

CPU Clocking
Operation of digital hardware governed by a
constant-rate clock
Clock period
Clock (cycles)
Data transfer
and computation
Update state

Clock period: duration of a clock cycle

e.g., 250ps = 0.25ns = 2501012 s

Clock frequency (rate): cycles per second

e.g., 4.0GHz = 4000MHz = 4.0109 Hz

Chapter 1 Computer Abstractions and Technology 27

CPU Time
CPU Time CPU Clock Cycles Clock Cycle Time
CPU Clock Cycles

Clock Rate
Performance improved by
Reducing number of clock cycles
Increasing clock rate
Hardware designer must often trade off clock rate against
cycle count

Chapter 1 Computer Abstractions and Technology 28

CPU Time Example

Computer A: 2GHz clock, 10s CPU time
Designing Computer B
Aim for 6s CPU time
Can do faster clock, but causes 1.2 clock cycles

How fast must Computer B clock be?

Clock CyclesB 1.2 Clock CyclesA

Clock RateB

CPU TimeB
6s
Clock Cycles A CPU TimeA Clock Rate A
10s 2GHz 20 109
1.2 20 109 24 109
Clock RateB

4GHz
6s
6s
Chapter 1 Computer Abstractions and Technology 29

Instruction Count and CPI

Clock Cycles Ins truction Count Cycles per Ins truction
CPU Tim e Ins truction Count CPI Clock Cycle Tim e
Ins truction Count CPI

ClockRate
Instruction Count for a program
Determined by program, ISA and compiler

Average cycles per instruction

Determined by CPU hardware
If different instructions have different CPI
Average CPI affected by instruction mix

Chapter 1 Computer Abstractions and Technology 30

CPI Example

Computer A: Cycle Time = 250ps, CPI = 2.0

Computer B: Cycle Time = 500ps, CPI = 1.2
Same ISA
Which is faster, and by how much?
CPU Time

CPU Time

Instruction Count CPI Cycle Time

A
A
I 2.0 250ps I 500ps
A is faster
Instruction Count CPI Cycle Time
B
B
I 1.2 500ps I 600ps

B I 600ps 1.2
CPU Time
I 500ps
A
CPU Time

by this much

Chapter 1 Computer Abstractions and Technology 31

CPI in More Detail

If different instruction classes take
different numbers of cycles
n

Clock Cycles (CPIi Instruction Counti )

i1

Weighted average CPI

n
Clock Cycles
Instruction Counti

CPI
CPIi

Instruction Count i1
Instruction Count

Relative frequency
Chapter 1 Computer Abstractions and Technology 32

CPI Example
Alternative compiled code sequences using
instructions in classes A, B, C

Class

CPI for class

IC in sequence 1

IC in sequence 2

Sequence 1: IC = 5

Clock Cycles
= 21 + 12 + 23
= 10
Avg. CPI = 10/5 = 2.0

Sequence 2: IC = 6

Clock Cycles
= 41 + 12 + 13
=9
Avg. CPI = 9/6 = 1.5

Chapter 1 Computer Abstractions and Technology 33

Performance Summary
Instructions Clock cycles Seconds
CPU Time

Program
Instruction Clock cycle
Performance depends on

Algorithm: affects IC, possibly CPI

Programming language: affects IC, CPI
Compiler: affects IC, CPI
Instruction set architecture: affects IC, CPI, Tc

Chapter 1 Computer Abstractions and Technology 34

Example
Suppose one machine, A, executes a program with an
average CPI of 2.1
Suppose another machine, B (with the same instruction set
and an enhanced compiler), executes the same program
with 25% less instructions and with a CPI of 1.8 at 800MHz
In order for the two machines to have the same performance,
what does the clock rate of the first machine (machine A)
need to be?

=

2.1 0.75 1.8

=

800 106

CSCE 212 35

Example
Suppose a program has the following instruction classes, CPIs,
and mixtures:
Instruction type
CPI
ratio
A
1.4
55%
B
2.4
15%
C
2
30%
Your engineers give you the following options:
Option A: Reduce the CPI of instruction type A to 1.1
Option B: Reduce the CPI of instruction type B to 1.2
Which option would you choose and why?
= .55 1.1 + .15 2.4 + .30 2 = 1.565
= .55 1.4 + .15 1.2 + .30 2 = 1.550
CSCE 212 36

Pitfall: MIPS as a Performance Metric

MIPS: Millions of Instructions Per Second
Doesnt account for
Differences in ISAs between computers
Differences in complexity between instructions

Instruction count
MIPS
Execution time 106
Instruction count
Clock rate

6
Instruction count CPI
CPI

10
6
10
Clock rate

CPI varies between programs on a given CPU

Chapter 1 Computer Abstractions and Technology 37

Example

Consider two different implementations, M1 and M2, of the same instruction set.
There are three classes of instructions (A, B, and C) in the instruction set. M1 has a
clock rate of 800 MHz and M2 has a clock rate of 2 GHz. The average number of
cycles for each instruction class and their frequencies (for a typical program) are as
follows:

Instruction class
A
B
C

Machine M1 CPI
1
2
4

Frequency
50%
20%
30%

Machine M2 CPI
2
3
4

Frequency
60%
30%
10%

Calculate the average CPI for each machine, M1, and M2.

M1 => .5(1) + .2(2) + .3(4) = 2.1

M2 => .6(2) + .3(3) + .1(4) = 2.5
Calculate the average MIPS ratings for each machine, M1 and M2.
Hint: MIPS = (clock rate / CPI) / 106.

M1 => 800 * 2.1 = 1680

M2 => 2000 * 2.5 = 5000
CSCE 212 38

Example (Cont)
How many less instructions would M1 need to execut to
match the speed of M2?
M1 => 800 * 2.1 = 1680
M2 => 2000 * 2.5 = 5000

5000/1680

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Power Trends

In CMOS IC technology

Power Capacitive load Voltage 2 Frequency

30

5V 1V

1000

Chapter 1 Computer Abstractions and Technology 40

Reducing Power
Suppose a new CPU has
85% of capacitive load of old CPU
15% voltage and 15% frequency reduction

Pnew Cold 0.85 (Vold 0.85)2 Fold 0.85

4

0.85
0.52
2
Pold
Cold Vold Fold

The power wall

We cant reduce voltage further

We cant remove more heat

How else can we improve performance?

Chapter 1 Computer Abstractions and Technology 41

Example
Assume:
Processor
Pentium 4
Core i5

Clock
3.6 GHz
3.4 GHz

Voltage
1.25 V
0.9 V

Dynamic P
90 W
40 W

Static P
10 W
30 W

Calculate capacitive load of each processor.

If total power is to be reduced by 10%, how much should the
voltage be reduced?

CSCE 212 42

Example
For given processor, assume we reduce the voltage by 10%
and increase the frequency by 5%. What is the
improvement to dynamic power consumption?

2
2
=
=
.9 2 (1.05)
.9 2 (1.05)
2
1
=
=
= 1.18
.81 2 (1.05) .81(1.05)

CSCE 212 43

Fallacy: Low Power at Idle

i7 power benchmark
At 100% load: 258W
At 50% load: 170W (66%)
At 10% load: 121W (47%)

Google data center

Mostly operates at 10% 50% load
At 100% load less than 1% of the time

Consider designing processors to make power proportional

to load

Chapter 1 Computer Abstractions and Technology 44

SPEC Power Benchmark

Power consumption of server at different
workload levels
Performance: ssj_ops/sec
ssj_ops = server side Java operations per second

Power: Watts (Joules/sec)

10
10

Overall ssj_opsper Watt ssj_opsi poweri

i 0
i 0

Chapter 1 Computer Abstractions and Technology 45

SPECpower_ssj2008 for Xeon X5650

Chapter 1 Computer Abstractions and Technology 46

SPEC CPU Benchmark

Programs used to measure performance
Supposedly typical of actual workload

Standard Performance Evaluation Corp (SPEC)

Develops benchmarks for CPU, I/O, Web,

SPEC CPU2006

Elapsed time to execute a selection of programs

Negligible I/O, so focuses on CPU performance

Normalize relative to reference machine

Summarize as geometric mean of performance ratios
CINT2006 (integer) and CFP2006 (floating-point)
n

Execution time ratio

i1

Chapter 1 Computer Abstractions and Technology 47

CINT2006 for Intel Core i7 920

Chapter 1 Computer Abstractions and Technology 48

Pitfall: Amdahls Law

Improving an aspect of a computer and
expecting a proportional improvement in overall
performance

Timproved

Example: multiply accounts for 80s/100s

Taffected

Tunaffected
improvement factor

How much improvement in multiply performance to get 5

overall?

80
Cant be done!
20
20
n
Corollary: make the common case fast
Chapter 1 Computer Abstractions and Technology 49

Example
Use Amdahls Law to compute the new execution time for
an architecture that previously required 25 seconds to
execute a program, where 15% of the time was spent
executing load/store instructions, if the time required for a
load/store operation is reduced by 40% (amount of
improvement for load/stores = 1/.60 = 1.67).

CSCE 212 50

Example
Suppose you have a machine which executes a program
consisting of 50% multiply instructions, 20% divide
instructions, and the remaining 30% are other instructions.
Management wants the machine to run 4 times faster. You
can make the divide run at most 3 times faster and the
multiply run at most 8 times faster. Can you meet
managements goal by making only one improvement, and
which one?

CSCE 212 51

Multiprocessors
Multicore microprocessors
More than one processor per chip

Requires explicitly parallel programming

Compare with instruction level parallelism
Hardware executes multiple instructions at once
Hidden from the programmer

Hard to do
Programming for performance
Load balancing
Optimizing communication and synchronization

Chapter 1 Computer Abstractions and Technology 52

Example
Assume the following instruction classes and corresponding CPIs
and dynamic execution counts:
Type

CPI Count

arithmetic

load/store

branch

When run on > 1 processors, the number of executed arithmetic

instructions is divided by 0.7p (where p = number of processors)
but the number of other instructions executed remains the same.
To what factor would the CPI of load/store instructions need to be
reduced (sped up) in order for a single processor to match the
performance of four processors each having the original CPI?

+
+ =
+ +

0.7 4
CSCE 212 53

Example
Assume the following instruction classes and corresponding CPIs
and dynamic execution counts:
Type

CPI Count

arithmetic

load/store

branch

As compared to a single processor, under what condition is it

possible to achieve an overall speedup of 6 by using multiple
processors? Express this as an inequality.

1 ++
+

+
6
.7
++

CSCE 212 54

Concluding Remarks
Cost/performance is improving
Due to underlying technology development

Hierarchical layers of abstraction

In both hardware and software

Instruction set architecture

The hardware/software interface

Execution time: the best performance

measure
Power is a limiting factor
Use parallelism to improve performance
Chapter 1 Computer Abstractions and Technology 55