Sprabw0b PDF

Application Report
SPRABW0B May 2014 Revised June 2015
Voltage Fed Full Bridge DC-DC and DC-AC Converter for

High-Frequency Inverter Using C2000
Atul Singh and Jabir VS
ABSTRACT
The High-Frequency Inverter is mainly used today in uninterruptible power supply systems, AC motor
drives, induction heating and renewable energy source systems. The simplest form of an inverter is the
bridge-type, where a power bridge is controlled according to the sinusoidal pulse-width modulation
(SPWM) principle and the resulting SPWM wave is filtered to produce the alternating output voltage. In
many applications, it is important for an inverter to be lightweight and of a relatively small size. This can be
achieved by using a High-Frequency Inverter that involves an isolated DC-DC stage (Voltage Fed PushPull/Full Bridge) and the DC-AC section, which provides the AC output. This application report documents
the implementation of the Voltage Fed Full Bridge isolated DC-DC converter followed by the Full-Bridge
DC-AC converter using TMS320F28069 (C2000) for High-Frequency Inverters.
Project collateral and source code discussed in this document can be downloaded from this URL:
http://www.ti.com/lit/zip/sprabw0.
Contents
1
Basic Inverter Concept ..................................................................................................... 2
2
High-Frequency Inverter Block Diagram ............................................................................... 3
3
DC-DC Isolation Stage - High-Frequency Inverter ..................................................................... 4
4
DC-AC Converter ........................................................................................................... 7
5
DC-DC Converter Section (Voltage Fed Full Bridge) ................................................................... 7
6
Control Section ............................................................................................................. 10
7
DC-AC Converter Section ................................................................................................. 10
8
Firmware Flowchart ........................................................................................................ 12
9
Waveforms .................................................................................................................. 13
10
Conclusion .................................................................................................................. 14
11
References .................................................................................................................. 14
Appendix A
Application Schematic ............................................................................................ 15
List of Figures
...........................................................................................................
50 Hz Technology
Transformerless Inverter Technology ..................................................................................... 2
High-Frequency Inverter Technology
High-Frequency Inverter Block Diagram
5
6
7
8
9
10
11
12
13
..................................................................................... 3
............................................................................... 3
Push-Pull Toplogy ........................................................................................................... 4
Half Bridge Converter ....................................................................................................... 5
Full Bridge Converter ........................................................................................................ 6
Functional Block Diagram of UCC27211 ................................................................................. 8
Gate Drive Waveforms for the Full Bridge DC-DC Converter ......................................................... 9
Functional Block Diagram ................................................................................................. 11
Firmware Flowchart ........................................................................................................ 12
Output Voltage at No Load................................................................................................ 13
Output Voltage and Current (100W Load) .............................................................................. 13

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Voltage Fed Full Bridge DC-DC and DC-AC Converter for High-Frequency
Inverter Using C2000
Copyright 20142015, Texas Instruments Incorporated
Basic Inverter Concept
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14
DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge) .................................................... 15
15
Control Section Schematic
16
DC-AC Converter Schematic
...............................................................................................
............................................................................................
16
17
Basic Inverter Concept

There are basically three different inverter technologies:
Inverter with a 50 Hz transformer
Inverter without a transformer
Inverter with a high-frequency (HF) transformer
S1
S3
S2
S4
L1
C1
Figure 1. 50 Hz Technology
The applied DC voltage is converted to a 50 Hz AC voltage via a full bridge (S1...S4). This is then
transmitted via a 50 Hz transformer and subsequently fed into the public grid.
Benefits:
High degree of reliability due to fewer components
Safety through galvanic isolation of the DC and AC sides
Disadvantages:
Low degree of efficiency resulting from high transformer losses
Heavy weight and volume (for example, due to 50 Hz transformer)
S1
S3
L1
C1
L2
S2
S4
Figure 2. Transformerless Inverter Technology
C2000, Piccolo are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.
2

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The existing DC voltage is converted to a square 50 Hz AC voltage via a full bridge (S1...S4), then
smoothed to a sinusoidal 50 Hz AC voltage via the chokes (L1+L2) and fed into the public grid.
Benefits:
Compact and light due to lack of transformer
Very high degree of efficiency (for example, no transformer losses)
Disadvantages:
Additional safety measures (residual current circuit breaker) required. In some countries, a lack of
galvanic isolation between the DC and AC sides is not permitted.
Complicated lightning protection
Not compatible with modules that must be earthed
L1
S1
D1
S3
D3
S5
S7
Tr1
C1
L2
C2
L3
D2
S2
D4
S4
S6
S8
Figure 3. High-Frequency Inverter Technology

The full bridge (S1...S4) generates a high-frequency square-wave signal with 40 50 kHz, which is
transmitted via the HF transformer (Tr1). The bridge rectifiers (D1...D4) convert the square-wave signal
back to DC voltage and store it in the intermediate circuit (L1+C2). A second full bridge (S5...S8) then
generates a 50 Hz AC voltage, which is smoothed to a sinusoidal 50 Hz AC voltage via the chokes
(L2+L3) before being fed into the public grid.
Benefits:
Compact and light, as the HF transformer is very small and light
High degree of efficiency through reduction of transformer losses
Safety through galvanic isolation between the DC and AC sides
Suitable for all module technologies, as module earthing (positive and negative) is possible

AC Input
EMI Filter
AC-DC Isolated
Power Supply
DPDT Relay
Load
TMS320F28069
C2000 Series
DC-DC
Isolation Stage
Battery
DC-AC
Converter
LC Filter
Figure 4. High-Frequency Inverter Block Diagram

DC-DC Isolation Stage - High-Frequency Inverter
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The present application report documents the implementation of the DC-DC isolation and DC-AC
conversion stage using TMS320F28069. The F2806x Piccolo family of microcontrollers provides the
power of the C28x core and the Control Law Accelerator (CLA) coupled with highly integrated control
peripherals in low-pin count devices. This family is code-compatible with previous C28x-based code, as
well as providing a high level of analog integration. An internal voltage regulator allows for single-rail
operation. Enhancements have been made to the high-resolution pulse width modulator (HRPWM) module
to allow for dual-edge control (frequency modulation).
Analog comparators with internal 10-bit references have been added and can be routed directly to control
the pulse width modulation (PWM) outputs. The analog-to-digital converter (ADC) converts from 0 to 3.3-V
fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been
optimized for low overhead and latency. The above features make the F2806x Piccolo suitable for
handling both the stages of the High-Frequency Inverter.
The main blocks of the High-Frequency Inverter include:
DC-DC isolation stage
DC-AC converter section

The selection of the DC-DC isolation stage for the High-Frequency Inverter depends on the kVA
requirements of the inverter. The power supply topologies suitable for the High-Frequency Inverter
includes push-pull, half-bridge and the full-bridge converter as the core operation occurs in both the
quadrants, thereby, increasing the power handling capability to twice of that of the converters operating in
single quadrant (forward and flyback converter). The push-pull and half-bridge require two switches while
the full-bridge requires four switches. Generally, the power capability increases from push-pull to halfbridge to full-bridge.
D1
+
VOUT
np
ns
np
ns
D2
VIN
Q2
PUSH
Q1
PULL
Figure 5. Push-Pull Toplogy

The Push-Pull topology is basically a forward converter with two primaries. The primary switches
alternately power their respective windings. When Q1 is active, current flows through D1. When Q2 is
active, current flows through D2. The secondary is arranged in a center tapped configuration as shown in
Figure 5. The output filter sees twice the switching frequency of either Q1 or Q2. The transfer function is
similar to the forward converter, where D is the duty cycle of a given primary switch, which accounts for
the 2X term. When neither Q1 nor Q2 are active, the output inductor current splits between the two
output diodes.
A transformer reset winding shown on the forward topology is not necessary, the topology is self resetting.
Ns
Vout = Vin D
2
Np
(1)

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3.1
Half Bridge Converter

The Half Bridge converter is similar to the Push-Pull converter, but a center tapped primary is not required.
The reversal of the magnetic field is achieved by reversing the direction of the primary winding current
flow. In this case, two capacitors, C1 and C2, are required to form the DC input mid-point. Transistors Q1
and Q2 are turned ON alternately to avoid a supply short circuit, in which case the duty cycle d must be
less than 0.5.
+VIN
D1
T1
Q1
L1
+VOUT
C1
+
C3
0V
+
C2
0V
Q2
D2
Figure 6. Half Bridge Converter

For the Half-Bridge converter, the output voltage VOUT equals:
N
Vout = Vin 2 d
N1
(2)
Where, d is the duty cycle of the transistors and 0 < d < 0.5.
N2/N1 is the secondary to primary turns ratio of the transformer.
3.2
Full Bridge Converter

The transformer topology for both the Half Bridge and Full Bridge converter is the same, except that for a
given DC link voltage of the Half Bridge transformer sees half the applied voltage as compared with that of
the Full Bridge transformer. The current flows in opposite directions during alternate half cycles. So flux in
the core swings from negative to positive, utilizing even the negative portion of the hysteresis loop,
thereby, reducing the chances of core saturation. Therefore, the core can be operated at greater Bm value
here. The largest power is transferred when the duty cycle is less than 50%. Diagonal pairs of transistors
(Q1-Q4 or Q2-Q3) conduct alternately, thus, achieving current reversal in the transformer primary.
Output voltage equals:
N
Vout = 2 Vin 2 d
N1
(3)
Where, d is the duty cycle of the transistors and 0 < d < 0.5.
N2/N1 is the secondary to primary turns ratio of the transformer.

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+VIN
L1
D1
T1
Q1
Q3
+VOUT
+
+
C2
+
C1
0V
Q2
Q4
D2
0V
Figure 7. Full Bridge Converter

The choice of the DC-DC isolation stage for the High-Frequency Inverter among the three topologies
discussed above depends on the VA requirement. For applications targeting 1KVA and above, the Full
Bridge converter is the ideal choice pertaining to the points below:
For a given input voltage, the voltage stress on the transistors is double in case of the push-pull
topology than Half Bridge and Full Bridge configuration.
The center tapped primary in the case of the push-pull converter limits the operation for a higher VA
rating for the same core size when compared to the Half Bridge and Full Bridge converter.
To prevent flux walking in the DC-DC stage, the current in both the halves need to be sensed and the
duty cycle needs to be corrected accordingly.
3.2.1
Flux Walking
Faradays Law states that the flux through a winding is equal to the integral volt-seconds per turn. This
requires that the voltage across any winding of any magnetic device must average zero over a period of
time. The smallest DC voltage component in an applied AC waveform will slowly but inevitably walk the
flux into saturation.
In a low frequency mains transformer, the resistance of the primary winding is usually sufficient to control
this problem. As a small DC voltage component pushes the flux slowly toward saturation, the magnetizing
current becomes asymmetrical. The increasing DC component of the magnetizing current causes an IR
drop in the winding, which eventually cancels the DC voltage component of the drive waveform, hopefully
well short of saturation. In a high frequency switchmode power supply, a push-pull driver will theoretically
apply equal and opposite volt-seconds to the windings during alternate switching periods, thus, resetting
the core (bringing the flux and the magnetizing current back to its starting point). But there are usually
small volt second asymmetries in the driving waveform due to inequalities in MOSFET RDSon or switching
speeds. The resulting small DC component causes the flux to walk. The high frequency transformer, with
relatively few primary turns, has extremely low DC resistance, and the IR drop from the DC magnetizing
current component is usually not sufficient to cancel the volt-second asymmetry until the core reaches
saturation.

DC-AC Converter
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The flux walking problem is a serious concern with any Push-Pull topology (bridge, half-bridge or push-pull
CT), when using voltage mode control. One solution is to put a small gap in series with the core. This
raises the magnetizing current so that the IR drop in the circuit resistances is able to offset the DC
asymmetry in the drive waveform. But the increased magnetizing current represents increased energy in
the mutual inductance, which usually ends up in a snubber or clamp, increasing circuit losses. A more
elegant solution to the asymmetry problem is an automatic benefit of using the current mode control (peak
or average CMC). As the DC flux starts to walk in one direction, due to the volt-second drive asymmetry,
the peak magnetizing current becomes progressively asymmetrical in alternate switching periods.
However, current mode control senses the current and turns off the switches at the same peak current
level in each switching period, so that ON times are alternately lengthened and shortened. The initial voltsecond asymmetry is thereby corrected, peak magnetizing currents are approximately equal in both
directions, and flux walking is minimized.
However, with the Half Bridge topology this creates a new problem. When current mode control corrects
the volt-second inequality by shortening and lengthening alternate pulse widths, an ampere-second
(charge) inequality is created in alternate switching periods. This is of no consequence in full bridge or
push-pull center-tap circuits, but in the half-bridge, the charge inequality causes the capacitor divider
voltage to walk towards the positive or negative rail. As the capacitor divider voltage moves away from the
mid-point, the volt-second unbalance is made worse, resulting in further pulse width correction by the
current mode control. A runaway situation exists, and the voltage will walk (or run) to one of the rails.
Considering the above points, the Full Bridge converter seems to be the ideal choice for the HighFrequency Inverter rated above 1kVA.
DC-AC Converter
The DC-AC Converter section of the High-Frequency Inverter is an H-Bridge, which converts the high
voltage DC bus (380 V) into sinusoidal AC waveform.
The sinusoidal PWM generation is done using the PWM interrupt handler in TMS320F28069 by entering
into an infinite loop. A look-up table is formed that samples the instantaneous values at specific time
intervals based on the operating frequency of the DC-AC section. The DC-AC section is operated at 20
kHz, based on that the total number of samples for half cycle is 200. The instantaneous value is then
multiplied by the maximum duty cycle count to get the duty cycle count at the corresponding sample
instant. This generates the sinusoidal PWM for the full bridge section. The DC-AC section consists of
high-side and low-side drivers to drive the Mosfets in the H-Bridge configuration followed by an output LC- L filter resulting in sinusoidal sine wave.
DC-DC Converter Section (Voltage Fed Full Bridge)

The DC-DC section consists of 120 V boot, 4A peak high frequency high-side and low-side driver
UCC27211 for driving the high-side and low-side FETs of the Full Bridge converter.
In UCC27211, the high side and low side each have independent inputs, which allow maximum flexibility
of input control signals in the application. The boot diode for the high-side driver bias supply is internal to
the chip. The UCC27210 is the pseudo-CMOS compatible input version and the UCC27211 is the TTL or
logic compatible version. The high-side driver is referenced to the switch node (HS), which is typically the
source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is
referenced to VSS, which is typically ground. The functions contained are the input stages, UVLO
protection, level shift, boot diode, and output driver stages.

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Figure 8 shows the independent control of the high-side and low-side drivers and the internal bootstrap
diode capable of withstanding the reverse voltage up to 120 V.
HB
HO
HS
LO
VSS
UVLO
Level
Shift
HI
VDD
1
UVLO
LI
Figure 8. Functional Block Diagram of UCC27211

The VDD supply of the IC is derived from the 12 V battery itself (HF inverter source). The DC-DC stage
converts the 12 V input voltage to a regulated 380 V DC bus, which is the input to the DC-AC section. To
avoid battery inrush current at the start of the PWM, soft start is implemented that controls the rate of di/dt.
The PWMs initially start with a very low duty and finally duty cycle is adjusted as per the regulation point
of the DC bus voltage (380 V). The operating frequency for the switches in the DC-DC section is 40 kHz,
the output filter sees twice the frequency of the switches M6 or M9 (see Figure 14).
5.1
Voltage Fed Full Bridge Converter Transformer Calculation
Total Output Power Po = (Vo + Vrl + Vd) Io
Where,
The Area Product for this configuration is given as:
Ap =
Po 2 + (1/ h)
4.Kw .J.Bm.Fsw
Where,
Vo = Output voltage
Vrl = Voltage drop due to winding resistance
Vd= Forward voltage drop of the output diode
Io= Output current
= Efficiency of the Full Bridge converter

Kw = Window factor
J = Current Density (A/m2)
Bm = Magnetic flux density
Fsw = Switching frequency

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Primary Number of Turns
Np =
Vin (maximum )
4.Ac.Bm.Fsw
Where, Ac= Core area
Vin (maximum) = Maximum input voltage applied to the Full Bridge converter
Turns Ratio
n=
(Vo + Vrl + Vd )
2.D max .Vin min

Where, Vin min = Minimum input voltage applied to the Full Bridge converter
Secondary turns Ns = n x Np
RMS Values of Currents
Where,
Isec = IoDmax
Ipri = n x Io
Isec = Secondary current
Ipri = Primary current
Using the above calculations, the number of turns can be calculated for the required output power and the
rms values of the primary and secondary currents can also be found out for a given core area.
The calculation was done considering 1kVA requirement with battery input as the input voltage (12 V) in
EF32 core and the corresponding numbers of turns were calculated for both primary and secondary.
Figure 9. Gate Drive Waveforms for the Full Bridge DC-DC Converter
In order to minimize flux walking, as discussed Section 3.2.1, the peak current in each of the conducting
halves can be sensed using the fully differential isolation amplifier AMC1100.

Control Section
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The AMC1100 is a precision isolation amplifier with an output separated from the input circuitry by a
silicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been
certified to provide galvanic isolation of up to 4250 V peak, according to UL1577 and IEC60747-5-2. Used
in conjunction with isolated power supplies, this device prevents noise currents on a high common-mode
voltage line from entering the local ground and interfering with or damaging sensitive circuitry.
After sensing the peak current, the duty cycle is corrected for each of the corresponding halves and volt
second asymmetry is thereby corrected, to minimize flux walking.
Control Section
The control section consists of TMS320F28069 performing the control operation generating PWMs for
both DC-DC section and SPWMs for the DC-AC section using the PWM interrupt handler.
MCU PWM Outputs
DC-DC section
PWM1DH_MCU = High-Side Input Gate Drive 1
PWM1DL_MCU = Low-Side Input Gate Drive 1
PWM2DH_MCU = High-Side Input Gate Drive 2
PWM2DL_MCU = Low-Side Input Gate Drive 2
DC-AC section:
PWM1AH_MCU = High-Side Input Gate Drive 1 for IRS21867S
PWM1AL_MCU = Low-Side Input Gate Drive 1 for IRS21867S
PWM2AH_MCU = High-Side Input Gate Drive 2 for IRS21867S
PWM2AL_MCU = Low-Side Input Gate Drive 2 for IRS21867S
The Opto couplers HCPL-0211 provides isolated gate drives for the DC-DC section:
PWM1DH = High-Side Input Gate Drive for UCC27211 (Driver 1)
PWM1DL = Low-Side Input Gate Drive for UCC27211 (Driver 1)
PWM2DH = High-Side Input Gate Drive for UCC27211 (Driver 2)
PWM2DL = Low-Side Input Gate Drive for UCC27211 (Driver 2)
DC-AC Converter Section

The DC-AC converter section consists of high- and low-side driver IRS21867S, which is a high-voltage,
high-speed power Mosfet and IGBT driver with independent low side and high side referenced output
channels. It has a floating channel designed for bootstrap operation and fully operational to +600 V. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration, which operates up to 600 V.
10

DC-AC Converter Section
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Figure 10 shows the functional block diagram of the driver. The bootstrap diode is placed external to the
driver and the device can handle peak currents up to 4A.
VB
UV
Detect
R
HIN
VSSCOM
Level
Shift
HV Level
Shifter
Pulse
Filter
R
S
Q
HO
Q
Pulse
Generator
VS
VCC
UV
Detect
LO
LIN
VSSCOM
Level
Shift
Delay
COM
Figure 10. Functional Block Diagram

The AC voltage feedback to the MCU for closed-loop control is given by scaling down the voltage by a
resistor divider network and rectifying it by means of a precision rectifier circuit. The precision rectifier
circuit is built with the high-speed precision difference amplifier INA143 followed by TL082 powered from a
dual supply (12 V). The rectified and scaled down Sine wave is fed to the MCU for closed-loop control of
the output voltage.
The load current sense is done using ACS709, which is a precision linear Hall sensor integrated circuit
with copper conduction path. Applied current flows through the copper conduction path, and the analog
output voltage from the Hall sensor IC linearly tracks the magnetic field generated by the applied current.
The voltage on the overcurrent input (VOC pin) allows to define an overcurrent fault threshold for the
device. When the current flowing through the copper conduction path (between the IP+ and IP pins)
exceeds this threshold, the open drain overcurrent fault pin transitions to a logic-low state and can be
used to shut down the PWM pulses of the DC-AC section and DC-DC section as well to provide protection
against overload and short circuit of the load.

11
Firmware Flowchart
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Firmware Flowchart
Power on reset
Set the clock to 60 MHz

Initialize GPIO
Initialize ADC
Initialize PWM1 for DC-DC Conversion

Configure the PWM1 Interrupts
Start the PWM switching

with very low duty cycle for
soft start
Is the DC BUS
voltage equal
to 380 Volts?
NO
Increase the
Duty Cycle
YES
Initialize PWM2 for DC-AC conversion
Configure the PWM2 Interrupts
Generate the Sine

modulated PWM using the
PWM Interrupt Handler
Enter Infinite loop and

operate using the interrupt
handlers
Figure 11. Firmware Flowchart
12

Waveforms
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Waveforms
Figure 12. Output Voltage at No Load
Figure 13. Output Voltage and Current (100W Load)

13
Conclusion
10
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Conclusion
This application report documents the concept reference design for the DC-DC Stage and the DC-AC
Converter section that can be used in the High-Frequency Inverter using TMS320F28069, which handles
the PWM generation and closed loop control of both the stages.
The reference design was tested for 100W load and can be further tested at higher VA ratings modifying
the power components of the DC-AC Converter Section. The reference design is targeted for HighFrequency Inverters rated for higher VA used in the industrial segment.
11
References
1. Analysis of a Voltage-fed Full Bridge DC-DC Converter in Fuel Cell Systems by A. Averberg, A.
Mertens, Power Electronics Specialists Conference, 2007. PESC 2007. IEEE.
2. A Current Mode Control Technique with Instantaneous Inductor Current Feedback for UPS Inverter by
H.Wu, D.Lin, D. Zhang, K. Yao, J.Zhang, IEEE transaction, 1999.
3. Power Electronics Converter, Applications and Design by Mohan, T.M. Undeland, and W.P. Robbins.
4. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065,
TMS320F28064, TMS320F28063, TMS320F28062 Piccolo Microcontrollers Data Manual (SPRS698)
14

PWM2DL
PWM2DH
PWM1DL
VBAT
VDD
LO
HS
HO
HB
C82
4.7uF
UCC27211
VSS
LI
HI
LO
HS
HO
HB
UCC27211
VSS
LI
HI
VDD
U19
U18
VBAT
C83
100nF
C81
100nF
D16
15V
2
1
C78
100nF
2
1

3
D16A
15V
TL1963A
GND
IN
SHDN
U20
4.7E
R70
4.7E
R68
D22A
15V
4.7E
R65
4.7E
R62
D22
15V
C74
100nF
2
1
C73
4.7uF
6
TAB

ADJ
OUT
R86
100k
R87
31.926k
1DL
C1D
1DH
2DL
C2D
2DH
1
2
C35
10uF
VBAT
J4
1DL
M8
PHP20NQ20T
C1D
1DH
PHP20NQ20T
M6
VBAT
R85
25mOhm
PHP20NQ20T
M9
2DH
2DL
4700pF/2kV
C2D C94
M7
PHP20NQ20T
T2
EE32/16/9
10
9
8
13
14
5VDC
3
4
5
6
PWM1DH
VBAT
AMC1100
GND1GND2
VINN VOUN
VINP VOUP
VDD1 VDD2
U21
3.3VDCISO
D21
DSEP8-12A
D17
DSEP8-12A
D23
DSEP8-12A
ISWADC
2 3 4 5 6 7
9 1011121314
L7
D20
DSEP8-12A
EE32/16/9
C80
220uF
380VDC
Appendix A
Application Schematic
Figure 14. DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge)
15
3.3VDCISO
2.2K
R12
R75
330E
R74
330E
LED2
SW DPST
SW1
BEAD
R76
330E
D29
LED
LED3
ADJ
OUT
ADJ
OUT
C21
100nF
C13
2.2uF
TL1963A
GND
IN
SHDN
U5
D28
LED
LED1
TCK
TDI
TDO
TMS
TRSTn
C17A
2.2uF
L2
TL1963A
GND
D27
LED
12VDC ISO
IN
6
TAB
6
TAB
SHDN
R4
100k
R10
100k
LED4
R77
330E
D30
LED
C13A
2.2uF
C14A
2.2uF
3.3VDCISO
2
C20
2.2uF
C17
2.2uF
2.2K
R13
PWM1DL_MCU
PWM1DH_MCU
C19
2.2uF
C14B
2.2uF
R14A
2.2K
C18B
2.2uF
C18A
1
2.2uF
R14
2.2K
C14
2.2uF
5VDC ISO
C18
2.2uF
C9
10uF
C3
10uF
C13B
2.2uF
C17B
2.2uF
3.3VDCISO
R11
31.926k
R32
57.9k
3.3VDCISO
53
21
3
13
28
38
50
64
73
48
47
36
10
54
58
57
56
9
71
2
12
29
51
65
72
20
37
4
11
30
49
63
74
R8
1.5k
U8
TEST
TRSTn
TCK
TMS
TDI
TDO
XRSn
VREGENZ
Vdd18
Vdd18
Vdd18
Vdd18
Vdd18
Vdd18
VdADC33
VdFL33
GPIO-39
ADCGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
X1
X2
SHIELD
GPIO-16
GPIO-17
GPIO-18
GPIO-19
GPIO-20
GPIO-21
GPIO-22
GPIO-23
GPIO-24
GPIO-25
GPIO-26
GPIO-27
GPIO-28
GPIO-29
GPIO-30
GPIO-31
GPIO-32
GPIO-33
GPIO-34
GPIO-00
GPIO-01
GPIO-02
GPIO-03
GPIO-04
GPIO-05
GPIO-06
GPIO-07
GPIO-08
GPIO-09
GPIO-10
GPIO-11
GPIO-12
GPIO-13
GPIO-14
GPIO-15
CMP2B/ADC-B4
ADC-B5
CMP3B/ADC-B6
ADC-B0
ADC-B1
CMP1B/ADC-B2
CMP2A/ADC-A4
ADC-A5
CMP3A/ADC-A6
ADC-A0
ADC-A1
CMP1A/ADC-A2
TMS320F28069U-PFP
HCPL-0211
U6
12VDC
12VDC
8
SHIELD
HCPL-0211
U2
VdIO33
VdIO33
VdIO33
VdIO33
VdIO33
VdIO33
R1
1.5k
U1
44
42
41
52
5
6
78
1
77
31
62
61
40
34
33
32
79
80
55
69
68
67
66
7
8
46
45
43
39
60
59
35
75
76
70
25
26
27
GPIO-16
GPIO-17
GPIO-18
GPIO-19
GPIO-12
LED1
LED2
LED3
LED4
RXD
TXD
PWM1DL
PWM2DL_MCU
PWM1DH
GPIO-00
GPIO-01
GPIO-02
GPIO-03
GPIO-04
GPIO-05
GPIO-06
GPIO-07
ADC-B4
ADC-B5
ADC-B6
ADC-B0
ADC-B1
ADC-B2
ADC-A4
ADC-A5
ADC-A6
16
15
14
22
23
24
ADC-A0
ADC-A1
ADC-A2
19
18
17
C8
0.1uF
C2
0.1uF
PWM2DH_MCU
VADC
PWM1AH_MCU
PWM1AL_MCU
12VDC
SHIELD
PWM2AH_MCU
PWM2AL_MCU
PWM2DH_MCU
PWM2DL_MCU
IADC
VBUS
ISWADC
TP1
TEST POINT
HCPL-0211
U4
R7
1.5k
12VDC
SHIELD
HCPL-0211
U3
PWM1DH_MCU
PWM1DL_MCU
R2
1.5k
C6
0.1uF
C1
0.1uF
C15
100nF
RXD
TXD
R78
2.2K
1
3
9
10
12
11
R80
2.2K TMS
TDI
VTREF
TDO
RTCK
TCK
EMU0
3.3VDCISO
3.3VDCISO
PWM2DL
VBUS
PWM2DH
C1+
C1-
ROUT2
DIN2
ROUT1
DIN1
C10
100nF
1
3
5
7
9
11
13
380VDC
3.3VDCISO
CON14A
J1
R9
3.3k
R6
110k
R5
110k
R3
110k
2
6
16
8
1
C11
100nF
C12
100nF
RS232
EMU1
TRSTn
TDIS
4
5
100nF
14 UART1TXD_232
7
13 UART1RXD_232
8
C16
2
4
6
8
10
12
14
MAX3232CPW
U7
C2+
C2-
DOUT1
DOUT2
RIN1
RIN2
V+
VVCC
GND
16
15
5VDC ISO
R79
2.2K
UART1TXD_232
UART1RXD_232
3.3VDCISO
1
2
3
CON3
J2
Appendix A
www.ti.com
Figure 15. Control Section Schematic

VBAT
VBAT
PWM2AL_MCU
PWM2AH_MCU
12VDC ISO
PWM1AL_MCU
PWM1AH_MCU
33pF
C63
0.22uF
C53
FB
COMP
DIS/EN
SS
RC
U14
4.7E
R35
4.7E
R34
D8A
15V
4.7E
R26
4.7E
R25
D2A
15V
1k
R53
TPS40210DGQ
R39
C52
R46
2k
C32
4.7uF
470pF
4.7uF
4.7uF
C27
4.7uF
402k
C41
IRS21867S
LO
VS
HO
VB
D8
15V
MURS160
COM
LIN
HIN
VCC
U13
D9
C31
100nF
IRS21867S
LO
VS
HO
VB
MURS160
COM
LIN
HIN
VCC
U11
C40
2
1
2
1
D5
PMPD
11
D2
15V
GND
ISNS
GDRD
VBP
VDD
0.1uF
R38
0E
C47
10
PWM2AL
A2D
PWM2AH
PWM1AL
A1D
PWM1AH
PWM1AH
1uF
C55
3300pF
C68
PWM1AL
M3
100pF
C56
FCPF400N60
A1D
FCPF400N60
M1
2k
R41
R40
20E
20k 1/2W
R37
R44
Si448EY
Q1
BAS16
D14
0.1uF
100V
C46
FCPF400N60
M4
A2D
M2
FCPF400N60
U16
TCMT1109
3.01k
R47
0.18 1W
4
3
C24
100nF
1
2
R51
3.01k
R42
10E
C54
1000pF
PWM2AL
PWM2AH
U17
TL431AIDBZ
0E
R54
EE25137
9
10
7
8
2
3
4
1
T3
12
11
10
R48
49.9E
U12
NC3
NC4
NC2
NC1
GND
VZCR
FILTER
VIOUT
FAULT
VCC
VOC
R55
5.11k
R50
19.6k
10uF
C48
24
13
14
15
16
17
18
19
20
21
22
23
C42
10uF
50V
MBRD1045
D12
4
ACS709
IP6-
IP5-
IP4-
IP3-
IP2-
IP1-
IP6+
IP5+
IP4+
IP+FAULT_EN
IP2+
IP1+
D13
MBRD1045
470pF
C67
100k
R21
L3
AC TRANS
4700pF/2kV
C39
VN
R15
100k
R16
VN
C30
5uF
VP
10uF
C49
C43
10uF
50V
FAULT_EN
100k
R22
100k
L5
R17
1uH
C59
1uF
R33
1uH
330k
2
C60
100nF
10uF
C51
VN-
VP+
C64
200pF
C69
220nF
C62
39nF
C61
1 100nF
C34
0.1uF
5VDC ISO
-12VDC ISOF
R36
10uF
C50
L4
C33
10nF
C37
10nF
R24
330E
R18
330E
12VDC ISO
C38
1nF
IADC
1k
R29
R28
4.7k
100k
R23
100k
R49
221k
R56
10.2k
R45 EN
1.43k
R43
10k
C44
10uF
SS
RT
RAMP
VCC
RES
EN
U15
C70
1uF
16
10
VP+
VN-
FB
OUT
CSG
CS
SW
HG
BOOT
11
12
13
14
82pF
R58
17.4k
C72
C71
-12VDC ISOF
C28
0.1uF
INA143/SO
V- Sense
15
V+
NC
+IN OUT
-IN
Ref
U9
2nF
LM5088
C45
10uF
35V
12VDC ISO
-12VDC ISO
1
VIN
VP
EP
380VDC
1
2
AGND
6
COMP
7

17

J3
CON3
3
2
1
D15
C57
100nF
-12VDC ISOC
-12VDC ISO
1k
R27
C25
0.1uF
12VDC ISO
4
R59
1.65k
R57
14.7k
M5
U10B
L6
R52
24mOhm
MBRB2060CT
TL082
CSD185Q351A
1k
R31
-12VDC ISO
TL082
U10A
12VDC ISO
-12VDC ISO
10uH 25mOhm
12VDC ISO
8
4
8
4
12VDC ISO
C65
22uF
D1N4148
D7
C29
0.1uF
D1N4148
D6
C26
0.1uF
C66
1uF
-12VDC ISOC
C58
1uF
VADC
www.ti.com
Appendix A
Figure 16. DC-AC Converter Schematic
17
Revision History
www.ti.com
Revision History
Changes from A Revision (April 2014) to B Revision .................................................................................................... Page
Udpates
Updates
Updates
Updates
were made
were made
were made
were made
to
to
to
to
Figure 3. ........................................................................................................
Equation 1. .....................................................................................................
Equation 2. .....................................................................................................
Equation 3. .....................................................................................................
3
4
5
5
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
18
Revision History

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Application Report

SPRABW0B May 2014 Revised June 2015

Voltage Fed Full Bridge DC-DC and DC-AC Converter for

Transformerless Inverter Technology ..................................................................................... 2

High-Frequency Inverter Technology

High-Frequency Inverter Block Diagram

SPRABW0B May 2014 Revised June 2015

Basic Inverter Concept

DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge) .................................................... 15

Control Section Schematic

DC-AC Converter Schematic

Basic Inverter Concept

Figure 2. Transformerless Inverter Technology

C2000, Piccolo are trademarks of Texas Instruments.

SPRABW0B May 2014 Revised June 2015

High-Frequency Inverter Block Diagram

Figure 3. High-Frequency Inverter Technology

High-Frequency Inverter Block Diagram

Figure 4. High-Frequency Inverter Block Diagram

SPRABW0B May 2014 Revised June 2015

DC-DC Isolation Stage - High-Frequency Inverter

DC-DC Isolation Stage - High-Frequency Inverter

Figure 5. Push-Pull Toplogy

SPRABW0B May 2014 Revised June 2015

DC-DC Isolation Stage - High-Frequency Inverter

Half Bridge Converter

Figure 6. Half Bridge Converter

Full Bridge Converter

SPRABW0B May 2014 Revised June 2015

DC-DC Isolation Stage - High-Frequency Inverter

Figure 7. Full Bridge Converter

SPRABW0B May 2014 Revised June 2015

DC-DC Converter Section (Voltage Fed Full Bridge)

SPRABW0B May 2014 Revised June 2015

DC-DC Converter Section (Voltage Fed Full Bridge)

Figure 8. Functional Block Diagram of UCC27211

Voltage Fed Full Bridge Converter Transformer Calculation

Total Output Power Po = (Vo + Vrl + Vd) Io

The Area Product for this configuration is given as:

= Efficiency of the Full Bridge converter

SPRABW0B May 2014 Revised June 2015

DC-DC Converter Section (Voltage Fed Full Bridge)

Primary Number of Turns

2.D max .Vin min

RMS Values of Currents

SPRABW0B May 2014 Revised June 2015

DC-AC Converter Section

SPRABW0B May 2014 Revised June 2015

DC-AC Converter Section

Figure 10. Functional Block Diagram

SPRABW0B May 2014 Revised June 2015

Set the clock to 60 MHz

Initialize PWM1 for DC-DC Conversion

Start the PWM switching

Generate the Sine

Enter Infinite loop and

Figure 11. Firmware Flowchart

SPRABW0B May 2014 Revised June 2015

Figure 12. Output Voltage at No Load