Atmel AVR

AVR instruction set provided ecient compilation of

high-level languages.[4] Atmel says that the name AVR is
not an acronym and does not stand for anything in particular. The creators of the AVR give no denitive answer
as to what the term AVR stands for.[3] However, it is
commonly accepted that AVR stands for Alf (Egil Bogen) and Vegard (Wollan)'s RISC processor.[5] Note that
the use of AVR in this article generally refers to the
8-bit RISC line of Atmel AVR Microcontrollers.

AVR logo

Among the rst of the AVR line was the AT90S8515,

which in a 40-pin DIP package has the same pinout as an
8051 microcontroller, including the external multiplexed
address and data bus. The polarity of the RESET line was
opposite (8051s having an active-high RESET, while the
AVR has an active-low RESET), but other than that the
pinout was identical.
The AVR 8-bit microcontroller architecture was introduced in 1997. By 2003, Atmel had shipped 500 million
AVR ash microcontrollers.[6]

2 Device overview
Atmel ATmega8 in 28-pin narrow DIP

The AVR is a modied Harvard architecture machine,

where program and data are stored in separate physical
memory systems that appear in dierent address spaces,
but having the ability to read data items from program
memory using special instructions.

The AVR is a modied Harvard architecture 8-bit RISC

single-chip microcontroller, which was developed by
Atmel in 1996. The AVR was one of the rst microcontroller families to use on-chip ash memory for program
storage, as opposed to one-time programmable ROM,
EPROM, or EEPROM used by other microcontrollers at
the time.

2.1 Basic families

AVRs are generally classied into following:

Brief history

tinyAVR the ATtiny series

Main article: Atmel AVR ATtiny comparison chart

The AVR architecture was conceived by two students at

the Norwegian Institute of Technology (NTH),[1] AlfEgil Bogen[2] and Vegard Wollan.[3]

0.516 KB program memory

632-pin package

The original AVR MCU was developed at a local ASIC

house in Trondheim, Norway, called Nordic VLSI at the
time, now Nordic Semiconductor, where Bogen and Wollan were working as students. It was known as a RISC
(Micro RISC) and was available as silicon IP/building
block from Nordic VLSI. When the technology was sold
to Atmel from Nordic VLSI, the internal architecture was
further developed by Bogen and Wollan at Atmel Norway, a subsidiary of Atmel. The designers worked closely
with compiler writers at IAR Systems to ensure that the

Limited peripheral set

megaAVR the ATmega series
4256 KB program memory
28100-pin package
Extended instruction set (multiply instructions
and instructions for handling larger program
memories)
1

2
Extensive peripheral set
XMEGA the ATxmega series
16384 KB program memory
4464100-pin package (A4, A3, A1)
32-pin package: XMEGA-E (XMEGA8E5)
Extended performance features, such as
DMA, Event System, and cryptography
support
Extensive peripheral set with ADCs
Application-specic AVR

DEVICE OVERVIEW

The size of the program memory is usually indicated in

the naming of the device itself (e.g., the ATmega64x line
has 64 KB of ash, while the ATmega32x line has 32
KB).
There is no provision for o-chip program memory; all
code executed by the AVR core must reside in the onchip ash. However, this limitation does not apply to the
AT94 FPSLIC AVR/FPGA chips.
2.2.2 Internal data memory
The data address space consists of the register le, I/O
registers, and SRAM.

megaAVRs with special features not found on

the other members of the AVR family, such
2.2.3 Internal registers
as LCD controller, USB controller, advanced
PWM, CAN, etc.
FPSLIC (AVR with FPGA)
FPGA 5k to 40k gates
SRAM for the AVR program code, unlike all
other AVRs
AVR core can run at up to 50 MHz[7]
32-bit AVRs
Main article: AVR32

In 2006, Atmel released microcontrollers

based on the 32-bit AVR32 architecture. They
include SIMD and DSP instructions, along
with other audio- and video-processing features. This 32-bit family of devices is intended
to compete with the ARM-based processors.
The instruction set is similar to other RISC
cores, but it is not compatible with the original AVR or any of the various ARM cores.

2.2

Device architecture

Flash, EEPROM, and SRAM are all integrated onto a

single chip, removing the need for external memory in
most applications. Some devices have a parallel external bus option to allow adding additional data memory
or memory-mapped devices. Almost all devices (except
the smallest TinyAVR chips) have serial interfaces, which
can be used to connect larger serial EEPROMs or ash
chips.

Atmel ATxmega128A1 in 100-pin TQFP package

The AVRs have 32 single-byte registers and are classied

as 8-bit RISC devices.
In the tinyAVR and megaAVR variants of the AVR architecture, the working registers are mapped in as the rst
32 memory addresses (000016 001F16 ), followed by 64
I/O registers (002016 005F16 ). In devices with many peripherals, these registers are followed by 160 extended
I/O registers, only accessible as memory-mapped I/O
(006016 00FF16 ).
Actual SRAM starts after these register sections, at address 006016 or, in devices with extended I/O, at
010016 .
Even though there are separate addressing schemes and
optimized opcodes for accessing the register le and the
rst 64 I/O registers, all can still be addressed and manipulated as if they were in SRAM.

The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15
are omitted) which are not addressable as memory loca2.2.1 Program memory
tions. I/O memory begins at address 000016 , followed
Program instructions are stored in non-volatile ash by SRAM. In addition, these devices have slight deviamemory. Although the MCUs are 8-bit, each instruction tions from the standard AVR instruction set. Most notakes one or two 16-bit words.
tably, the direct load/store instructions (LDS/STS) have

2.3

Program execution

been reduced from 2 words (32 bits) to 1 word (16 bits),

limiting the total direct addressable memory (the sum of
both I/O and SRAM) to 128 bytes. Conversely, the indirect load instructions (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash
and conguration bits; therefore, the LPM instruction is
unnecessary and omitted.

3
same way an external peripheral device is, using special pointer registers and read/write instructions, which
makes EEPROM access much slower than other internal
RAM.

However, some devices in the SecureAVR (AT90SC)

family[9] use a special EEPROM mapping to the data or
program memory, depending on the conguration. The
In the XMEGA variant, the working register le is not XMEGA family also allows the EEPROM to be mapped
mapped into the data address space; as such, it is not pos- into the data address space.
sible to treat any of the XMEGAs working registers as Since the number of writes to EEPROM is limited Atthough they were SRAM. Instead, the I/O registers are mel species 100,000 write cycles in their datasheets
mapped into the data address space starting at the very a well designed EEPROM write routine should compare
beginning of the address space. Additionally, the amount the contents of an EEPROM address with desired conof data address space dedicated to I/O registers has grown tents and only perform an actual write if the contents need
substantially to 4096 bytes (000016 0FFF16 ). As with to be changed.
previous generations, however, the fast I/O manipulation
instructions can only reach the rst 64 I/O register loca- Note that erase and write can be performed separately in
tions (the rst 32 locations for bitwise instructions). Fol- many cases, byte-by-byte, which may also help prolong
lowing the I/O registers, the XMEGA series sets aside a life when bits only need to be set to all 1s (erase) or se4096 byte range of the data address space, which can be lectively cleared to 0s (write).
used optionally for mapping the internal EEPROM to the
data address space (100016 1FFF16 ). The actual SRAM
2.3 Program execution
is located after these ranges, starting at 200016 .
Atmels AVRs have a two-stage, single-level pipeline design. This means the next machine instruction is fetched
as the current one is executing. Most instructions take
Each GPIO port on a tiny or mega AVR drives up to eight just one or two clock cycles, making AVRs relatively fast
pins and is controlled by three 8-bit registers: DDRx, among eight-bit microcontrollers.
PORTx and PINx, where x is the port identier.
The AVR processors were designed with the ecient exe2.2.4

GPIO ports

cution of compiled C code in mind and have several built DDRx: Data Direction Register, congures the pins in pointers for the task.
as either inputs or outputs.
PORTx: Output port register. Sets the output value 2.4 Instruction set
on pins congured as outputs. Enables or disables
Main article: Atmel AVR instruction set
the pull-up resistor on pins congured as inputs.
PINx: Input register, used to read an input signal.
On some devices (but not all, check the datasheet),
this register can be used for pin toggling: writing a
logic one to a PINx bit toggles the corresponding bit
in PORTx, irrespective of the setting of the DDRx
bit.[8]
xmegaAVR have additional registers for push/pull,
totem-pole and pullup congurations.
2.2.5

EEPROM

Almost all AVR microcontrollers have internal

EEPROM for semi-permanent data storage.
Like
ash memory, EEPROM can maintain its contents when
electrical power is removed.
In most variants of the AVR architecture, this internal
EEPROM memory is not mapped into the MCUs addressable memory space. It can only be accessed the

The AVR instruction set is more orthogonal than those

of most eight-bit microcontrollers, in particular the 8051
clones and PIC microcontrollers with which AVR competes today. However, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are dierent from each other.
Register locations R0 to R15 have dierent addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have dierent addressing capabilities than I/O ports 32 to 63.
CLR aects ags, while SER does not, even though
they are complementary instructions. CLR set all
bits to zero, and SER sets them to one. (Note that
CLR is pseudo-op for EOR R, R; and SER is short
for LDI R,$FF. Math operations such as EOR modify ags, while moves/loads/stores/branches such as
LDI do not.)

DEVICE OVERVIEW

Accessing read-only data stored in the program

memory (ash) requires special LPM instructions;
the ash bus is otherwise reserved for instruction
memory.

Multifunction, bi-directional general-purpose I/O

ports with congurable, built-in pull-up resistors

Additionally, some chip-specic dierences aect code

generation. Code pointers (including return addresses on
the stack) are two bytes long on chips with up to 128 KB
of ash memory, but three bytes long on larger chips;
not all chips have hardware multipliers; chips with over 8
KB of ash have branch and call instructions with longer
ranges; and so forth.

Internal, self-programmable instruction ash memory up to 256 KB (384 KB on XMega)

The mostly regular instruction set makes programming it

using C (or even Ada) compilers fairly straightforward.
GCC has included AVR support for quite some time, and
that support is widely used. In fact, Atmel solicited input
from major developers of compilers for small microcontrollers, to determine the instruction set features that were
most useful in a compiler for high-level languages.

2.5

MCU speed

The AVR line can normally support clock speeds from

0 to 20 MHz, with some devices reaching 32 MHz.
Lower-powered operation usually requires a reduced
clock speed. All recent (Tiny, Mega, and Xmega, but
not 90S) AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Some
AVRs also have a system clock prescaler that can divide
down the system clock by up to 1024. This prescaler can
be recongured by software during run-time, allowing the
clock speed to be optimized.
Since all operations (excluding multiplication and 16-bit
add/subtract) on registers R0R31 are single-cycle, the
AVR can achieve up to 1 MIPS per MHz, i.e. an 8 MHz
processor can achieve up to 8 MIPS. Loads and stores
to/from memory take two cycles, branching takes two cycles. Branches in the latest 3-byte PC parts such as ATmega2560 are one cycle slower than on previous devices.

2.6

Development

AVRs have a large following due to the free and inexpensive development tools available, including reasonably
priced development boards and free development software. The AVRs are sold under various names that share
the same basic core, but with dierent peripheral and
memory combinations. Compatibility between chips in
each family is fairly good, although I/O controller features
may vary.
See external links for sites relating to AVR development.

2.7

Features

Current AVRs oer a wide range of features:

Multiple internal oscillators, including RC oscillator

without external parts

In-system programmable using serial/parallel

low-voltage proprietary interfaces or JTAG
Optional boot code section with independent
lock bits for protection
On-chip debugging (OCD) support through JTAG
or debugWIRE on most devices
The JTAG signals (TMS, TDI, TDO, and
TCK) are multiplexed on GPIOs. These pins
can be congured to function as JTAG or
GPIO depending on the setting of a fuse bit,
which can be programmed via ISP or HVSP.
By default, AVRs with JTAG come with the
JTAG interface enabled.
debugWIRE uses the /RESET pin as a bidirectional communication channel to access
on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires
one pin.
Internal data EEPROM up to 4 KB
Internal SRAM up to 16 KB (32 KB on XMega)
External 64 KB little endian data space on certain
models, including the Mega8515 and Mega162.
The external data space is overlaid with the internal data space, such that the full 64 KB address space does not appear on the external bus
and accesses to e.g. address 010016 will access
internal RAM, not the external bus.
In certain members of the XMega series, the
external data space has been enhanced to support both SRAM and SDRAM. As well, the
data addressing modes have been expanded to
allow up to 16 MB of data memory to be directly addressed.
AVRs generally do not support executing code
from external memory. Some ASSPs using the
AVR core do support external program memory.
8-bit and 16-bit timers
PWM output (some devices have an enhanced
PWM peripheral which includes a dead-time
generator)
Input capture that record a time stamp triggered by a signal edge

3.1

ISP

Analog comparator

MISO

1
1

VCC

MOSI

VCC

10 or 12-bit A/D converters, with multiplex of up to

16 channels

SCK

MOSI

NC

GND

12-bit D/A converters

RST

GND

RST

GND

SCK

GND

MISO

10

GND

A variety of serial interfaces, including

IC compatible Two-Wire Interface (TWI)

ISP
HEADERS
TOP
VIEW

Synchronous/asynchronous serial peripherals

(UART/USART) (used with RS-232, RS-485,
6- and 10-pin ISP header diagrams
and more)
Serial Peripheral Interface Bus (SPI)

3.1 ISP

Universal Serial Interface (USI): a multipurpose hardware communication module that

can be used to implement an SPI,[10] I2 C[11][12] The in-system programming (ISP) programming method
is functionally performed through SPI, plus some twidor UART[13] interface.
dling of the Reset line. As long as the SPI pins of the
AVR are not connected to anything disruptive, the AVR
Brownout detection
chip can stay soldered on a PCB while reprogramming.
Watchdog timer (WDT)
All that is needed is a 6-pin connector and programming
adapter. This is the most common way to develop with
Multiple power-saving sleep modes
an AVR.
Lighting and motor control (PWM-specic) con- The Atmel AVRISP mkII device connects to a computers
troller models
USB port and performs in-system programming using Atmels software.
CAN controller support
AVRDUDE (AVR Downloader/UploaDEr) runs on
USB controller support
Linux, FreeBSD, Windows, and Mac OS X, and supports a variety of in-system programming hardware, in Proper full-speed (12 Mbit/s) hardware & Hub cluding Atmel AVRISP mkII, Atmel JTAG ICE, older
controller with embedded AVR.
Atmel serial-port based programmers, and various third Also freely available low-speed (1.5 Mbit/s) party and do-it-yourself programmers.[15]
(HID) bitbanging software emulations
Ethernet controller support

3.2 PDI

LCD controller support

The Program and Debug Interface (PDI) is an Atmel proLow-voltage devices operating down to 1.8 V (to 0.7 prietary interface for external programming and on-chip
debugging of XMEGA devices. The PDI supports highV for parts with built-in DCDC upconverter)
speed programming of all non-volatile memory (NVM)
picoPower devices
spaces; ash, EEPROM, fuses, lock-bits and the User
Signature Row. This is done by accessing the XMEGA
DMA controllers and event system peripheral NVM controller through the PDI interface, and executing
communication.
NVM controller commands. The PDI is a 2-pin interface
using the Reset pin for clock input (PDI_CLK) and a dedFast cryptography support for AES and DES
icated data pin (PDI_DATA) for input and output.[16]

Programming interfaces

There are many means to load program code into an AVR

chip. The methods to program AVR chips varies from
AVR family to family. Most of the methods described below use the RESET line to enter programming mode. In
order to avoid the chip accidentally entering such mode,
it is advised to connect a pull-up resistor between the RESET pin and the positive power supply.[14]

3.3 High-voltage serial

High-voltage serial programming (HVSP)[17] is mostly
the backup mode on smaller AVRs. An 8-pin AVR package does not leave many unique signal combinations to
place the AVR into a programming mode. A 12-volt
signal, however, is something the AVR should only see
during programming and never during normal operation.
The high voltage mode can also be used in some devices

5 DEVELOPMENT TOOLS AND EVALUATION KITS

where the reset pin has been disabled by fuses.

4.2 JTAG

The Joint Test Action Group (JTAG) feature provides access to on-chip debugging functionality while the chip
3.4 High-voltage parallel
is running in the target system.[23] JTAG allows accessing internal memory and registers, setting breakpoints on
High-voltage parallel programming (HVPP) is consid- code, and single-stepping execution to observe system beered the nal resort and may be the only way to correct haviour.
bad fuse settings on an AVR chip.
Atmel provides a series of JTAG adapters for the AVR:

3.5

Bootloader

Most AVR models can reserve a bootloader region, 256

B to 4 KB, where re-programming code can reside.
At reset, the bootloader runs rst and does some userprogrammed determination whether to re-program or to
jump to the main application. The code can re-program
through any interface available, or it could read an encrypted binary through an Ethernet adapter like PXE. Atmel has application notes and code pertaining to many bus
interfaces.[18][19][20][21]

3.6

ROM

The AT90SC series of AVRs are available with a factory

mask-ROM rather than ash for program memory.[22]
Because of the large up-front cost and minimum order
quantity, a mask-ROM is only cost-eective for highproduction runs.

3.7

aWire

aWire is a new one-wire debug interface available on the

new UC3L AVR32 devices.

Debugging interfaces

1. The Atmel-ICE[24] is the latest adapter. It supports

JTAG, debugWire, aWire, SPI, TPI, and PDI interfaces.
2. The JTAGICE 3[25] is a midrange debugger in the
JTAGICE family (JTAGICE mkIII). It supports
JTAG, aWire, SPI, and PDI interfaces.
3. The JTAGICE mkII[26] replaces the JTAGICE and
is similarly priced. The JTAGICE mkII interfaces
to the PC via USB, and supports both JTAG and
the newer debugWIRE interface. Numerous thirdparty clones of the Atmel JTAGICE mkII device
started shipping after Atmel released the communication protocol.[27]
4. The AVR Dragon[28] is a low-cost (approximately
$50) substitute for the JTAGICE mkII for certain
target parts. The AVR Dragon provides in-system
serial programming, high-voltage serial programming and parallel programming, as well as JTAG or
debugWIRE emulation for parts with 32 KB of program memory or less. ATMEL changed the debugging feature of AVR Dragon with the latest rmware
of AVR Studio 4 - AVR Studio 5 and now it supports
devices over 32 KB of program memory.
5. The JTAGICE adapter interfaces to the PC via
a standard serial port. Although the JTAGICE
adapter has been declared "end-of-life" by Atmel,
it is still supported in AVR Studio and other tools.

JTAG can also be used to perform a boundary scan

The AVR oers several options for debugging, mostly in- test,[29] which tests the electrical connections between
volving on-chip debugging while the chip is in the target AVRs and other boundary scan capable chips in a syssystem.
tem. Boundary scan is well-suited for a production line,
while the hobbyist is probably better o testing with a
multimeter or oscilloscope.

4.1

debugWIRE

debugWIRETM is Atmels solution for providing on-chip 5 Development tools and evaluadebug capabilities via a single microcontroller pin. It is
tion kits
particularly useful for lower pin count parts which cannot provide the four spare pins needed for JTAG. The
JTAGICE mkII, mkIII and the AVR Dragon support de- Ocial Atmel AVR development tools and evaluation kits
bugWIRE. debugWIRE was developed after the original contain a number of starter kits and debugging tools with
support for most AVR devices:
JTAGICE release, and now clones support it.

5.3

STK200 starter kit

7
STK503 Adds support for microcontrollers in
100-pin TQFP packages.
STK504 Adds support for LCD AVRs in 100-pin
TQFP packages.
STK505 Adds support for 14 and 20-pin AVRs.
STK520 Adds support for 14 and 20, and 32-pin
microcontrollers from the AT90PWM and ATmega
family.

Atmel STK500 development board

STK524 Adds support for the ATmega32M1/C1

32-pin CAN/LIN/Motor Control family.

5.1

STK525 Adds support for the AT90USB microcontrollers in 64-pin TQFP packages.

STK600 starter kit

The STK600 starter kit and development system is an update to the STK500.[30] The STK600 uses a base board,
a signal routing board, and a target board.

STK526 Adds support for the AT90USB microcontrollers in 32-pin TQFP packages.

The base board is similar to the STK500, in that it provides a power supply, clock, in-system programming, an 5.3 STK200 starter kit
RS-232 port and a CAN (Controller Area Network, an
automotive standard) port via DE9 connectors, and stake The STK200 starter kit and development system has a
DIP socket that can host an AVR chip in a 40, 20, or
pins for all of the GPIO signals from the target device.
8-pin package. The board has a 4 MHz clock source, 8
The target boards have ZIF sockets for DIP, SOIC, QFN, light-emitting diode(LED)s, 8 input buttons, an RS-232
or QFP packages, depending on the board.
port, a socket for a 32k SRAM and numerous general I/O.
The signal routing board sits between the base board and The chip can be programmed with a dongle connected to
the target board, and routes the signals to the proper pin the parallel port.
on the device board. There are many dierent signal routing boards that could be used with a single target board,
5.4 AVRISP and AVRISP mkII
depending on what device is in the ZIF socket.
The STK600 allows in-system programming from the PC
via USB, leaving the RS-232 port available for the target
microcontroller. A 4 pin header on the STK600 labeled
'RS-232 spare' can connect any TTL level USART port
on the chip to an onboard MAX232 chip to translate the
signals to RS-232 levels. The RS-232 signals are connected to the RX, TX, CTS, and RTS pins on the DB-9
connector.

5.2

STK500 starter kit

The STK500 starter kit and development system features

ISP and high voltage programming (HVP) for all AVR
devices, either directly or through extension boards. The
board is tted with DIP sockets for all AVRs available in
DIP packages.
STK500 Expansion Modules: Several expansion modules
AVRISP mkII
are available for the STK500 board:
STK501 Adds support for microcontrollers in 64pin TQFP packages.

The AVRISP and AVRISP mkII are inexpensive tools allowing all AVRs to be programmed via ICSP.

The AVRISP connects to a PC via a serial port and draws

STK502 Adds support for LCD AVRs in 64-pin power from the target system. The AVRISP allows using
TQFP packages.
either of the standard ICSP pinouts, either the 10-pin

5 DEVELOPMENT TOOLS AND EVALUATION KITS

or 6-pin connector. The AVRISP has been discontinued, bugWIRE interfaces. The debugWire interface enables
replaced by the AVRISP mkII.
debugging using only one pin (the Reset pin), allowing
The AVRISP mkII connects to a PC via USB and draws debugging of applications running on low pin-count mipower from USB. LEDs visible through the translucent crocontrollers.
case indicate the state of target power.

The JTAGICE mkII connects using USB, but there is an

alternate connection via a serial port, which requires using a separate power supply. In addition to JTAG, the
mkII supports ISP programming (using 6-pin or 10-pin
adapters). Both the USB and serial links use a variant of
the STK500 protocol.

As the AVRISP mkII lacks driver/buer ICs,[31] it can

have trouble programming target boards with multiple
loads on its SPI lines. In such occurrences, a programmer
capable of sourcing greater current is required. Alternatively, the AVRISP mkII can still be used if low-value
(~150 ohm) load-limiting resistors can be placed on the
SPI lines before each peripheral device.
5.8

5.5

AVR Dragon

JTAGICE3

The JTAGICE3 updates the mkII with more advanced

debugging capabilities and faster programming. It connects via USB and supports the JTAG, aWire, SPI, and
PDI interfaces.[35] The kit includes several adapters for
use with most interface pinouts.

5.9 AVR ONE!

The AVR ONE! is a professional development tool for all
Atmel 8-bit and 32-bit AVR devices with On-Chip Debug capability. It supports SPI, JTAG, PDI, and aWire
programming modes and debugging using debugWIRE,
JTAG, PDI, and aWire interfaces.[36]
AVR Dragon with ISP programming cable and attached, blue ZIF
Socket

5.10 Buttery demonstration board

The Atmel Dragon is an inexpensive tool which connects

to a PC via USB. The Dragon can program all AVRs via
JTAG, HVP, PDI,[32] or ICSP. The Dragon also allows
debugging of all AVRs via JTAG, PDI, or debugWire; a
previous limitation to devices with 32 KB or less program
memory has been removed in AVR Studio 4.18.[33] The
Dragon has a small prototype area which can accommodate an 8, 28, or 40-pin AVR, including connections to
power and programming pins. There is no area for any
additional circuitry, although this can be provided by a
third-party product called the Dragon Rider.[34]

5.6

JTAGICE mkI

The JTAG In Circuit Emulator (JTAGICE) debugging

tool supports on-chip debugging (OCD) of AVRs with a
JTAG interface. The original JTAGICE mkI uses an RS232 interface to a PC and can only program AVRs with a
JTAG interface. The JTAGICE mkI is no longer in production, however it has been replaced by the JTAGICE
mkII.

Atmel ATmega169 in 64-pad MLF package on the back of an

Atmel AVR Buttery board

Main article: AVR Buttery

The very popular AVR Buttery demonstration board is

a self-contained, battery-powered computer running the
Atmel AVR ATmega169V microcontroller. It was built
to show-o the AVR family, especially a then new built5.7 JTAGICE mkII
in LCD interface. The board includes the LCD screen,
The JTAGICE mkII debugging tool supports on-chip de- joystick, speaker, serial port, real time clock (RTC), ash
bugging (OCD) of AVRs with SPI, JTAG, PDI, and de- memory chip, and both temperature and voltage sensors.

5.13

Third-party programmers

Earlier versions of the AVR Buttery also contained a

CdS photoresistor; it is not present on Buttery boards
produced after June 2006 to allow RoHS compliance.[37]
The small board has a shirt pin on its back so it can be
worn as a name badge.
The AVR Buttery comes preloaded with software to
demonstrate the capabilities of the microcontroller. Factory rmware can scroll your name, display the sensor
readings, and show the time. The AVR Buttery also has
a piezoelectric transducer that can be used to reproduce
sounds and music.

9
Buttery cards, plus a wireless USBKey; and costing
about that much (under $US100). All these boards support JTAG-based development.
The kit includes two AVR Raven boards, each with a 2.4
GHz transceiver supporting IEEE 802.15.4 (and a freely
licensed ZigBee stack). The radios are driven with ATmega1284p processors, which are supported by a custom
segmented LCD display driven by an ATmega3290p processor. Raven peripherals resemble the Buttery: piezo
speaker, DataFlash (bigger), external EEPROM, sensors,
32 kHz crystal for RTC, and so on. These are intended for
use in developing remote sensor nodes, to control relays,
or whatever is needed.

The AVR Buttery demonstrates LCD driving by running

a 14-segment, six alpha-numeric character display. However, the LCD interface consumes many of the I/O pins. The USB stick uses an AT90USB1287 for connections to
The Butterys ATmega169 CPU is capable of speeds up a USB host and to the 2.4 GHz wireless links. These are
to 8 MHz, but it is factory set by software to 2 MHz to pre- intended to monitor and control the remote nodes, relying
serve the button battery life. A pre-installed bootloader on host power rather than local batteries.
program allows the board to be re-programmed via a standard RS-232 serial plug with new programs that users can
5.13
write with the free Atmel IDE tools.

5.11 AT90USBKey
This small board, about half the size of a business card,
is priced at slightly more than an AVR Buttery. It includes an AT90USB1287 with USB On-The-Go (OTG)
support, 16 MB of DataFlash, LEDs, a small joystick,
and a temperature sensor. The board includes software,
which lets it act as a USB mass storage device (its documentation is shipped on the DataFlash), a USB joystick,
and more. To support the USB host capability, it must
be operated from a battery, but when running as a USB
peripheral, it only needs the power provided over USB.

Third-party programmers

A wide variety of third-party programming and debugging tools are available for the AVR. These devices use
various interfaces, including RS-232, PC parallel port,
and USB. AVR Freaks has a comprehensive list.

6 Atmel AVR usage

Only the JTAG port uses conventional 2.54 mm pinout.

All the other AVR I/O ports require more compact 1.27
mm headers.
The AVR Dragon can both program and debug since the
32 KB limitation was removed in AVR Studio 4.18, and
the JTAGICE mkII is capable of both programming and
debugging the processor. The processor can also be programmed through USB from a Windows or Linux host,
using the USB Device Firmware Update protocols. Atmel ships proprietary (source code included but distri- Atmel AVR ATmega328 28-pin DIP on an Arduino Duemilanove
bution restricted) example programs and a USB protocol board
stack with the device.
LUFA[38] is a third-party free software (MIT license) AVRs have been used in various automotive applications
USB protocol stack for the USBKey and other 8-bit USB such as security, safety, powertrain and entertainment
systems. Atmel has recently launched a new publicaAVRs.
tion Atmel Automotive Compilation to help developers
with automotive applications. Some current usages are in
BMW, Daimler-Chrysler and TRW.
5.12 Raven wireless kit
The Arduino physical computing platform is based on
The RAVEN kit supports wireless development using At- an ATmega328 microcontroller (ATmega168 or ATmels IEEE 802.15.4 chipsets, for ZigBee and other wire- mega8 in board versions older than the Diecimila). The
less stacks. It resembles a pair of wireless more-powerful ATmega1280 and ATmega2560, with more pinout and

10

REFERENCES

implementing techniques not found in the original

AVR processor such as deeper pipelining.
avr_core,[47] written in VHDL, is a clone aimed at
being as close as possible to the ATmega103.
Navr,[48] written in Verilog, implements all Classic
Core instructions and is aimed at high performance
and low resource usage. It does not support interrupts.
The opencores project CPU lecture[49] written in
VHDL by Dr. Jrgen Sauermann explains in detail
how to design a complete AVR based System on a
Chip (SoC).

8 See also
Arduino
AVR32
Atmel AVR ATmega8 28-pin DIP on a custom development board

9 References
memory capabilities, have also been employed to develop
the Arduino Mega platform. Arduino boards can be used
with its language and IDE, or with more conventional programming environments (C, assembler, etc.) as just standardized and widely available AVR platforms.
USB-based AVRs have been used in the Microsoft Xbox
hand controllers. The link between the controllers and
Xbox is USB.
Numerous companies produce AVR-based microcontroller boards intended for use by hobbyists, robot
builders, experimenters and small system developers including: Cubloc,[39] gnusb,[40] BasicX,[41] Oak
Micros,[42] ZX Microcontrollers,[43] and myAVR.[44]
There is also a large community of Arduino-compatible
boards supporting similar users.

[1] Since 1996, NTH has become part of the Norwegian University of Science and Technology (NTNU)
[2] alfbogen.com blog
[3] The Story of AVR. youtube.com.
[4] The AVR Microcontroller and C Compiler Co-Design
(PDF). Retrieved 2012-09-19.
[5] UNSW School of Computer Science and Engineering General AVR Info. Cse.unsw.edu.au. Retrieved 201209-19.
[6] Atmel press release. Atmels AVR Microcontroller Ships
500 Million Units.

Schneider Electric produces the M3000 Motor and Motion Control Chip, incorporating an Atmel AVR Core and
an advanced motion controller for use in a variety of motion applications.[45]

[7] Field Programmable System Level Integrated Circuit

[9] Atmel Smart Card ICs

FPGA clones

[8] http://www.atmel.com/Images/
Atmel-2586-AVR-8-bit-Microcontroller-ATtiny25-ATtiny45-ATtiny85_
AVR-8-bit-Microcontroller-ATtiny25Datasheet.pdf
ATtiny45-ATtiny85_Datasheet.pdf

[10] AVR319: Using the USI module for SPI communication (PDF). Atmel. 2004. Retrieved 10 June 2014.

With the growing popularity of FPGAs among the open

source community, people have started developing open [11] Atmel AVR310: Using the USI Module as a I2 C Master
source processors compatible with the AVR instruction
(PDF). Atmel. 2013. Retrieved 10 June 2014.
set. The OpenCores website lists the following major
[12] AVR312: Using the USI module as a I2 C slave (PDF).
AVR clone projects:
Atmel. 2005. Retrieved 10 June 2014.

pAVR,[46] written in VHDL, is aimed at creating the

fastest and maximally featured AVR processor, by

[13] AVR307: Half Duplex UART Using the USI Module

(PDF). Atmel. 2003. Retrieved 10 June 2014.

11

[14] AVR Hardware Design Considerations (PDF) (application note). Atmel Corporation. Jun 2015. p. 5. Retrieved
14 Jun 2015. The reset line has an internal pull-up resistor, but if the environment is noisy it can be insucient
and reset can therefore occur sporadically.
[15] AVRDUDE programmer. Savannah.nongnu.org. Retrieved 2012-09-19.
[16] PDI programming driver (PDF). Retrieved 2012-0919.
[17] HVSP_Description.
2012-09-19.

Support.atmel.no.

Retrieved

[18] DES-encrypted AVR Bootloader (PDF). Retrieved

2012-09-19.
[19] AES-encrypted AVR Bootloader (PDF). Retrieved
2012-09-19.

[40] gnusb: Open Source USB Sensor Box. Retrieved 13

January 2013.
[41] BasicX. NetMedia, Inc. Retrieved 13 January 2013.
[42] Welcome to Oak Micros. Oak Micros. Oak Micros.
Retrieved 13 January 2013.
[43] ZBasic. Retrieved 13 January 2013.
[44] myAVR. Laser & Co. Solutions GmbH. Retrieved 13
January 2013.
[45] M3000 Motion controller on a chip. imshome.com.
Schneider Electric Motion USA.
[46] pAVR :: Overview. OpenCores. Retrieved 2012-0919.
[47] AVR Core :: Overview. OpenCores. Retrieved 201209-19.

[20] XMEGA Bootloader (PDF). Retrieved 2012-09-19.

[21] AVR USB Bootloader (PDF). Retrieved 2012-09-19.

[48] Navr AVR clone (8-bit RISC) :: Overview. OpenCores. Retrieved 2012-09-19.

[22] Atmels Self-Programming Flash Microcontrollers

(PDF). Retrieved 2012-09-19.

[49] CPU lecture. OpenCores. Retrieved 2015-02-16.

[23] Guide to understanding JTAG and security fuses on the

AVR. Retrieved 2012-09-19.

10 Further reading

[24] Atmel-ICE - Atmel Corporation.

trieved 2015-09-11.

Atmel.com.

Re-

[25] JTAGICE 3- Atmel Corporation. Atmel.com. Retrieved 2012-09-19.

[26] AVR JTAGICE mkII. Atmel. Retrieved 13 January
2013.
[27] JTAGICE mkII Communication Protocol (PDF). Retrieved 2012-09-19.
[28] AVR Dragon. Atmel. Retrieved 13 January 2013.
[29] JTAGICE Press Release, 2004.
[30] STK600. Atmel. Retrieved 13 January 2013.

AVR Microcontroller and Embedded Systems: Using

Assembly and C; Muhammad Ali Mazidi, Sarmad
Naimi, Sepehr Naimi; 792 pages; 2010; ISBN 9780138003319.
Embedded C Programming and the Atmel AVR;
Richard H Barnett, Sarah Cox, Larry O'Cull; 560
pages; 2006; ISBN 978-1-4180-3959-2.
C Programming for Microcontrollers Featuring ATMELs AVR Buttery and WinAVR Compiler; Joe
Pardue; 300 pages; 2005; ISBN 978-0-9766822-02.

[32] AVR1005: Getting started with XMEGA, page 7

(PDF). Atmel. Retrieved 7 November 2011.

Atmel AVR Microcontroller Primer: Programming

and Interfacing; Steven F Barrett, Daniel Pack,
Mitchell Thornton; 194 pages; 2007; ISBN 978-159829-541-2.

[33] AVR Studio v4.18 Release Notes. Retrieved 2012-0919.

Arduino: A Quick Start Guide; Maik Schmidt; 276

pages; 2011; ISBN 978-1-934356-66-1.

[31] AVRISP mkII Disassembled

[34] ECROS Technology - Dragon Rider. Ecrostech.com.

2008-03-02. Retrieved 2012-09-19.

11 External links

[35] JTAGICE3 Product Page

[36] AVR ONE! Product Page
[37] AVR Buttery
[38] LUFA (Formerly MyUSB)". Four Walled Cubicle. Retrieved 2012-09-19.
[39] Comle Technology. Comle Technology, Inc. Retrieved 13 January 2013.

Ocial
Atmel AVR
Communities
AVR Freaks community

12
Arduino community
Other
Atmel AVR at DMOZ, numerous AVR links
AVR-Libc
Atmel AVR Serial Port Programmer
Why you need a clock source for the AVR?
AVR Basics - AVR guide for beginners
Simplest AVR programmer Using LPT Port
ATmega8 Breadboard Tutorial
AVR
DIP-Package
Pinout
Diagrams:
ATtiny44/45/84/85, ATmega328P, ATmega644P,
ATmega1284P
AVR
TQFP-Package
Pinout
Diagrams:
ATmega328, ATmega2560, ATmega32U4

11

EXTERNAL LINKS

13

12
12.1

Text and image sources, contributors, and licenses

Text

Atmel AVR Source: https://en.wikipedia.org/wiki/Atmel_AVR?oldid=730257408 Contributors: PierreAbbat, Maury Markowitz,

Mahjongg, Egil, Stan Shebs, Glenn, Alf, Saltine, EthanL, Wernher, RedWolf, Pengo, Alan Liefting, DavidCary, DanielHolth, Chowbok,
Alexf, Julien~enwiki, Abdull, Trevor MacInnis, Chappell, Moxfyre, Imroy, Rhobite, Stevenyu~enwiki, Rnsanchez, Bender235, Kms, Phil
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Osiixy, Tomitech, Comp.arch, Kevinf28, Tolmeros, Akhilsn, Moshaydi, 0xTJ, Dharmendra Kumar Dangi, GSS-1987, Akashpc2050,
Tcarisland and Anonymous: 310

12.2

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