1.

Explain the differences between the following: a) RISC and CISC processors b) Harvard and Von-Neumann architectures Ans: RISC:[Reduced Instruction Set Computer] Computer] CISC:[Complex Instruction Set

1. Number of instructions is less. 2. Instructions take only one instruction cycle to instruction Execute. execute. 3. Fixed format instructions. 4. In RISC only few addressing modes are there and most instructions have register to register addressing mode. 5.Due to orthogonality or symmetry of the procon status -essor (ability to write to all registers as if they were same), conditional jumps can be based on a bit in any memory. 6.Eg: PIC 16F877

1. Large number of instructions. 2. Many instructions take multiple cycle to

3. Variable format instructions. 4.Many addressing modes.

5.Conditonal jumps are usually based

register bits.

6.Motorola 68000

Harvard Architecture

Von-Neumann Architecture

1. Separate blocks of Data memory & Program memory. Data Data memory Memory CPU Program Program memory Memory

1. Single memory block for Data & Program memory. Program Program & and Data Data Memory memory

CPU CPU

2. Execution in one cycle. Hence easier timing of loops and delays. 3. Here we can fetch data and program in parallel so that we can save the time. 4. Here instruction & data are always separate. 5.Different code(instruction) and data path width are Possible. Ex: 14-bit instructions, 8-bit data in PIC 16F84. 6. It consists of more complex hardware. 7.MOV ACC,REG Cycle1) a)Execute the previous instruction b)Read MOV Acc, Reg Cycle2) Execute MOV Acc, Reg i.e. current instruction was fetched during the previous instructions execution. This makes faster execution. 8. 8051 as Harvard:8051 has two separate signals a) ~RD (P3.7) It is activated when byte is to be read from external data memory. b) ~PSENIt is for external program memory. 9.Ex:Microchip PIC families, Atmel AVR

2. Execution in multiple cycles.

3.Serial fetch instructions and data because program & And data memories are in same block. 4. Here problem is that data / program can get mixed. 5.Data and Instructions (multiples of) are of same size

6. It consists of Simple chip design. 7. MOV ACC,REG Cycle1) Read instruction Cycle2) Execute MOV Acc, Reg In the first cycle of instruction execution, the instruction is read from the memory space. In the next cycle, the data to be put in the accumulator is read from the memory space. 8.8051 as Von-Neumann: Here the two signals ~RD and ~PSEN are combined with a logical AND operation.
~RD EN ~PSEN

9. PCs (Intel 80X86/Pentium, Motorola 68000), Motorola 68XX C families.

2. Explain the memory organization in 8051 microcontroller.

Ans: The 8051 has three very general types of memory. To effectively program the 8051 it is necessary to have a basic understanding of these memory types.

The memory types are:

On-Chip Memory: refers to any memory (Code, RAM, or other) that physically exists on the microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly. External Code Memory: is code (or program) memory that resides off-chip. This is often in the form of an external EPROM or RAM. It ranges from 0000H to FFFFH (64KB). External Data memory: is RAM memory that resides off-chip. This is often in the form of standard static RAM or flash RAM. It ranges from 0000H to FFFFH (64KB). Program (Code) memory (64KB) Internal ROM (4KB) SFRs (128bytes)

8051 C
Internal RAM (128bytes)

Data memory
(64KB)

Code Memory

Code memory is the memory that holds the actual 8051 program that is to be run. This memory is limited to 64K and comes in many shapes and sizes: Code memory may be found on-chip, either burned into the microcontroller as ROM or EPROM. Code may also be stored completely off-chip in an external ROM or, more commonly, an external EPROM. Flash RAM is also another popular method of storing a program. Various combinations of these memory types may also be used--that is to say, it is possible to have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM. However, code memory is most commonly implemented as off-chip EPROM. This is especially true in low- cost development systems and in systems developed by students. Since code memory is restricted to 64K, 8051 programs are limited to 64K. Some assemblers and compilers offer ways to get around this limit when used with specially wired hardware. However, without such special compilers and hardware, programs are limited to 64K.
The 8051 Program memory

FFFFH

FFFFH

60K Bytes External 64K Bytes External

OR

Data memory:
The 8051Data memory

FFFFH

Internal
FFH

SFRs
DIRECT ADDRESSING ONLY

64K BYTES EXTERNAL

AND

80H 7FH

DIRECT &INDIRECT ADDRESSING

OOH

0000H

External Data memory:

As the name suggests, External Data Memory is any random access memory which is found off-chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For example, to increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle. To increment a 1-byte value stored in External Data Memory requires 4 instructions and 7 instruction cycles. In this case, external memory is 7 times slower! The 8051 can address up to 64K-bytes of data memory external to the chip. The MOVX instruction used access the external data memory.

 What External RAM loses in speed and flexibility it gains in quantity. While Internal RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up to 64K.

On-Chip Memory:
The 8051 includes a certain amount of on-chip memory. On-chip memory is really one of two types: Internal RAM and Special Function Register (SFR) memory. The layout of the 8051's internal memory is presented in the following memory map:
I RAM ADDRE SSSS DISCRIPTION

00 0F 10 1F 20 2F

R0 R0 R0 R0 00 40

R1 R1 R1 R1 08 48

R2 R2 R2 R2 10 50

R3 R3 R3 R3 18 58

R4 R4 R4 R4 20 60

R5 R5 R5 R5 28 68

R6 R6 R6 R6 30 70

R7 R7 R7 R7 38 78

Reg Bank 0 Reg Bank 1 Reg Bank 2 Reg Bank 3 Bit 00-3Fh Bit 40-7Fh

Register Banks Bit addressable area

Scratch Pad Area and Stack space (80-bytes , 30h-7Fh) 7F

General IRAM

In the above table each small blocks represents one byte wide. As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more in a later chapter. For now it is sufficient to know that they "live" and are part of internal RAM. Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very shortly, but for now just keep in mind that bit memory actually resides in internal RAM, from addresses 20h through 2Fh. The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a storage area for the operating stack. This fact severely limits the 8051s stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes--and usually it is less since these 80 bytes has to be shared between the stack and user variables.

SFRs: Each SFR has an address (80h through FFh) and a name. The following chart provides a graphical presentation of the 8051's SFRs, their names, and their address.

As you can see, although the address range of 80h through FFh offers 128 possible addresses, there are only 21 SFRs in a standard 8051. All other addresses in the SFR range (80h through FFh) are considered invalid. Writing to or reading from these registers may produce undefined values or behavior

3. What is an addressing mode? Explain different addressing modes with examples. Ans: The various ways of accessing data such as data could be in a register, or in memory, or be provided as an immediate valve. An "addressing mode" refers to how you are addressing a given memory location . The 8051 provides a total of five distinct addressing modes. They are as follows. 1. 2. 3. 4. 5. Immediate addressing Register addressing Direct addressing Register indirect addressing Index addressing

Immediate Addressing Mode

Immediate addressing is so-named because the value to be stored in memory immediately follows the operation code in memory. That is to say, the instruction itself dictates what value will be

stored in memory. Here the source operand is a constant. The immediate data must be preceded by the pound sign, #. For example, the instruction: MOV A, #20h

; This instruction uses Immediate Addressing because the Accumulator will be loaded with the value that immediately follows; in this case 20 (hexadecimal). MOV MOV R7, #58 ; Load the decimal valve 58 into R7 DPTR, #3605H ; DPTR=3605h

Immediate addressing is very fast since the value to be loaded is included in the instruction. However, since the value to be loaded is fixed at compile-time it is not very flexible. We can also use immediate addressing mode to send a data to 8051 ports. MOV P1, #55H ; P1=55H

We can use the EQU directive to access the immediate data as shown below COUNT EQU 30 MOV R4, #COUNT ; R4=1EH (1EH=30)

Register Addressing Mode

Register addressing mode involves the use of registers to hold the data to be manipulated. It should be noted that the source and destination register must match in size. A, R0 ; Copy the contents of RO into A

Ex: MOV

MOV R2, A ; Save the accumulator in R6 MOV R7, DPL MOV R6, DPH ; Copy the contents of DPTR into R6, R7 We can move the data between the accumulator and Rn (for n=0 to 7) but movement data between Rn register is not allowed. MOV R4, R7 ; It is not allowed

Direct Addressing Mode

It is mainly used to accessing memory. Direct addressing is so-named because the value to be stored in memory is obtained by directly retrieving it from another memory location. Direct addressing is generally fast since, although the value to be loaded isnt included in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM. It is also much more flexible than Immediate Addressing since the value to be loaded is whatever is found at the given address--which may be variable. RAM locations 00h-1Fh is assigned to the register bank and stack. RAM locations 20-2Fh is set aside as bit-addressable space. RAM locations 30-7Fh is available as a place to save byte-sized data.

Also, it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself. The obvious question that may arise is, "If direct addressing an address from 80h through FFh refers to SFRs, how can I access the upper 128 bytes of Internal RAM that are available on the 8052?" The answer is: You cant access them using direct addressing. As stated, if you directly refer to an address of 80h through FFh you will be referring to an SFR. However, you may access the 8052s upper 128 bytes of RAM by using the next addressing mode, "indirect addressing." Ex: MOV R0, 40H ; save the content of RAM location 40H in R0. MOV 56H, A ; Save the content of A in RAM location 56H. MOV R7, 82H ; Save the content of RAM location 82H(DPL) in R7. MOV 0E0h, #55h ; A=55h

Register Indirect Addressing Mode

In the register indirect addressing mode, a register is used as a pointer to a data. If the data is inside the internal RAM, only R0, R1 are used for this purpose, and they must be preceded by the @sign. This mode makes accessing data dynamic rather than static as in the case of direct addressing mode. Ex: MOV A, @R0 ; Move contents of RAM location whose address is held by R0 into A. MOV @R1, B ; Move contents of B into RAM location whose address is held by R1. Disadvantages: Indirect addressing always refers to Internal RAM; it never refers to an SFR. Thus, in a prior example we mentioned that SFR 99h can be used to write a value to the serial port. Thus one may think that the following would be a valid solution to write the value 1 to the serial port: MOV R0,#99h ;Load the address of the serial port MOV @R0,#01h ;Send 01 to the serial port -- WRONG!! This is not valid. Since indirect addressing always refers to Internal RAM these two instructions would produce an undefined result since the 8051 only has 128 bytes of Internal RAM. Accessing external data is not possible with R0, R1. Because external memory is 16 bitaddressable.

Indexed Addressing Mode

On chip ROM access & PM: This mode is widely used in accessing data elements of look up table entries located in the program ROM space of the 8051.The instruction used for this purpose is MOV A, A+@DPTR. Here, A+@DPTR Holds the address of the data stored in on-chip ROM.C means code. A index of the look up table. Ex: WAP to transfer the bytes into RAM from ROM space (i.e. look-up table ) ORG MOV 0000H DPTR, #SID

MOV MOV LOC: CLR MOV MOV INC INC DJNZ HERE: SJMP ORG SID DB END

R0, #40H R7, #07 A A, A+@DPTR; Move a data from code space pointed by DPTR+A to A. @R0, A R0 DPTR R7, LOC HERE 250H AMERICA ; Loop until counter=0 ; Save it in RAM

Accessing DM(Data memory or external memory): External Memory is accessed using a suite of instructions which use what I call "External Direct" addressing. I call it this because it appears to be direct addressing, but it is used to access external memory rather than internal memory. There are only two commands that use External Direct addressing mode: MOVX A,@DPTR MOVX @DPTR, A As you can see, both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address of external memory that you wish to read or write. Once DPTR holds the correct external memory address, the first command will move the contents of that external memory address into the Accumulator. The second command will do the opposite: it will allow you to write the value of the Accumulator to the external memory address pointed to by DPTR.

4. Differentiate between a microprocessor and micro controller.

Microprocessor 1. Intended to be a general purpose digital computer. 2. Contains a CPU, memory addressing 1.

Micro controller Intended to be a special purpose digital controller. 2. Contains a CPU, memory addressing

circuits and interrupt handling circuits. 3. Has many opcodes for moving data from external memory to the CPU. 4. Is concerned with rapid movement of code and data from external addresses to the chip. 5. Has one or two types of bit-handling instructions. 6. Must have many additional parts to be operational.

3. 4. 5. 6.

circuit, interrupt handling circuit, as well as timers, parallel and serial I/O, and internal RAM and ROM. Has one or two opcodes. Is concerned with rapid movement of bits within the chip. Has many type of bit handling instructions. Can function as a computer with no addition of external digital path.

5. With a neat diagram, explain the operation of port 1 of 8051. Explain the functions of port 3. PORT 1

The output latch is directly connected to the gate of the lower FET, which has an FET circuit labeled Internal FET Pullup as an active pullup load.

When used as an input, a 1 is written to the latch , turning the lower FET off. The pin and the input to the pin buffer are pulled high by the FET load. An

external circuit can overcome the high-impedance pull-up and drive the pin low to input a 0 or leave the input high for a 1.

If used as an output, the latches containing a 1 can drive the input of an external circuit high through the pull up. If a 0 Is written to the latch, the lower FET is on, the pull up is off, and the pin can drive the input of the external circuit low.

To aid in speeding up switching times when the pin is used as an output, the internal FET pullup has another FET in parallel with it. The second FET is turned on for two oscillator time periods during a low-to-high transition on the pin as shown in figure. This arrangement provides a low impedance path to the positive voltage supply to help reduce rise times in charging any parasitic capacitances in the external circuitry.

It is also to be observed that the Port 1 pins have no dual functions.

PORT 3

Port 3 is an input/output port similar to port 1. The input and output functions can be programmed under the control of the P3 latches or under the contol of various other special function registers. The port 3 alternate uses are shown in the table.

PIN P3.0-RXD P3.1-TXD P3.2-(~INTO) P3.3-(~INT1)

Alternate Use Serial data input Serial data output External Interrupt 0 External interrupt 1

SFR SBUF SBUF TCON.1 TCON.3

P3.4-T0 P3.5-T1 P3.6-(~WR) P3.7-(~RD)

External timer 0 input External timer 1 input External memory write pulse External memory read pulse

TMOD TMOD

Unlike ports 0 and 2, which can have external addressing functions and charge all eight port bits when in alternative use, each pin of port 3 may be individually programmed to be either used as I/O or as one of the alternate functions.

6. Write a program to put the number 34h in registers R4, R5, R6 and R7 using different addressing modes. Immediate Addressing

ORG 0

MOV R4,#34H MOV R5,#34H MOV R6,#34H MOV R7,#34H SJMP $ END

Register Addressing

ORG 0 MOV A,#34H MOV R4,A MOV R5,A MOV R6,A MOV R7,A SJMP $ END

Direct Addressing(considering R4,R5,R6,R7 to be in the Bank Zero)

ORG 0 MOV A,#34H MOV 4,A MOV 5,A

MOV 6,A MOV 7,A SJMP $ END

Indirect Addressing

ORG 0 MOV 8,#34H ; storing data in R0 of first bank MOV R0,#8H MOV 4,@R0 MOV 5,@R0 MOV 6,@R0 MOV 7,@R0 SJMP $ END ;location address of R0 of first bank

7. list out the microprocessors.

ans.

typical

applications

of

microcontrollers

and

microcontroller, also known as a "true computer" is used in many embedded products. home appliances: ucs are used in telephones, security systems, garage door openers, fax machines, computers, tv,cable tv tuner, vcr, camcorder, remote controls, video game devices, cellular phones,musical instruments, electronic sewing machines, lighting controller,camers,toys and gym equipments. Looking on to the diverse use of microcontrollers in the devices that are used frequently, there is no doubt in saying that we live in the era of microcontrollers rather than saying that the latter is in our era. office appliances:

Major elevtronic devices used in offices like telephones,security systems, computers,laser printer, colour printer, microwave, fax machine use microcontrollers in them. auto appliances: In the auto world, engine control,instrumentation,security system,cellular phone, entertainment, climate control etc use microcontrollers in them. though microcontrollers prove to be a boon in the embeded industry , it is the microprocessors that perform some major tasks where the microcontrollers fail to do. The leading microprocessors maufacturers have stepped forward to implement more functions into the processor chips.The POWER PC is a joint adventure of the ibm and freescale and is targetted for the high end of the embedded market and also the pc market. The critical issue of power consumption is well handled by the mups based on x86 and 680x0 and have also been efficient in consuming minimum space. apart from this, i/o, com port and rom have also been integrated into a single CHIP. The All three major seventh-generation game consoles contain PowerPC-based processors. because of the dos and windows standardization, x86 has become the predominant muc in most of the computers. This saves both money and development time as there are already meny softwares written for dos and windows platforms. The microprocessors have proved their existence in the aerospace and military spacecrafts. It is also used in printers and graphics, and network and usb devices. The personal digital assistants have helped managing many schedules for the man. tv set top boxes and digital recorders use the processors. Apart from the diverse use of this chip, supercomputers and servers have also profounded the applications. 08.with a neat block diagram, explain the architecture of 8051. ans.

The 8051 microcontroller known as 'THE TRUE COMPUTER ON A CHIP' comprises the features of both Harvard and Von-Neumann architectures. While the ability of 8051 to address 64k makes it an HARVARD architecture, its feature of mapping a single block of memory to act as both program and data memory makes it the VON-NEUMANN architecture. The memory is organized into data and program memory which includes 4kb of internal program memory ,128bytes of internal ram and many special function registers (SFR). Packed in a 40pin DIP, the following features of 8051 makes it an actual 'TRUE COMPUTER'

. The 'A' and 'B' registers: Out of the 34 general purpose registersof 8051, these two registers hold the results of many instructions pertaining to 8051, particularly math and logical operations. The 'B' register is used in association with 'A' for multiplication and division operations. 'A' is a multipurpose register also used for data transfer between 8051 and external memory. .PROGRAM COUNTER AND DATA POINTER:

Being the two 16bits registers of the 8051, they make their mark by holding the address of a byte in memory. The pc, which is the only register without an internal address, holds the addresses of the instruction bytes stacked in the program ROM. Being segmented into two 8 bit registers namely, DPH and DPL, each assigned with an unique address, the DPTR plays its role by holding memory addresses for accessing internal and external data or code. .PSW AND FLAGS: The 1 bit registers, flags are packed inside the PSW(Program Status Word) and the PCON. The four math flags(CY,OV,AC,P) are used to store results of certain instructions. The three general purpose flags are F0,GF0,GF1 and are used by the programmer to record certain results. the flags can be set and cleared at the programmer's disposition.

.INTERNAL RAM The 128byte internal ram is made up of three different areas. The first area being a collection of four register banks with 8 registers each, extends between the internal ram memory address 00h to 1Fh. The selection of the bank is under the control of two bit registers of the PSW. The next area extends from 20H to 2FH and forms the bit addressable area of the internal RAM. 128 bits can be addressed either separately or in association with the address of the byte two which they belong. The last part is known as the 'SCRATCH PAD' is used for general purpose and extends upto 7FH. SPECIAL FUNCTION REGISTERS: These internal registers are addressed from 80H to FFH and are used for those operations which exclude the use of 128 bytes of INTERNAL RAM. Some of the SFRs are bit addressable. INTERNAL ROM: This block of program instructions ranges from 0000H to 0FFFH. When PC is made to address to an address greater than 0FFFH, codes are fetched from an external rom upto an address of FFFFH. By configuring the external access pin, the entire range of codes from 0000H to FFFFH can be fetched from an external ROM.

INPUT/OUTPUT PORTS AND PINS: The DIP has 40 pins and the versatality of 8051 owes to the flexibility built into the use of these pins. The alternate pin assignments expand the 8051 from a single component to one with additional memory, serial data communication and parallel ports. The 4 port i/o with 8 pins each has an SFR associated to it . The SFR contains 8 latches which can be addressed at the SFR address to that port.

09.what is stack? with examples, explain the push and the pop instructions. ans. The shortage of registers in the microcontroller emphasises on any segment of memory that can store data or an address temperorily. THE STACK comes into picture. stack is that part of the internal ram which stores data or address temperorily. The stack pointer (sp) is the rehister which helps in accessing the locations of the stack. The 8 bit register is compatible to store the 8 bit addresses of the internal ram.when reset, the SP register holds the value 07H and thus the first location of the stack becomes 08H. PUSH and POP are the two operations that feature the stack. push: The storing of the cpu register on to the stack is called push. The stack pointer is so set that it always points to the last used location on the stack.when data is pushed on to the stack, the sp increases by a value 1. The ran addresses of the registers are used inorder to push their contents on to the stack. likewise, "push 06h" pushes the contents of the register R6. consider the following program: MOV A,#01H MOV R0,#02H MOV R1,#03H PUSH 0E0H PUSH 00H PUSH 01H

Let

us

consider

that

the

cpu

is

reset

before

executing

the program and hence theSP points to 07H.

POP: The operation of pulling off the data from the stack onto the cpu register is called pop. with every pop, the byte on the top of the stack is retrieved onto the register and the SP is decremented by one. consider the following example as the continuation of the previous example. POP 01H POP 02H POP 0E0H

Before pop instruction, the sp will be pointing to the highest stack location. once pop is executed, the 03h is popped onto the A register and the sp decrements by 1. this continues until all the sp points to 07H.

pop and push instructions are used in saving the contents of certain registers during calls. stack cannot be pulled down to the default register bank and whenever the bank1 is used, by the use of some instructions, stack is mapped onto a different memory location which can extend upto 7fh excluding the bit addressable area of the stack.

(Q-10) With a diagram, list the specific features of 8051 microcontroller. Ans: The 8051 architecture consists of these specific features: Eight-bit CPU registers A & B: These registers hold the results of many instructions, particularly math & logical operations. The A register is the most versatile, used for many operations (addition, subtraction, multiplication, division & Boolean bit manipulations) & for all data transfer between 8051 & external memory. The B register used in multiplication & division operation.

Sixteen-bit program counter(PC) & the data pointer(DPTR): Each is used to hold address of a byte in memory. Program instructions bytes are fetched from locations in memory addressed by the PC. It is automatically incremented after every instruction byte is fetched. It is the only register without an internal address. DPTR register is made up of two 8-bit registers (DPH &DPL) that are used to provide memory addresses for internal & external code access & external data access. Eight-bit Program Status Word(PSW): In order that the flags may be conveniently addressed they are grouped inside the PSW & the PCON registers. It contains all the math flags (carry, auxiliary carry, overflow & parity flag), user program flag F0, the register select bits. Eight-bit Stack Pointer: It is a register used to point to the top of stack. The address held in the SP is the location in internal RAM where the last byte of data was stored by the stack operations. Internal ROM of 4K: The 8051 is so organized that the data memory & program code memory can be in two entirely different physical memory entities. The PC is ordinarily used to address the program code bytes from 0000H to FFFFH. Internal RAM of 128 Bytes: is organized into 3 distinct features (1) 32 bytes from address 00H to 1FH that make up the 32 working registers organized as 4 banks (0-3) of 8 registers each (R0-R7). Bank 0 is selected on reset. (2) A bit addressable area of 16 bytes occupies RAM byte addresses 20H to 2F, forming a total of 128 addressable bits. (3) A general purpose RAM area above the bit area, from 30H to 7FH, addressable as bytes. Four 8-bits Ports: The 32 input/output pins are arranged as four 8-bit ports. Port 0 may serve as inputs, outputs or when used together as bi-directional low-order address & data bus for external memory. Port 1 has no dual functions. Port 2 may be used as input/output similar in operation to port 1. It is also used to supple high-order address byte in conjunction with the port 0 low-order byte to address external memory. Port 3 is similar to Port 1. Two 16-bit timer/counter (T0 &T1) Full duplex serial data receiver/transmitter(SBUF): The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any value which the 8051 receives via the serial port's RXD pin will be delivered to the user program via SBUF. In other words, SBUF serves as the output port when written to and as an input port when read from. Control Registers( TCON, PCON, TMOD, SCON, IP & IE): The Interrupt Enable SFR is used to enable and disable specific interrupts. The Interrupt Priority SFR is used to specify the relative priority of each interrupt. The Serial Control SFR is used to configure the behavior of the 8051's on-board serial port. The Timer Mode SFR is used to configure the mode of operation of each of the two timers. The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. The Power Control SFR is used to control the 8051's power control modes. Two external & Three Internal interrupt sources Oscillator & clock circuits

8051 BLOCK DIAGRAM

(Q-11) With the help of a timing diagram, explain how to interface 8K EEPROM & 4K RAM to 8051 Microcontroller. Ans: The system designer is not limited by the amount of internal RAM & ROM available on chip. Two separate external memory spaces are made available by the 16-bit DPTR & PC & by different control pins for enabling external ROM & RAM chips. Internal control circuitry accesses the correct physical memory, depending on the machine cycle state & the opcode being executed. The 8051 accesses external RAM whenever certain program instructions are executed. External ROM is accessed whenever the EA(bar) pin is grounded or when PC contains an address higher than the last address in the internal 4K ROM. 8051 users can thus use both internal & external ROM automatically. During any memory access cycle, port 0 is time multiplexed. That is, it first provides the lower byte of the 16-bit memory address, then acts as a bidirectional data bus to write or read a byte of memory data. Port 2 provides the high byte of the memory address during the entire memory read/write cycle. If the memory access is for a byte of program code in the ROM, the PSEN(bar) {Program Store Enable} pin will go low to enable the ROM to place a byte of program code on the data bus. If the access is for RAM byte, the WR(bar) or RD(bar) pins will go low, enabling data to flow between the RAM & the data bus.

To connect the 8051 to external ROM containing data, we use RD. For the ROM containing program code, PSEN is used to fetch the code. To access the external memory space, we use MOVX. To connect to external SRAM, we use both RD & WR as shown in the fig below.

(Q-12) Write a program to swap the contents of register R7 & R6 of register bank 0, in 4 different ways. Ans: The different ways to swap the contents of R6 & R7 is as discussed: METHOD 1: Using a series of register address mode MOVes. MOV A, R6 MOV R5, A MOV A, R7 ; Copy contents of R6 to A ; Save contents of R6 in R5 ; Copy contents of R7 to A ; Contents of R7 now in R6

MOV A, R6 MOV A, R5 MOV R7, A

; Retrieve contents of R6 ; Contents of R6 now in R7

(Total: 6 bytes, 6 lines) METHOD 2: Using a series of direct address mode MOVes. MOV 10H, 06H ; Copy the contents of R6 to RAM address 10H MOV 06H, 07H ; Copy contents of R6 to R7

MOV 07H, 10H ; Copy saved contents of R6 to R7 (Total: 9 bytes, 3 lines) METHOD 3: Using a series of PUSHes & POPs. PUSH 07H ; Push contents of R7 on the stack PUSH 06H ; Push contents of R6 on the stack POP 06H POP 07H ; POP contents of R6 to R7 ; POP contents of R7 to R6

(Total: 8 bytes, 4 lines) METHOD 4: Using a series of XCHes. XCH A, R6 ; Exchange contents of A & R6 XCH A, R7 ; Contents of R7 in A, R6 now in R7 XCH A, R6 ; Contents of R7 now in R6, A same (Total: 3 bytes, 3 lines)

(Q-13) List out the bit addressable SFRs available in 8051. Ans:

These are the bit addressable SFRs present in 8051.

(i) P0 (Port 0, Address 80h): This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. (ii) TCON (Timer Control, Addresses 88h): The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed.

(iii) P1 (Port 1, Address 90h): This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. (iv) SCON (Serial Control, Addresses 98h): The Serial Control SFR is used to configure the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received. (v) P2 (Port 2, Address A0h): This is input/output port 2. (vi) IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit. (vii) P3 (Port 3, Address B0h): This is input/output port 3. Similar bit addressable as P0. (viii) IP (Interrupt Priority, Addresses B8h): The Interrupt Priority SFR is used to specify the relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower priority. (ix) T2CON (Timer/Counter 2 control Register): The operation of Timer 2 (T2) is controlled almost entirely by the T2CON SFR, at address C8h. (x) PSW (Program Status Word, Addresses D0h): The Program Status Word is used to store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the PSW register contains the register bank select flags which are used to select which of the "R" register banks are currently selected. (xi) ACC (Accumulator, Addresses E0h): The Accumulator is one of the most-used SFRs on the 8051 since it is involved in so many arithmetic & logic instructions like MUL, DIV etc. (xii) B (B Register, Addresses F0h): The "B" register is used in two instructions: the multiply and divide operations. The B register is also commonly used by programmers as an auxiliary register to temporarily store values.

(Q-14) Explain the following instructions with examples: (i) SWAP A

This instruction works only in the Accumulator(A). It swaps the lower nibble & the upper nibble. In other words, the lower bits are put into the higher 4 bits & the upper 4 bits are put into the lower 4 bits. It does not affect flags. It takes one cycle & is one byte instruction. e.g.: before-10110110 (SWAP A) after-01101011 D7-D4 D3-D0 D3-D0 D7-D4

(ii) XCHD A, @Ri This instruction exchanges the lower nibble between A & the address in Ri (i=0,1) while the upper nibble of A & the upper nibble of the address location in Ri do not change. It takes one cycle & is one byte instruction. e.g.: Assuming RAM location 30H has the value 65H, MOV A, #12H MOV R1, #30H XCHD A,@R1 ; A= 12H ; R1= 30H, load pointer ; Now A=15H & RAM location 40H has 62H.

(iii) DA A The DA instruction adjusts the 8-bit value in the accumulator to correspond to binary-coded decimal (BCD) format. This instruction begins by testing the low-order nibble of the accumulator. If the AC flag is set or if the low 4 bits of the accumulator exceed a value of 9, the accumulator is incremented by 6. The high-order nibble is then tested. If the carry flag is set or if the high 4 bits of the accumulator exceed a value of 9, the value 60h is added to the accumulator. It takes one cycle & is one byte instruction. This instruction performs a decimal conversion by adding 00h, 06h, or 66h to the accumulator depending on the initial contents of the PSW and accumulator. IF (A3-0 > 9) OR (AC = 1) A=A+6 IF (A7-4 > 9) OR (C = 1) A = A + 60H

e.g.: For the set of instructions MOV A, #32H ; A=32 is the first BCD operand MOV B, #29H ; B=29 is the second BCD operand

ADD A,B DA A

; hex addition A=5BH ; Value of A now is 61H, 0110 added to lower nibble as AC=1.

(iv) MUL AB

This instruction is for byte-by-byte multiplication only. The bytes of data are assumed to be unsigned data. One operand is in A while the other in B. This instruction multiplies the contents of A & B. After multiplication, the lower byte of the result is in A & the upper byte is in B. It takes 4 cycles & is a 1 byte instruction.
MUL AB ; AxB, placing 16-bit result in B & A. e.g.: MOV A, #72H ; First operand in A

MOV B, #0E3H ; Second operand in B MUL AB ; 72*E3 = 6516H where the result B=65H & A=16H

(Q15) Explain the different ranges of jumps available in 8051 microcontroller. Ans: The jump instruction replaces the contents of the program counter with a new program address number that causes program execution to begin at the code located at the new address. It can have

(i) RELATIVE RANGE- of +127 & -128 bytes from the instruction following the jump instruction. It is so named because the address placed in program counter is relative to the address where the jump occurs. This

instruction is of two bytes in which first one is opcode & second is the

address. This has 2 advantages:

Only one byte of data needs to be specified in positive(for forward jump) or in 2s complement form(for backward jump). The displacement address can be added to PC to get absolute address. This saves program bytes & speeds up program execution. The program written with relative jumps can be located in program address space without reassembling the code to generate absolute address.

(ii) ABSOLUTE RANGE- use concept of dividing memory into logical divisions called pages. Program memory (0000H-FFFFH) can be divided into series of pages of convenient sizes like 2K, 4K etc. It jumps to an offset address within the current 11-bit (2K) address page (i.e. care must be taken to not jump outside the current page). In other words, PC15-0 = PC15-11 & sadd or PC10-0 = sadd. It has the same advantages as relative or short jump; fewer bytes are needed & the code is

relocatable as long as

the relocated code remains on the same page.

This instruction is of three bytes in which the first is the opcode and the second & third are for address. The relative address of the instruction can be anywhere on the ROM i.e. this instruction can access the entire program space from 0000H to FFFFH.
(iii) LONG JUMP-

Ranges for jump instructions

16. specify the memory area for bit level logical instructions and list them.
ans. For the bit level logical instructions , a segment of memory which permits the addressing of bits is amicable. The internal byte addresses from 20H to 2FH serves this purpose and is both byte and bit

addressable.The bit addresses are numbered from 00h to 07fh counting to a total of 128 bits. some of the sfrs are also bit addressable.

BIT LEVEL LOGICAL INSTRUCTIONS: None of the flags other than the CY flag is affected by the execution of these instructions. a) ANL C,b This instruction performs AND operation between C and the bit addressed and places the result in CARRY FLAG, C. b) ANL C,/b This instruction ANDS C and the compliment of the bit addressed and places back the result in C without affecting the bit adressed. c)ORL C,b C isORRED with the bit addressed and places the result in C.I uses only one machine cycle for its execution.

d) ORL C,/b In this instruction, C is orred with the compliment of the bit addressed and the result is placed back in the C. e) CPL b This instruction compliments the bit addressed. f)MOV C,b This instruction copies the addressed bit to the C flag. g)MOV b,C This instruction copies the C flag to the addressed bit. h)SETB C This instruction sets the carry flag to 1 i)SETB b this instruction sets the addressed bit to 1

18. WRITE AN ALP TO PERFORM 16*8 BIT MULTIPLICATION TO GET 24 BIT RESULT. INPUT THE NUMBERS FROM EXTERNAL MEMORY LOCATIONS 9000H,9001H,9002H AND OUTPUT THE RESULT TO EXTERNAL LOCATIONS FROM 9100H
FLOW CHART:

PROGRAM: ORG 0000H

LJMP ORG 8000H: MOV

8000H 8000H DPTR,#9000H ;INITIALIZE A POINTER TO POINT TO THE OPERANDS

MOVX MOV

A,@DPTR 30H,A ;MOV THE OPERAND BYTES INTO INTERNAL MEMORY LOCATIONS

INC MOVX MOV INC MOVX MOV

DPTR A,@DPTR 31H,A DPTR A,@DPTR 32H,A

MOV MOV MUL MOV MOV MOV MOV MUL MOV MOV

A,30H B,31H AB 33H,A 34H,B A,30H B,32H AB 35H,A 36H,B

;MULTIPLY THE LS BYTE WITH THE MULTIPLIER

;STORE THE 16 BIT RESULT IN INTERNAL RAM ;MULTIPLY THE MS BYTE WITH THE MULTIPLIER

;STORE THE RESULT IN INTERNAL RAM LOCATIONS

MOV MOV A,34H ADD

37H,33H

;MAKE ADDITION OPERATION OF THE CORRESPONDING RESULT BYTES STORED IN THE INTERNAL RAM AND STORE

A,35H

MOV MOV ADDC MOV

38H,A A,36H A,#00H 39H,A

IN OTHER IR LOCATIONS

MOV DESTINATION MOV MOVX INC

DPTR,#9100H

;INITIALIZE

POINTER

TO

POINT

TO

A,37H @DPTR,A DPTR ;MOVE THE STORED RESULT BYTES TO THE RESPECTIVE LOCATIONS IN THE DESTINATION

MOV

A,38H

MOVX INC MOV MOVX

@DPTR,A DPTR A,39H @DPTR,A

LJMP END

17. EXPLAIN THE FOLLOWING INSTRUCTIONS WITH EXAMPLES. a. CJNE A,DIR,RELATIVE The template for the above CJNE SOURCE _BYTE,DESTINATION_BYTE, TARGET instruction is of the form

The above instruction compares the contents of the accumulator with the contents of the direct address and jumps to the target if they are not equal. The instruction affects the carry flag. If a is less than the contents of the direct address, cy flag is set to 1 or else cy flag is set to 0. 2 machine cycles are used for the execution of this very instruction. example: Given block of 100h to 200h. Find out how many bytes from this block are greater then the number in r2 and less then number in r3. Store the count in r4. Org 0000H Mov dptr, #0100h ; get initial location ; counter ; number counter ; get the upper and lower limits in ; 20h and 21h ; get the content in acc ; check the upper limit first ; if number is larger ; jump out ; check lower limit ; if number is lower ; jump out ; if number within limit increment count ; get next location ; repeat until block completes

Mov r7, #0FFh Mov r4, #00h Mov 20h, r2 Mov 21h, r3 Nxt: Movx a, @dptr Cjne a, 21h, lower Sjmp out Lower: jnc out Cjne a, 20h, limit Sjmp out Limit: jc out Inc r4 Out: inc dptr Djnz r7, nxt Ljmp $ End b. ACALL ADDR

ACALL stands for absolute call. The function of this instruction is to call a sub-routine with a target address within 2k bytes from the current program counter. For this instruction, care must be taken not to jump outside the current page. It is a 2 byte instruction and requires four machine cycles for the execution.

ACALL has 16 bits out of which 5bits are constant(specifying a given page) and is used for the The 11 bits are used for the target subroutine address.

opcode.

During the execution, the pc register is pushed on to the stack and sp is incremented by 2. Then the pc is loaded with the new address and the cintrol is transferred to the subroutine. At the end of the procedure, when RET is executed, PC is popped off the stack and the instruction next to the acall is executed. EXAMPLE: CALLING SUBROUTINES FOR ADDITION AND SUB ORG 0000H MOV R0,#20H MOV R1,#30H ACALL ADDER ACALL SUBTRACTOR ; CALLING SUBROUTINES FOR ADDING AND SUBTRACTING ; INITIALIZING REGISTERS WITH VALUES TO BE OPERATED ON

ADDER: MOV 36H,0E0H MOV A, R0 ADD A,R1 MOV R2,A MOV 0E0H,36H RET

;PROCEDURE AT PC ADDRESS WITHIN 2K FROM ACALL

; ADDING THE OPERANDS AND RETURNING BACK TO THE MAIN

SUBTRACTOR: MOV 36H,0E0H MOV A,R0 SUBB A,R1 MOV R3,A MOV 0E0H,36H RET

; PROCEDURE FOR SUBTRACTING

; SUBTRACTION

LJMP $ END

C. DIV AB This instruction devides the contents of register A by that of B and stores the quotient in A and the remainder in B. The operation is between bytes . this instruction affects CY and OV flags. If a byte number is divided by a 0 equivalent of the divisor, the OV flag is set. CY flag is always 0 in this instruction. it requires 4 machine cycles of operation. example: a program to divide the content of r0 by r1. Store the result in r2 and r3 (reminder). Then restore the original content of r0 Org 0000h Mov a, r0 Mov b, r1 Div ab Mov r2, a Mov r3, b Mov b, r1 Mul ab Add a, r3 Mov r0, a Ljmp end 19. GCD OF TWO 8 BIT NUMBERS $ ;get the content of r0 and r1 ; in register A and B ; divide A by B ; store result in r2 ; and reminder in r3 ; again get content of r1 in B ; multiply it by answer ; add reminder in new answer ; finally restore the content of r0

ORG 1000H

MOV

DPTR, #9000H

; initialize pointer ; store the two numbers in registers

MOVX A, @DPTR MOV R0,A

INC

DPTR

MOVX A , @DPTR MOV R2, A

LOC2: MOV A, R0 MOV DIV B,R2 AB

; ; ; ; ;

MOV A, B JZ MOV MOV MOV SJMP LOC1 A, R2 R0,A R2 ,B LOC2

LOC1:MOV

A, R2

MOV DPTR,#9100H MOVX @DPTR, A LJMP $ END

Store the two numbers in external ram memory locations 9000 and 90001 See the result in 9100h

Flowchart

20. Explain with a neat diagram, the significance of stack memory, whenever a CALL instruction is executed by the 8051 microcontroller.

A call, whether hardware or software initiated, causes a jump to the address where the called subroutine is located. At the end of the subroutine the program resumes operation at the opcode address immediately following the call. The stack area of the internal RAM is used to automatically store the address, called the return address, of the instruction found immediately after the call. The stack pointer register holds the address of the last space used on the stack. It stores the return address above this space, adjusting itself upward as the return address is stored.

The sequence of events is as explained. 1) A call opcode occurs in the program software. 2) The return address of the next instruction after the call instruction is found in the program counter. 3) The return address bytes are pushed on the stack, low byte first. 4) The stack pointer is incremented for each push on the stack.

5) The subroutine address is placed in the program counter. 6) The subroutine is executed. 7) A RET(return) opcade is encountered at the end of the subroutine. 8) Two pop operations restore the return address to the PC from the stack area in the internal RAM. 9) The stack pointer is decremented for each address byte pop.

20) EXPLAIN WITH A NEAT DIAGRAM,THE SIGNIFICANCE OF STACK MEMORY ,WHENEVER A CALL INSTRUCTION IS EXECUTED BY THE 8051
PROGRAM COUNTER

PCH

PCL

PCH SP+2 SP+2 PCL SP+2 SP+1 SP+1 RET PCH PCL RETI

SP PROGRAM COUNTER ACALL LCALL INTERNAL RAM INTERRUPT

SP

A call whether hardware or software initiated causes a jmp to the address where the called subroutine is located .At the end of the subroutine the program resumes operation at the opcode address immediately following the call. As the calls can be located anywere in the program address apace and used many times ,there must be an automatic means of storing the address of the instruction following the call so that program execution can continue after the subroutine has executed . The stack area of internal RAM is used to automatically store the address called the return address, of the instruction found immediately after the call. The stack pointer register holds the address of The last space used on the stack. It stores the return address, above this space, adjusting itself upward as the return address is stored. the terms stack and stack pointer are often used interchangeably to designate the top of the stack area in RAM that is pointed to by stack pointer

The sequence of events for the above diagram:1) A call opcode occurs in the prog software or an interrupt is generated in the hardware circuitry 2) The return address of the next instruction after the call instruction or interrupt is found in the prog counter 3) The return address bytes are pushed on the stack ,low byte first 4) The stack pointer is increamented for each push on the stack 5) The subroutine address is placed in the prog counter 6) The subroutine is executed 7) A RET (return) opcode is encountered at the end of the subroutine 8) Two pop operation restore the return address to the PC from the stack area in internal RAM

9) The stack pointer is decreamented for each address byte pop

21) WRITE A PROGRAM TO FIND THE ADDRESS OF THE FIRST TWO INTERNAL RAM LOCATIONS 20H TO 60H WHICH CONTAINS CONSECUTIVE NUMBERS.IF SO , SET THE CARRY FLAG TO 1 ELSE CLEAR THE FLAG USING A SUBROUTINE
ORG 000H LJMP START ORG 8000H START: MOV A,@R0 MOV R1,A

CJNE A

22. Explain the following instructions with examples: a) DJNZ Rn, rel Ans: The above instruction takes two cycles to execute. It is 2 byte instruction. PC+2+rel(1-byte)PC Function: Decrement and jump if not zero. Flag: None In this instruction a byte is decremented, and if the result is not zero it will jump to the target address. Here target address used is relative addressing mode which is 1-byte wide (range is 127 to -128). Ex: Count from 1 to 20 and send the count toP1. CLR A ; A=0 MOV R7, #20 ; R7=20 counter INC A

BACK:

MOV DJNZ b) MOV C, bit Ans:

P1, A R2, BACK; repeat if R2 is not equal to zero.

The above instruction takes one cycles to execute. It is 2 byte instruction. Function: a bit is copied to carry flag. Flag : carry flag. In this instruction a bit ( 0 or1)is copied to carry flag . In source position, any bit addressable registers such as A, B, PSW (except PSW.7), IP, IE, SCON, and TCON or Memory location (internal RAM only) from 20H to 2FH. Ex: 1.WAP to save the status of bit P1.7 on RAM address bit 05 MOV C, P1.7 ; get bit from the port MOV 05, C ; save bit th 2. WAP to move the content of 7 bit of the A register to pin P0.7, and also to RAM location 08H th MOV C, ACC.7 ; move the 7 bit of A register to carry MOV P0.7, C ; put it on P0.7 MOV 08H, C ; move to RAM location 08(bit addressable area)

c) JBC Ans:

bit, rel

The above instruction takes two cycles to execute. It is 3 byte instruction. PC+3+rel (1-byte)PC. Function: Jump if bit is set and clear bit Flag : None In source position, any bit addressable registers such as A, B, PSW (except PSW.7), IP, IE, SCON, and TCON or Memory location (internal RAM only) from 20H to 2FH. If the desired bit is high it will jump to the target address while at the same time the bit is cleared. Here target address used is relative addressing mode which is 1-byte wide (range is 127 to -128). Ex: The following instruction will jump to label SID if 07 of register A is high; at same time D7 is cleared to zero. ACC.7, NEXT P1, A

JBC MOV

. NEXT: d) SJMP Ans: The above instruction takes two cycles to execute. PC+2+rel (1-byte) PC. rel

This is a two byte instruction. The first byte is the opcode and the second byte is the signed number displacement, which is added to the PC (program counter) of the instruction following the SJMP to get the target address. Therefore, in this jump the target address must be within 128 to 127 bytes of the PC of the instruction after the SJMP since a single byte of address can take the values of -128 to +127. This address is often referred to as a relative address since the target address is relative to the PC. All conditional jumps are SJMP. Ex: Line 2 of the code below shows 803E as the object code for SJMP OVER, which is a forward jump instruction. The 80H, located at address 100H, is the opcode for the SJMP, and 3EH, located at address 101H, is the relative address. The address is relative to the next address location, which is 102H+F8h=140H gives the target address of the OVER label. LOC 0100 0100 0140 0140 0142 0144 0144 0146 0148 OBJ 803E 7A0A 7B64 00 00 DBFC 80F8 LINE 1 2 3 4 5 6 7 8 9

ORG SJMP ORG OVER: MOV AGAIN: MOV BACK: NOP NOP DJNZ SJMP

100H OVER 140H R2, #10 R3, #100

R3, BACK AGAIN

23.Write an ALP to generate the first ten FIBONACCI series numbers.

Ans: Flow chart : Start

A=0, B=1 P0=32, C=8

A=30H, B=31H R0, R7

(P0)A+B AB, B (P0) Loc1 P0=P0+1 C=C-1 N Is C=0?

Y A=0, B=1

End Algorithm: Start Move the first two numbers of the series to internal RAM location (say 30h, 31h) set the counter, and a pointer (P0) which is pointed to next RAM location after first two numbers. Move sum of the contents of 30h, 31h into RAM location pointed by P0. Move content of P0 to 31h and 31h30h. Increment the pointer and decrement the counter. Check for counter is equal to 00.if yes initialize 30h,31h to 0 and 1.otherwise repeat the steps from step2. End

Program:

Label

START:

Mnemonic ORG SJMP ORG MOV MOV MOV MOV MOV ADD MOV MOV

Operands 0000H START 0030H 30H, #00H 31H, #01H R0, #32H R7, #8H A, 30H A, 31H @R0, A 30H, 31H

Comments

;initialization of first 2 numbers of series ; Counter =8 ; producing the next number of the series.

HERE:

MOV INC DJNZ MOV MOV SJMP END

31H, A R0 R7, LOC1 30H, #00H 31H, #1H HERE

; increment the pointer

; Restore first 2 values to first 2 memory locations

OUTPUT: Fibonacci Series:0,1,1,2,3,5,8,13,21,34 24. What is an interrupt?List different interrupts in 8051 with their ISR addresses. Ans: An interrupt is some event which interrupts normal program execution an interrupt is a special feature which allows the
8051 to provide the illusion of "multi-tasking," although in reality the 8051 is only doing one thing at a time. The word "interrupt" can often be substituted with the word "event." An interrupt is triggered whenever a corresponding event occurs. When the event occurs, the 8051 temporarily puts "on hold" the normal execution of the program and executes a special section of code referred to as an interrupt handler. The interrupt handler performs whatever special functions are required to handle the event and then returns control to the 8051 at which point program execution continues as if it had never been interrupted. For every interrupt there must be an ISR. When an interrupt is invoked, the C runs the ISR. For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the address of ISRs is called IVT (Interrupt Vector Table).

Sl. No.

Interrupt Reset INT0 (External hardware interrupt 0) TF0 (Timer 0 interrupt) INT1 (External hardware interrupt1) TF1 (Timer 1 interrupt) RI and TI (Serial communication interrupt ) (UART)

Polling Priority 0(highest) 1 2 3 4

Flag

Pin 9

Interrupt Handler Address (hex) 0000h 000Bh 001Bh 0023h

1
2 3 4 5 6

IE0 TF0 IE1 TF1

P3.2(12) 0003h P3.3(13) 0013h

5 (lowest) RI/TI