Contents

Manual for K-Notes ................................................................................. 2

Number Systems and Boolean Algebra ................................................... 3
Combinational Logic Circuits ................................................................. 12
Sequential Logic Circuits ....................................................................... 15
A/D and D/A Converters ....................................................................... 25
Microprocessor ..................................................................................... 31

2015 Kreatryx. All Rights Reserved.

1

Manual for K-Notes

Why K-Notes?
Towards the end of preparation, a student has lost the time to revise all the chapters
from his / her class notes / standard text books. This is the reason why K-Notes is
specifically intended for Quick Revision and should not be considered as comprehensive
study material.
What are K-Notes?
A 40 page or less notebook for each subject which contains all concepts covered in GATE
Curriculum in a concise manner to aid a student in final stages of his/her preparation. It
is highly useful for both the students as well as working professionals who are preparing
for GATE as it comes handy while traveling long distances.
When do I start using K-Notes?
It is highly recommended to use K-Notes in the last 2 months before GATE Exam
(November end onwards).
How do I use K-Notes?
Once you finish the entire K-Notes for a particular subject, you should practice the
respective Subject Test / Mixed Question Bag containing questions from all the Chapters
to make best use of it.

2015 Kreatryx. All Rights Reserved.

2

Number Systems and Boolean Algebra

Decimal : Radix = 10; Symbols = (0, 1, 2, 39)

Binary : Radix = 2; Symbols = (0, 1)

Hexadecimal : Radix = 16; Symbols = (0, 1, 2., 9, A, B,., F)

Octal : Radix = 8; Symbols = (0, 1, 2, .., 7)

For radix N, following digits are possible

(0, 1, 2, , N-1)

To convert a number from radix x to bare 10 or decimal.

Eg. 136 x ? 10 1.x2 3.x 6.x0 x2 3x 6

Complimentary Number Representation

A B = A + (- B) A compliment of B
For a base r system

r 1 's compliment rn r m N
r 's compliment rn N

Where r = base
N = given number
n = no. of digits in integer part of N
m = no. of digits in decimal part of N
eg. For 378.67 10
N = 378.67 ; m = 3 ; n = 2 ; r = 10

Boolean Algebra

Compliment

0 1

10
Represented as A A

And A A

AND function
0.0 0

A.A A

0.1 0

A.1 A

1.0 0

A.0 0

1.1 0

A.A 0

OR Function

00 0

AAA

0 1 1

A 1 1

10 1

A0 A

11 1

AA 1

Laws of Boolean Algebra

1) Commutative Law
OR A A B A
AND AB BA
NAND AB BA

2) Associative Law
OR A B C A B C
AND A B C A B C

3) Consensus Law
AB AC BC AB AC

4) Distributive Law
A. B C AB AC
.

Dual : Convert all

.
10
0 1

A + (BC) = (A+B)(A+C)
5) De Morgans Law

NOR operation is same as bubbled AND

A B C................... A.B.C..............

NAND operation is same as bubbled OR

A B C................... A B C..............

6) Transposition Law

A.B AC A C A B
Operator precedence
1) Parenthesis
2) NoT
3) AND

Decreasing priority

4) OR

Minterms, Maxterms & Properties

Minterm : It is a standard product term i.e. a product term which contains all variables of a given
function either in normal form or compliment form.
Maxterm : it is standard sum term i.e. a sum term which contains all the variables of the function
either in normal or compliment form.
5

F (A, B, C) = min terms F A,B,C max terms

ABC=m 0,0,0
0
ABC=m 0,0,1
1
ABC=m 1,1,1
7

A+B+C=M
7
A+B+C=M
6
A+B+C=M
0

Properties

1) n variable function 2n minterms & 2n max terms

2) M m & m M
j
j
j
j
3) m M 2n 1i ; M m 2n 1i ; D = indicates dual


iD
iD
4)
a)

b)

2n 1

mi 1

m 0
j

i0
2n 1
j0

Note : The output of XOR and XNOR gate contains half the total number of minterms.
Forms of Boolean function
1) Sum of product (SOP) form = DNF (Distinjunctive Normal Form)
2) Canonical SOP form = DCF (Disjunctive Canonical Form)
3) Product of sum (POS) form = CNF (Conjunctive Normal Form)
4) Canonical POS form = CCF (Conjunctive Canonical Form)
Eg. Convert F A,B,C A AC ABC to Canonical SOP form :
F A AC ABC

ABC ABC ABC ABC ABC ABC

m
0

m
1

m
2

m
3

m
6

F m 0,1,2,3, 4,6 canonical SOP form

M 5,7 canonical POS form

Karnaugh Map
3 variable K map
Octant group of 8 minterms
Quad group of 4 min terms
Pair group of 2 min terms
4 variable k map
All corners of k map
(0, 2, 8, 10) Quad

Eg. F A,B,C,D m 0,1, 4,5,6,8,9,10,12,14,15

F AC AD BD BC ABC

Eg. F A,B,C M 0,1,2,3, 4,7

F A B C B C

Implicant : it is the set of all adjacent min terms

Eg. Pair, quad, octants
Prime Implicant : It is an implicant which is not a subset of another implicant.
Essential PI (EPI) : It is a prime implicant which contains at least one min terms which is not
covered by other prime implicant.
1) PI,Non PI
2) PI, EPI
3) PI, EPI
4) PI, EPI
5) PI, EPI

Dont care condition

In a digital system, for a non occurring input, the output can be taken as either one or zero
during simplification & it is called dont care condition.
Eg. X A,B,C,D m 0,1 d 10,11,12,13,14,15 ;

X ABC

Logic Gates
1) Equivalence Gate = Ex NOR Gate
A B F
0 0 1
0 1 0
1

0 0

1 1 1
F A B AB AB

2) Staircase connection = Ex OR Gate

A B F
0 0 0
0 1 1
1

0 1

1 1 0

F A B AB AB

In Ex OR, output = 1 if input has odd no. of 1s

In Ex NOR, output = 1, if input has even no. of 1s

3) Inverter

A F
0 1
1 0

FA

4) AND GATE
A
0
0
1

B
0
1
0

1 1

F
0
0
0

F=A.B
5) OR GATE
A
0
0
1

B
0
1
0

1 1

F
0
1
1

F=A+B
6) NAND GATE
A B F
0 0 1
0 1 1
1

0 1

1 1 0
F AB

This gate is equivalent to

10

7) NOR GATE
A B F
0 0 1
0 1 0
1

0 0

1 1 0

F A B
This gate is equivalent to

CODES :1) Binary coded decimal code (BCD) :a) Each digit of decimal number is represented by binary equivalent.
b) It is 4 bit binary code.
9
4
3
c) eg. 943

decimal
1001 0100 0011
94310 100101000011 2
2) Gray Code :a) Only one bit in the code group changes when going from one step to the next.
b) For 3-bit
000 001 011 010 110 111 101 100

11

Combinational Logic Circuits

1) Half Adder
A
0
0
1
1

B
0
1
0
1

S
0
1
1
1

C
0
0
0
1

S A B
C AB
1 Half adder = 1 XOR Gate & 1 AND Gate

To implement a half adder using NAND Gates, 5 NAND Gates are required.
To implement a half adder using NOR Gates, 5 NOR Gates are required.

2) Half Subtractor
A
0
0
1
1

B
0
1
0
1

D
0
1
1
0

B
0
1
0
0

D A B
B A B borrow

To implement a half sub tractor 5 NAND or 5 NOR Gates are required.

12

3) Full Adder :A

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

S
0
1
1
0
1
0
0
1

C
i1
0
0
0
1
0
1
1
1

C = Carry input
i

= Carry Output
C
i1

S A B C
C
AB BC AC
i1
i
i

To implement full adder using NAND & NOR Gates 9 Gates are required.

4) Full Subtractor:A

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

D
0
1
1
0
1
0
0
1

b
iH
0
1
1
1
0
0
0
1

D A B b
i
bi1 AB Bbi Abi

To implement full sub tractor using NAND or NOR Gates 9 Gates are required.
13

Magnitude Comparator
For 2 bit Magnitude comparator
A A1 A0

A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

B B1B0

B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

A B A B A B
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0

A B A1 B1 . A0 B0

A B A B A

B1 A 0B0

A B A B A

B1 A 0B0

1 1

1 1

Decoder
2 4 decoder

Active high output

0AB
1AB
2AB
3AB

14

Active low output

0 A B
1 AB
2 A B
3 AB

Each output of a decoder with active high output represents a min term & hence it can be used
to implement any SOP expression.

Each output of a decoder with active low output represents a max term and hence can be used
to implement any POS expression if AND Gate is used and SOP expression if NAND Gate is used.

Multiplexer
4 1 MUX
F ABI0 ABI1 ABI 2 ABI 3
2n 1 MUX requires n select lines.

A 2n : 1 MUX can be used to implement any SOP expression with (n+1) variable with n variables
applied at select lines & n 1 th variable & its complement & 1 & 0 serve as input to MUX.

Sequential Logic Circuits

1) SR Latch

0
0
1
1

0
1
0
1

Q
n1
Qn

0
1
0

S=1, R=1 and Qn+1=0 is impractical state

15

2) S R Latch

0
0
1
1

0
1
0
1

Q
n1
1
1
0
Q
n

S=1, R=1 and Qn+1 =1 is impractical state

3) Clocked SR Flip Flop

When ClK = 0, the flip flop retains its previous state.

When ClK = 1
S

0
0
1
1

0
1
0
1

Q
n1
Qn

0
1
Ambiguous state

Characteristics equations : Q
S R.Q
n1
n

16

4) J K Flip Flop
To convert SR flip flop to a JK flip flop.
S j Q ; R KQ

Characteristics equation
Q
jQ K Q
n1
n
n

0
0
1
1

0
1
0
1

Q
n1
Qn
1
0

Q
n

5) D Flip Flop

D
Qn+1
0
0
1
1
Characteristics equation

Q
D
n1

17

6) T Flip Flop

T
0
1

Qn+1
Qn

Characteristics equation

Q
n

Q
TQ
n1
n

Asynchronous or direct input

CLK
0
0
1

P
r
0
1
1

C
r
1
0
1

Q
n1
1
0

o\p depends on characteristic table of flip-flop

Preset and clear input when enabled set or reset the flip flop irrespective of the state of clock.
Types of Triggering

1) Level Triggered FF

2) Edge Triggered FF
a) +ve edge triggered

b) ve edge triggered

18

Level triggered FF are called as latch and edge triggered FF are called as Flip Flops.
Race around Condition

When a FF is in toggle mode, then due to propagation delay of gates involved in

construction of FF, output toggles multiple times instead of once & this is called as Race
around condition.
This only occurs in level triggered FF.
To avoid this problem, Master slave configuration is used.

Note: Whenever a FF is in toggle mode, output frequency is half of input frequency.

Applications of FF
1) Shift Register

3 bit shift Register

Q Q Q parallel output
2 1 0
P P P parallel input
2 1 0

1) Serial input parallel output (SIPO)

Q2

Q1

Q0

ClK

serial i / p

For n bit, time taken = nxT

Parallel output

T=clock period

19

2) Serial input serial output (SISO)

ClK
0

serial o / p

1
2
3
4
5

1
0
1

Q2
0

Q1
0

1
0
1

0
1
0
1

For n bits, time taken = (2n - 1)T,

Q0
0
0
0
1
0
1

Serial output

T = clock period

3) Parallel input parallel output (PIPO)

Parallel input can be fed to register using preset enable and for input to propagate to parallel
output, it does not require any clock pulse.
4) Parallel input serial output (PISO)
Suppose P P P 101 2
2 1 0
ClK

1
2

Q2
1

Q1
0
1

Q0
1
0
1

Serial output

For n bits, (n-1) clock cycles are required.

20

COUNTERS
Asynchronous Counters

Different ff are applied with different clocks.

No. of stages in a counter are called as modules of a counter.

MOD 5 Counter = 5 Stages

n
2 N
N = no. of bits or no. of flip flop required
N = no. of stages in a counter

If MOD M and MOD N counter are cascaded, resultant counter is MOD (MN)

Ripple Counter

ClK Q
0
1
2
3
4
5
6
7
8

2
0
0
0
0
1
1
1
1
0

Q
1
0
0
1
1
0
0
1
1
0

o
0
1
0
1
0
1
0
1
0

This is a MOD 8 up counter

In a n bit ripple counter, propagation delay of each ff is t
, then time period of ClK is
pd ff
t

1
=> fClK
,
nt
ClK
pdff
nt
pdff

1
f

max n t
pdff

21

Note:
i)
ii)

ve edge trigger Q as clock up counter

+ve edge trigger Q as clock up counter

iii)

ve edge trigger Q as clock down counter

iv)

+ve edge trigger Q as clock down counter

BCD Counter (Decade Counter)

4 Flip flops are required.

This counter counts from 0000 1001

And as soon as count is incremented to 1010, then CLR input of ff is asserted and all ff are reset
to 0 and count again becomes 0000, so this counter counts from 0 9.
Ring Counter (Synchronous Counter)
The last FF output is connected to first FF input.

22

ClK Q
0

2
0

Q
1
0

1
2

0
1

0
0

1
0

3
4

0
0

1
0

0
1

0
0

A n bit synchronous counter has n status.

Johnson Counter (Twisted Ring Counter)

ClK Q

2
0
1
1
1
0
0
0

0
1
2
3
4
5
6

Q
1
0
0
1
1
1
0
0

0
0
0
0
1
1
1
0

A n bit Johnson counter has 2n states.

T = (2n) TCLK
Synchronous counter design for given sequence

Suppose counting sequence is 0 3 1 2 0

Using positive edge triggered D FF

23

State diagram

Excitation Table
Present state

Next State

Q
1
0
1
0
1

Q
1
1
0
1
0

0
0
1
1
0

D Q ; D Q
1
1
2
1

Q
0
1
1
0
0

D1 D0

1 1
0 1
1 0
0 0

Q
0

24

Conversion of different flip flops

From

SR
Flip Flop
-

SR FF
JK FF
D FF

J=S
K=R
D S RQ

T FF

T SQ RQ

JK
Flip Flop
S JQ

D
Flip Flop
S=D
R D

R=kQ
-

T
Flip Flop
S TQ

D JQ kQ

J=D
K D
-

R = TQ
J=T
K=T
D TQ

T JQ kQ

T DQ

A/D and D/A Converters

Digital to Analog Converter (DAC)

Resolution
The change in analog voltage corresponding one LSB increment in digital input.

Re solution

V
r
n
2 1

V = reference voltage corresponding to logic 1

r
N = no. of bits

V
Re solution Decimal equivalent of binary i / p
analog
1
%resolution
100%
n
2 1

Resolution of R 2R ladder type DAC is

V
Re solution r
2n

25

1) Weighted Resister DAC (4 - bit)

V
V
V
V
I r b ; I r b ; I r b ; I r b
3 R
3
2 2R
2
1 4R 1 0 8R
0
V
V I I I I R r R b 2b 4b 8b
0
3 2 1 0 f
1
2
3
8R f 0

LSB Resistance = 2n 1 MSB Resistance

2) R 2R ladder
a) 3 bit Non inverting R 2R ladder

R
V 1 f
0
R
1

R
V n1
V r 2i b 1 f
i
x 2n
R
1

i0

Resolution Decimal gain

26

b) 3 bit R 2R Inverting ladder

R
V n1
f
V r 2i b
0
i R R
n
2
i

i0

Analog to Digital Converter (ADC)

a) Counter Type ADC

Maximum number of clock pulse required for n bit conversion is 2n 1

Maxm Conversion time = 2n 1 T

CLK

27

b) Parallel Comparator Type

2 1 comparators required

For n bit 2n resistors required

n
2 n priority encoder

This is called as Flash ADC.

Fastest ADC of all

For SAR & Dual slope ADC, refer EMMI K Notes.

28

Logic Families
1) RTL (Resistor Transistor Logic)

(Wired AND Logic)

(Basic NOR Gate)

A B
0 0

T
1
cut off

T
2
cut off

V
0
1

0 1

cut off

saturation

cut off

0 saturation

1 1 saturation saturation

2) DTL (Diode Transistor Logic)

29

A B
0

T
Y
1
0 OFF 1

NAND Gate

0 1 OFF 1

0 OFF 1

ON

When all input are high then D

& D are reverse biased and D , D . Become forward biased

B
2
1

and T becomes ON and output becomes low.

1
3) TTL (Transistor Transistor Logic)

T : multi emitter Transistor

1

A B T
1
0 0 A

T
2
C

T
3
C

T
4
S

0 1

1 1

A : Active
C : Cut off
S : Saturation

30

Microprocessor
The 8085 Microprocessor

It is an 8 bit up (microprocessor)

It is an 40 PIN IC

Its data bus has 8 bits

Its address bus has 16 bits

It is capable of addressing 64 K of memory

Address Bus:

It is 16 bits of length

It is unidirectional bus.

It is decided in to 2 parts namely

Lower order address bus A0 A7 is also called Line number
Higher order address bus A8 A15 is also called page number
Interrupts and externally initiated operations: -

The 8085 up has 5 interrupts signals that can be used to interrupt a program execution

It also accepts external interrupts to provide acknowledgement (ack) to the external device.

Here TRAP, RST 7.5, RST 6.5, RST 5.5, INTR are called Hardware interrupts.

1. INTR

It is abbreviated as interrupt request

It is used as general purpose interrupt

It has least or 5th priority

It is a non-vectored interrupt

Address is provided by user or external device

It is a level triggered signal.

2. INTA

It is abbreviated as interrupt acknowledge

It is an output signal.

3. TRAP

It has highest priority

It is the only non-maskable interrupt.

31

It is a vectored interrupt.

Also called RST 4.5

This is both edge and level triggered signal.

Its vectored address = 0024 H

Trick : since it is a RST 4.5
Hexa 24 0024
So, 4.5 x 8 = 36
H
H
decimal

4. RST 7.5

Is has 2 nd highest priority

It is maskable interrupt

It is a vectored interrupt.

It is edge triggered only

It vectored address = 003C H

5. RST 6.5

It has 3rd highest priority.

It is a maskable interrupt.

It is a vectored interrupt.

It is level triggered.

It vectored address = 0034 H .

6. RST 5.5

If has 4th highest priority.

It is a maskable interrupt.

It is a vectored interrupt.

It is level triggered

Its vectored address = 002C H

8085 Microprocessor Flags

The flags are affected by the arithmetic and logic operations in the ALU :In most of these operations the result is stored in accumulator therefore the flags generally
reflect data conditions in the accumulator with some exceptions. The descriptions and
conditions of the flag as follows:

Sign flag (S) :- After execution of an arithmetic or logic operation, if bit D 7 of the result (usually
in the accumulator ) is 1, the sign flag is set .

32

Zero Flag (Z) : - The zero flag is set if the ALU operations result in 0, and the flag is reset if the
result is not 0. This flag is modified by the result in the accumulator as well as in other registers.

Auxiliary carry flag (AC) : - In an arithmetic operation, when a carry is generated by digit D3 and
passed on to digit D4 the AC flag is set.

Parity Flag (P) : After an arithmetic or logical, operation, if the result has an even number of 1s,
the flag is set. If it has an odd number of 1s, the flag is reset.

Carry flag (CY) : If an arithmetic operation results in a carry, the carry flag is set; otherwise it is
reset.

Among the five flags, the AC flag is used internally for BCD arithmetic the instruction set does
not include any conditional jump instruction based on the AC flag of the remaining four flags,
the Z and CY flags are those most commonly used.
REGISTERS

General Purpose

Special Purpose

Register (GPR)

Register (SPR)

B (8 bits)
C (8 bits )
D (8 bits)
E (8 bits)
H( 8bits)
L (8 bits)

User Accessible

User Not Accessible

Accumulator (8 bits)

Temporary Register (8 bits)

SR (8 bits)
PC (8 bits)
SP (8 bits)

1 R (8 bits)
Increment / decrement
address latch (8 bits)

33

Possible register pairs are :

B C (16 bits)
D E (16 bits)
H L (16 bits)

Accumulator (A) : -

It is a 8 bits SPR and user accessible

It acts as one source of operand to the ALU and destinations to the result.
During I/O data transfer, data is transferred between accumulator (A) and I/O device.

Status register (SR) :-

It is also called Flag registers

It is used to store ALU results
FLAGS are used for testing of data conditions
PSW (program status word) = Accumulator + flag register. Also PSW is a 16 bit register.

Program counter (PC) :-

It is a a 16 bit SPR which is accessible

It is required to keep track of the address of the next instruction to be fetched from the
memory of execution.

In other words we can say, PC provides the address of next instruction to memory which has
to be executed

when a byte is fetched then PC automatically incremented by 1 to point to next memory

location.

when the microprocessor is reset, the PC sets to 0

Stock pointer :
It is a 16 bit SPR used as memory pointer SP provides the address of stack top or top address of
stack.

A memory location in R/W memory is called STACK. It is a part of RAM, which is used
during subroutines PUSH and POP operations.

34

Instruction Set:
INSTRUCTION

SYMBOLIC FORM

EXAMPLE

LXI rP , 16 bit Data

rp

16 bit data

Lx 1H, 2800 H MC=1+2=3

(load register pair

immediately)

rh

8 MSBs of data

i.e. |L| [00]

rl

8 LSBs of data

LDA address (Load

accumulator direct)
STA address
(STORE
accumulator direct)
LHLD address (load
H L pair direct)
SHLD address
(Store H L pair
direct)
LDAX rP : (Load

A address

|[address]| |A|

A rp

XCHG : (Exchange
the content of H
L pair D E pair)

NO FLAGS
are Affected

4T + (3T x 3) =
13T

No flags are
Affected

STA 2000H

MC=1+2+1

4 T + (2x3T) +
3T = 13T

No flags are
affected

4T + (4 x3T) =
16T states

No flags are
affected

4T + (2 x 3T) +
(2 x 3T) =16 T
states

No flags are
affected

4T + 3 T = 7T
States

No flags are
affected

4T + 3T = 7T

NO Flags
are Affected

4T states

No flags are
Affected

LHLD2500 H

MC = 1 + 4
=5

SHLD 2500 H

MC=1+2+2
=5

LDAX B

MC = 1 + 1
=2

rp

4T + (3T x 2) =
10T

1+3=4

H [|address + 1|]

address L
address 1 H

F LAGS
AFFECTED

LDA 2400 H

=4

L [|address|]

T-STATE

(H) [28]

accumulator
indirect)
STAXrP : (store
accumator indirect)

MACHINE
CYCLE

STAXD

MC = 1 + 1
=2

|H L| |D E|

XCHG data

35

MC = 1

INSTRUCTION
MOV r1 ,r2 (move
the content of one
register into
another register )

SYMBOLIC FORM

r1 r2

MOV r, M

r M or

(Move the content

of Memory to
register)

MOV M, r

M r or

(Move the content

of register to
memory)

H L

MVI r, data

r data

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

MOV A, B

1 MC

4 T - STATE

NO FLAGS
Affected

MOV B, M

MC = 1 + 1

4T + 3T = 7T

No flags
Affected

4 T + 3 T = 7T

No flags
affected

4T + 3 T = 7 T

No flags
affected

H L

=2

MOV M, C

MC = 1 + 1
=2

MVI A, 05

(Move immediate
data to register)

MC = 1 + 1
=2

36

INSTRUCTION

SYMBOLIC FORM

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

MVl M, data

H L data

MC = 1+ 1 + 1

(move immediate
data to memory)

M data

LXI H, 2400 H
MVl M, 08

4 T + 3T+3T
= 10T states

No flags
are
affected

or

=3

HLT Halt

ADD r (Add register

to accumulator)

A A r

ADD B

MC = 1

4T states

All flags
are
affected

ADC r : (Add
register with carry
to accumulator)

A A r cs

ADC B

MC = 1

4T states

All flags
are
affected

ADD M : (add
memory to
accumulator)

A M

ADD M

MC = 1 + 1 =2

4T + 3 T = 7T
States

All flags
are
affected

ADC M

MC = 1 + 1 =2

4T + 3 T = 7T
States

All flags
are
affected

MC = 1 + 1 =2

4T + 3T = 7T

All Flags
are
Affected

ADC M : (add
memory to
accumulator)
ADI data :

or

H L

A A M CS
or

A A

H L

CS

A A data ADl 08

(Add immediate
data to
accumulator)
ACI data :
(add with carry
immediate data to
accumulator)
SUB r : (subtract
register from
accumulator)

|A| |A| + data

+ |cs|

ACI 08

MC = 1 + 1 =2

4T +3T = 7T

All flags
are
Affected

|A| |A| |r|

SUB 08

MC = 1

4T

All flags
are
affected

37

INSTRUCTION

SYMBOLIC FORM

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

SBB r : (subtract
register from
accumulator with
Borrow)

A A r cs

MC = 1

4T

All flags
are
affected

SUB M : (subtract
memory from
accumulator)

A A M

MC = 1 + 1 =2

4T + 3T =7T
states

All flags
are
affected

MC = 1 + 1 =2

4T + 3 T = 7T
States

All flags
are
affected

SBB M : (subtract
memory from
accumulator alone
with borrow)

or

A A H L

A A M
or

A A H L

SUI data (subtract

immediate data
from accumulator)

A A data

MC = 1 + 1 =2

4T + 3 T = 7T
States

All flags
are
affected

SBI data (subtract

immediate from
accumulator with
borrow)

A A data CS

MC = 1 + 1 =2

4T + 3T = 7T

All Flags
are
Affected

MC = 1

4T

All flags
are
Affected
except CY

MC= 1+1+1=3

4T+3T+3T

All flags
are
affected
except CY

INR r (increment
register content by
1)

|r| |r| + |01|

INR M (increment
|M| |M| + [01] Or
memory content by
[H L] |[H L]|+ [01]
1)

=10T

38

INSTRUCTION

SYMBOLIC FORM

INX rP : (increment
the content of
register pair by 1)

rp rp 0001

DCR M :
(Decrement the
content of memory
by 1)

M M 01

DCX rP:
(Decrement the
content of Memory
by )1
DAA : (Decimal
adjust accumulator
after addition)
DAD rP (Double
addition register
pair)
ANA r: (And
register with
accumulator)

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

INX H
INX SP
INX C

MC = 1

4T

All flags
except CY
are affected

MC = 1 + 1 +1

4T + 3T+3T
=10T

All flags are

affected
except CY
flag

MC = 1

6T

No flags are
affected

MC = 1

4T

All flags are

affected

MC = 1 + 2 =3

4T +(2 x 3T)
= 10T

Only carry
(CY) is
affected

MC = 1

4T States

All flags are

Affected
AC=1,

=3

or H L H L 01

rp rp 0001

DCX B
DCX SP
DCX H

DAA

H L H L rp

|A||A| |r|

CY= 0
ANA M : (And
memory with
accumulator)

|A| |A| |M|

MC = 1+1 =2

|A| |A| |[H L]|

39

4T+3T=7T State

All flags are

affected AC
=1, CY = 0

INSTRUCTION

SYMBOLIC FORM

EXAMPLE

MACHINE
CYCLE

T-STATE

FLAGS
AFFECTED

ANI data : (And

immediate data
with accumulator)

A A data

MC = 1+1=2

4T +3T=7T

All flags
affected AC
= 1, CY =0

ORA r (OR register

with accumulator)

A A V M

MC = 1

4T

All flags are

affected CY
= 0, AC = 0

ORA M : (OR
memory with
accumulator)

A A VM

MC = 2

7T

CY = 0,
AC=0

ORI data (or data

immediate with
accumulator)

A A V data

MC = 2

7T

CY = 0, AC
=0

XRA r : EXOR
register with
accumulator

A A V r

MC =1

4T

All flags are

affected
and AC = 0,
CY = 0

XRA M : EXOR
memory with
accumulator

A A V M

MC =1

4T

All flags are

affected
and AC = 0,
CY = 0

XRI data: EXOR

immediate data
with accumulator

A A V data

MC =2

7T

All flags are

affected AC
=0, CY = 0

CMA :
(Complement with
Accumulate)

A A

MC = 1

4T

No flags are
affected

MC = 1

4T

All flags are

Affected

CMP r: (Compare
register with
accumulator)

|A||A| |r|

40

INSTRUCTION

SYMBOLIC FORM

CMP M : (compare
memory with
accumulator)

|A| |A| |M|

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

MC = 1+1 =2

4T+3T=7T

All flags are

affected

CPI data : (compare

immediate data
with accumulator)

A A data

MC =2

4T +3T=7T

All flags
affected

CMC :
(complement the
carry status)

CS CS

MC = 1

4T

No flags are
affected
except carry
flag

STC (Set carry

status)

CS 1

MC = 1

4T

NO flags
are affected
except CY
flag

MC = 1+2=3

6T+(3T x
2)= 12T
states

No flags are
affected

MC =1+2=3

6T + (3T x
2) = 12T
state

No flags are
affected

MC =1 +2=3

10T state

No flags are
affected

MC = 1

6T

No flags are
affected

RST n: (Restart)

SP 1 PC
SP 1 PCL

SP SP 2
PC 8 times

Push rP: (Push the

content of register
pair to stack)

SP 1 rh

SP 2

SP SP 2

POP rP : (POP the

content of register
pair which has
been saved from
stack)

r sp

SPHL : (move the

content of HL pair
to SP)

H L SP

rh sp 1
sp sp 2

41

INSTRUCTION

SYMBOLIC FORM

XTHL : (Exchange
stock top with H
L pair)

| L | | SP |

IN Port address :
(Input to
accumulator from
I/O part)

|A| |port |

Out port address :

(output to
accumulator to I/o
part)

port A

HLT : (Halt)

HLT

EXAMPLE

MACHINE
CYCLE

T-STATE

F LAGS
AFFECTED

MC = 5

4T + (3T x
2) + (3T x 2)
= 16 T

No flags are
Affected

MC = 1+1+1

4T+3T+3T=
10T

No flags are
affected

MC =3

4T+3T+3T=
10T

No flags are
affected

MC = 1

5 T state

No flags are
affected

MC = 1

6T state

NO flags
are affected

MC = 1+2=3

4T+(2 x3T)=
10T states

| H | |SP| +1

=3

PCHL :(jump to
address specified
by H L pair)

PC H L
PCH H
PCL L

Unconditional
JMP instruction
RLC : (Rotate accumulator left)
Symbolic form :

n1 An
A A7
0

CS A7
The content of the accumulator is rotated left by one bet
42

RRC : (Rotate accumulator right)

Symbolic form :

A7 A0

CS A0

An An1
The content of the accumulator is rotated right by one bit
RAL : (Rotate accumulator left through carry)
Symbolic form :

n1 An

CS A7
A CS
0

The content of the accumulator is rotated left one bit through carry.
RAR : - (Rotate accumulator right through carry)

An An1

Symbolic form :

CS A0
A CS
7

The content of the accumulator is rotated right one bit through carry.
Conditional JMP instruction : OPCODE

Operand

Description

JC

16 bit

jump on carry (if result generate CY = 1)

JNC

16 bit

jump on carry (cy = 0)

JZ

16 bit

jump on zero (if result generate or Z = 1)

JNZ

16 bit

jump one no zero (Z = 0)

43

JP

16 bit

jump on plus (if D7 = 0, s =0)

JM

16 bit

jump on minus (if D7 =1 and S = 1)

JPE

16 bit

jump on even parity (p = 1)

JPO

16 bit

jump on odd parity (P = 0)

Unconditional CALL instruction :

When it is executed, microprocessor will store address of next instruction is STACK
MC = 1 + 2 + 2 = 5
6T + (3T x 2) + (3T x 2) = 18T states
No flags are affected
Conditional CALL :
CC call subroutine if carry flag is set (CY =1)
CNC call subroutine if carry flag is reset (CY = 0)
CZ call subroutine if zero flag is set (z = 1)
CNZ call subroutine if zero flag is reset (z = 0)
CM call subroutine if sign flag is set (s =1, negative number)
CP call subroutine if sign flag is reset (s =0, positive number)
CPE call subroutine if parity flag is set (P =1, even parity)
CPC call subroutine if parity flag is reset (P =0, odd parity)

Unconditional RET instruction :

It will change program sequence from subroutine to main program.
MC = 1 + 2 = 3
4T + (3T x 2) = 10T states
No flags are affected.
44

Conditional RET instruction :

RC Return if carry flag is set (CY =1)
RNC Return if carry flag is reset (CY = 0)
RZ

Return if zero flag is set (z = 1)

RNZ Return if zero flag is reset (z = 0)

RM Return if sign flag is set (s =1, negative number)
RP

Return if sign flag is reset (s =0, positive number)

RPE Return if parity flag is set (P =1, even parity)

RPC Return if parity flag is reset (P =0, odd parity)

RST n : (restart)
Symbolic form : [(Sp 1) [PC]H]
(Sp 2) (PC)L
(Sp ) (Sp 2)
[PC] 8 times n
MC = 1 + 2 =3
6 T + (3T x 2) = 12 T states
No flags are affected

45