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    Octal Transparent Latch With 3-State Outputs Octal D-Type Flip-Flop With 3-State Output SN54/74LS373 SN54/74LS374

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    Miyuki_22
    The SN54/74LS373 and SN54/74LS374 are octal latch and flip-flop integrated circuits. The SN54/74LS373 contains eight transparent latches that can latch input data asynchronously when an enable signal is high, and output the latched data when an output enable signal is low. The SN54/74LS374 contains eight D-type flip-flops that can clock input data from the D-inputs to the Q-outputs on the rising edge of a clock signal, and output the stored data when an output enable signal is low. Both ICs have 3-state outputs that can high impedance the outputs to allow for bus-oriented applications.

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    Octal Transparent Latch With 3-State Outputs Octal D-Type Flip-Flop With 3-State Output SN54/74LS373 SN54/74LS374

    Uploaded by

    Miyuki_22
    122 views2 pages
    The SN54/74LS373 and SN54/74LS374 are octal latch and flip-flop integrated circuits. The SN54/74LS373 contains eight transparent latches that can latch input data asynchronously when an enable signal is high, and output the latched data when an output enable signal is low. The SN54/74LS374 contains eight D-type flip-flops that can clock input data from the D-inputs to the Q-outputs on the rising edge of a clock signal, and output the stored data when an output enable signal is low. Both ICs have 3-state outputs that can high impedance the outputs to allow for bus-oriented applications.

    Original Description:

    data sheet

    Original Title

    SN74LS373N

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    The SN54/74LS373 and SN54/74LS374 are octal latch and flip-flop integrated circuits. The SN54/74LS373 contains eight transparent latches that can latch input data asynchronously when an enable signal is high, and output the latched data when an output enable signal is low. The SN54/74LS374 contains eight D-type flip-flops that can clock input data from the D-inputs to the Q-outputs on the rising edge of a clock signal, and output the stored data when an output enable signal is low. Both ICs have 3-state outputs that can high impedance the outputs to allow for bus-oriented applications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    122 views2 pages

    Octal Transparent Latch With 3-State Outputs Octal D-Type Flip-Flop With 3-State Output SN54/74LS373 SN54/74LS374

    Uploaded by

    Miyuki_22
    The SN54/74LS373 and SN54/74LS374 are octal latch and flip-flop integrated circuits. The SN54/74LS373 contains eight transparent latches that can latch input data asynchronously when an enable signal is high, and output the latched data when an output enable signal is low. The SN54/74LS374 contains eight D-type flip-flops that can clock input data from the D-inputs to the Q-outputs on the rising edge of a clock signal, and output the stored data when an output enable signal is low. Both ICs have 3-state outputs that can high impedance the outputs to allow for bus-oriented applications.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 2

    SN54/74LS373

    SN54/74LS374

    OCTAL TRANSPARENT LATCH


    WITH 3-STATE OUTPUTS;
    OCTAL D-TYPE FLIP-FLOP
    WITH 3-STATE OUTPUT

    OCTAL TRANSPARENT LATCH


    WITH 3-STATE OUTPUTS;
    OCTAL D-TYPE FLIP-FLOP
    WITH 3-STATE OUTPUT

    The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
    organized system applications. The flip-flops appear transparent to the data
    (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is
    LOW, the data that meets the setup times is latched. Data appears on the bus
    when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
    the high impedance state.
    The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common
    to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low
    Power Schottky technology and is compatible with all Motorola TTL families.

    LOW POWER SCHOTTKY

    20
    1

    Eight Latches in a Single Package


    3-State Outputs for Bus Interfacing
    Hysteresis on Latch Enable
    Edge-Triggered D-Type Inputs
    Buffered Positive Edge-Triggered Clock
    Hysteresis on Clock Input to Improve Noise Margin
    Input Clamp Diodes Limit High Speed Termination Effects

    PIN NAMES

    J SUFFIX
    CERAMIC
    CASE 732-03

    N SUFFIX
    PLASTIC
    CASE 738-03

    20
    1

    DW SUFFIX
    SOIC
    CASE 751D-03

    LOADING (Note a)
    20

    HIGH
    0.5 U.L.
    0.5 U.L.
    0.5 U.L.
    0.5 U.L.
    65 (25) U.L.

    Data Inputs
    Latch Enable (Active HIGH) Input
    Clock (Active HIGH going edge) Input
    Output Enable (Active LOW) Input
    Outputs (Note b)

    D0 D7
    LE
    CP
    OE
    O0 O7

    LOW

    0.25 U.L.
    0.25 U.L.
    0.25 U.L.
    0.25 U.L.
    15 (7.5) U.L.

    ORDERING INFORMATION
    SN54LSXXXJ
    Ceramic
    SN74LSXXXN Plastic
    SN74LSXXXDW SOIC

    NOTES:
    a) 1 TTL Units Load (U.L.) = 40 A HIGH/1.6 mA LOW.
    b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
    (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
    65 U.L. for Commercial (74) Temperature Ranges.

    CONNECTION DIAGRAM DIP (TOP VIEW)


    SN54 / 74LS374

    SN54 / 74LS373
    VCC

    O7

    D7

    D6

    O6

    O5

    D5

    D4

    O4

    LE

    VCC

    O7

    D7

    D6

    O6

    O5

    D5

    D4

    O4

    CP

    20

    19

    18

    17

    16

    15

    14

    13

    12

    11

    20

    19

    18

    17

    16

    15

    14

    13

    12

    11

    10

    OE

    O0

    D0

    D1

    O1

    O2

    D2

    D3

    O3

    GND

    NOTE:
    The Flatpak version
    has the same pinouts
    (Connection Diagram) as
    the Dual In-Line Package.

    10

    OE

    O0

    D0

    D1

    O1

    O2

    D2

    D3

    O3

    GND

    FAST AND LS TTL DATA


    5-521

    SN54/74LS373 SN54/74LS374
    TRUTH TABLE
    LS373

    LS374

    Dn

    LE

    OE

    On

    Dn

    Q0

    Z*

    LE

    OE

    On

    Z*

    H = HIGH Voltage Level


    L = LOW Voltage Level
    X = Immaterial
    Z = High Impedance
    * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).

    LOGIC DIAGRAMS
    SN54LS / 74LS373

    

    

    
     
     
    
    

    

    
    
    

    

    

    
    
    

    

    

    
    
    

    

    
    
    

    

    
    
    

    
    
    

      
      
     

    
    
    
    

    
    

    

    
    

    

    

    

    

    

    

    

    

    

    SN54LS / 74LS374
    

    

    

    

    

    

    

    

    

    

    

    
     
     

     
     

     
     

     
     

     
     

     
     

     
     

     
     

    
    

    

    

    
    

    

    
    

    

    

    

    

    GUARANTEED OPERATING RANGES


    Symbol

    Parameter

    Min

    Typ

    Max

    Unit

    VCC

    Supply Voltage

    54
    74

    4.5
    4.75

    5.0
    5.0

    5.5
    5.25

    TA

    Operating Ambient Temperature Range

    54
    74

    55
    0

    25
    25

    125
    70

    IOH

    Output Current High

    54
    74

    1.0
    2.6

    mA

    IOL

    Output Current Low

    54
    74

    12
    24

    mA

    FAST AND LS TTL DATA


    5-522

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