Ordering number : ENA1130A

STK672-640A-E

Thick-Film Hybrid IC

2-phase Stepping Motor Driver

Overview
The STK672-640A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.

Applications
Office photocopiers, printers, etc.

Features
Built-in overcurrent detection function (output current OFF).
Built-in overheat detection function (output current OFF).
If either over-current or overheat detection function is activated, the FAULT signal (active low) is output.
Built-in power on reset function.
The motor speed is controlled by the frequency of an external clock signal.
2 phase or 1-2 phase excitation switching function.
Using either or both edges of the clock signal switching function.
Phase is maintained even when the excitation mode is switched.
Rotational direction switching function.
Supports schmitt input for 2.5V high level input.
Incorporating a current detection resistor (0.089: resistor tolerance 2%), motor current can be set using two
external resistors.
The ENABLE pin can be used to cut output current while maintaining the excitation mode.
With a wide current setting range, power consumption can be reduced during standby.
No motor sound is generated during hold mode due to external excitation current control.

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.

62911HKPC 018-08-0035/71608HKIM No. A1130-1/21

STK672-640A-E
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter

Symbol

Conditions

Ratings

unit

Maximum supply voltage 1

VCC max

No signal

52

Maximum supply voltage 2

VDD max

No signal

-0.3 to +6.0

Input voltage

VIN max

Logic input pins

-0.3 to +6.0

Output current 1

IOP max

10A, 1 pulse (resistance load)

20

Output current 2

IOH max

VDD=5V, CLOCK200Hz

IOF max

mA

Output current 3

Pin16 output current

10

Allowable power dissipation 1

PdMF max

With an arbitrarily large heat sink. Per MOSFET

8.3

Allowable power dissipation 2

PdPK max

No heat sink

3.1

Operating substrate temperature

Tc max

105

Junction temperature

Tj max

150

Storage temperature

Tstg

-40 to +125

Allowable Operating Ranges at Ta=25C

Parameter

Symbol

Conditions

Ratings

unit

Operating supply voltage 1

VCC

With signals applied

10 to 42

Operating supply voltage 2

VDD

With signals applied

55%

Input high voltage

VIH

Pins 10, 12, 13, 14, 15, 17

2.5 to VDD

Input low voltage

VIL

Pins 10, 12, 13, 14, 15, 17

0 to 0.8

Output current 1

IOH1

Tc=105C, CLOCK200Hz,

3.0

3.3

Continuous operation, duty=100%

Output current 2

IOH2

Tc=80C, CLOCK200Hz,
Continuous operation, duty=100%,
See the motor current (IOH) derating curve

CLOCK frequency
Phase driver withstand voltage
Recommended operating

fCL
VDSS
Tc

Minimum pulse width: at least 10s

0 to 50

kHz

ID=1mA (Tc=25C)

100min

0 to 105

0.14 to 1.31

No condensation

substrate temperature
Recommended Vref range

Vref

Tc=105C

Refer to the graph for each conduction-period tolerance range for the output current and brake current.
Electrical Characteristics at Tc=25C, VCC=24V, VDD=5.0V
Parameter

Symbol

Conditions

VDD supply current

ICCO

Pin 9 current CLOCK=GND

Output average current

Ioave

R/L=1/0.62mH in each phase

min

typ

0.519

max

unit

4.4

0.625

0.731

mA
A

FET diode forward voltage

Vdf

If=1A (RL=23)

0.83

1.5

Output saturation voltage

Vsat

RL=23

0.20

0.33

Input high voltage

VIH

Pins 10, 12, 13, 14, 15, 17

Input low voltage

VIL

Pins 10, 12, 13, 14, 15, 17

FAULT low output voltage

VOLF

Pin 16 (IO=5mA)

5V level FAULT leakage current

IILF

Pin 16=5V

5V level input current

IILH

Pins 10, 12, 13, 14, 15, 17=5V

GND level input current

IILL

Pins 10, 12, 13, 14, 15, 17=GND

Vref input bias current

IIB

Pin 19=1.0V

PWM frequency

fc

Overheat detection temperature

TSD

2.5

0.25

50

29
Design guarantee

0.8

0.5

10

75

10

10

15

45

61

kHz

144

*Ioave values are for when the lead frame of the product is soldered to the mounting substrate.
Notes: A fixed-voltage power supply must be used.

No. A1130-2/21

STK672-640A-E
Package Dimensions
unit:mm (typ)
29.2
25.6
(20.47)

4.5

14.4

(5.0)

(5.0)

(12.9)

2.0

7.2

11.0

14.5

19

(3.5)

14.5

(R1.7)

1.0
(5.6)

4.2

0.52

0.4
8.2

18 1.0=18.0

(20.4)

Derating curve of motor current, IOH, vs. STK672-640A-E Operating substrate temperature, Tc
IOH - Tc

4.5

200Hz 2-phase excitation

4.0

Hold mode

Motor current, IOH - A

3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0

10

20

30

40

50

60

70

80

90

Operating Substrate Temperature, Tc- C

100

110
ITF02588

Notes
The current range given above represents conditions when output voltage is not in the avalanche state.
If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-6** series hybrid ICs given
in a separate document.
The operating substrate temperature, Tc, given above is measured while the motor is operating.
Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent
operation of IOH, always verify this value using an actual set.

No. A1130-3/21

STK672-640A-E
Block Diagram
N.C
8
VDD=5V

MODE1 10
N.C 11

VDD
Excitation mode
selection

MODE2 17

AB

5
F1

3
F2

BB
1
F4

F3

FAO
Phase
excitation
signal
generator

Phase
advance
counter

CLOCK 12
CWB 13
RESETB 14

N.C
7

FBO
FBB

Overcurrent
detection

Latch
Circuit

Power-on
reset

FAB

R1

R2

P.G2

ENABLE 15

AI
FAULT 16

FAULT
signal
(open drain)

Current control
chopper circuit

BI
P.G1
6

Vref/4.9
Vref

Latch
Circuit

Overheating
detection

Amplifier
VSS
100k
VSS

VSS

S.G 18
Vref 19

Sample Application Circuit

STK672-640A-E
VDD(5V)

CLOCK

12

MODE1

10

MODE2

17

CWB

2 phase stepping motor driver

4
5

A
VCC
24V

AB

13

ENABLE

15
3

RESETB
14
R01

R03

C01
at least 100F
16

FAULT

Vref
19
R02

B
BB

18

P.G2
P.G1

P.GND

S.G

No. A1130-4/21

STK672-640A-E
Precautions
[GND wiring]
To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18
(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.
[Input pins]
If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S.G, Pin 18,
and do not apply a voltage greater than or equal to VDD voltage.
Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal
block diagram.
Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17.
Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17
are used as inputs, a 1 to 20k pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).
[Current setting Vref]
Considering the specifications of the Vref input bias current, IIB, a value of 1k or less is recommended for R02.
If the motor current is temporarily reduced, the circuit given below (STK672-630A-E: IOH>0.2A, STK672-640A-E:
IOH>0.3A) is recommended.
5V

5V
R01

R01

Vref

Vref
R02

R3

R3

R02

Motor current peak value IOH setting

IOH

IOH=(Vref4.9) Rs
The value of 4.9 in Equation above represents the Vref voltage as divided by a circuit inside the control IC.
Vref=(R02 (R01+R02)) 5V(or 3.3V)
Rs is an internal current detection resistor value of the hybrid IC.
Rs=0.141 when using the STK672-630A-E
Rs=0.089 when using the STK672-640A-E

No. A1130-5/21

STK672-640A-E
[Smoke Emission Precuations]
If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at
VCCON (24V ON), causing the STK672-630A-E, STK672-640A-E to emit smoke because 5V circuits cannot be
controlled.
In addition, as long as one of the output Pins, 1, 3, 4, or 5, is open, inductance energy stored in the motor results in
electrical stress on the driver, possibly resulting in the emission of smoke.
Input Pin Functions
Pin Name

Pin No.

Function

CLOCK

12

Reference clock for motor phase current switching

MODE1

10

Excitation mode selection

Input Conditions When Operating

Operates on the rising edge of the signal (MODE2=H)
Low: 2-phase excitation
High: 1-2 phase excitation

MODE2

17

High: Rising edge

CWB

13

Motor direction switching

RESETB

14

System reset

Low: Rising and falling edge

Low: CW (forward)
High: CCW (reverse)
A reset is applied by a low level

Initial state of A and BB phase excitation in the timing

charts is set by switching from low to high.
ENABLE

15

The A, AB, B, and BB outputs are turned off, and after

The A, AB, B, and BB outputs are turned off by a low-

operation is restored by returning the ENABLE pin to the

level input.

high level, operation continues with the same excitation

timing as before the low-level input.

Output Pin Functions

Pin Name
FAULT

Pin No.
16

Function
Monitor pin used when over-current detection or overheat

Input Conditions When Operating

Low level is output when detected.

detection function is activated.

Note: See the timing chart for the concrete details on circuit operation.

No. A1130-6/21

STK672-640A-E
Timing Charts
2-phase excitation
VDD
Power On Reset
(or RESETB)

MODE1
MODE2
CWB
CLOCK

ENABLE
FAO

FAB

FBO
FBB

1-2 phase excitation

VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE
FAO

FAB

FBO

FBB

No. A1130-7/21

STK672-640A-E
1-2 phase excitation (CWB)

VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE

FAO

FAB

FBO

FBB

2 phase excitation Switch to 1-2 phase excitation

VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE

FAO

FAB

FBO

FBB

No. A1130-8/21

STK672-640A-E
1-2 phase excitation (ENABLE)
VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE

FAO

FAB

FBO

FBB

1-2 phase excitation (Hold operation results during fixed CLOCK)

VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE
Hold operation
FAO

FAB

FBO

FBB

No. A1130-9/21

STK672-640A-E
2 phase excitation (MODE 2)
VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE

FAO

FAB

FBO

FBB

1-2 phase excitation (MODE 2)

VDD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB

CLOCK

ENABLE
FAO

FAB

FBO

FBB

No. A1130-10/21

STK672-640A-E
Usage Notes
1. STK672-630A-E, STK672-640A-E input signal functions and timing
[ENABLE, CLOCK and power on reset, RESETB (Input signal timing when power is first applied)]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD,
which is outside the operating supply voltage, is less than 4.75V.
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10s until CLOCK
input.
3.8V typ

4V typ
Control IC power (VDD) rising edge
Control IC power on reset

RESETB signal input

No time specification

ENABLE signal input

CLOCK signal input

At least 10s

At least 10s

ENABLE, CLOCK, and RESETB Signals Input Timing

[CLOCK (Phase switching clock)]
Input frequency: DC to 50kHz
Minimum pulse width: 10s
MODE2=1(High) Signals are read on the rising edge.
MODE2=0(Low) Signals are read on the rising and falling edges.
[CWB (Motor direction setting)]
The direction of rotation is switched by setting CWB to 1 (high) or 0 (low).
See the timing charts for details on the operation of the outputs.
Note: The state of the CWB input must not be changed during the 6.25s period before and after the rising edge of the
CLOCK input.
[ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)]
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later
restored to the 1 state, the IC will resume operation with the excitation timing continued from before the
point ENABLE was set to 0.
If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the
theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing
the CLOCK cycle is required.

No. A1130-11/21

STK672-640A-E
[MODE1 and MODE2 (Excitation mode selection)]
MODE1=0: 2-phase excitation
MODE2=1: Rising edge of CLOCK
MODE1=1: 1-2 phase excitation
MODE2=0: Rising and falling edges of CLOCK
See the timing charts for details on output operation in these modes.
Note: The state of the MODE input must not be changed during the 5s period before and after the rising edge of the
CLOCK input.
[Configuration of Each Input Pin]
<Configuration of the MODE1, MODE2, CLOCK, CWB, ENABLE, and RESETB input pins>
Input pins: Pin 10, 17, 12, 13, 15, and 14
5V

10k

100k
VSS

All input pins of this driver support schmitt input. Typ specifications at Tc = 25C are given below. Hysteresis voltage
is 0.3V (VIHa-VILa).

When rising

When falling

1.8V typ

1.5V typ

Input voltage

VILa

VIHa

Input voltage specifications are as follows.

VIH=2.5V min
VIL=0.8V max
<Configuration of the FAULT Input Pin>

5V

<Configuration of the Vref Input Pin>

Vref/4.9
-

Output pin
Pin 16

Input pin
Pin 19

+
Amplifier
100k
VSS

VSS

VSS

The internal impedance, 100k, is designed so that the increase in current is prevented while Pin 19 is open.
The recommended Vref voltage is 0.14V or higher because the output offset voltage of Vref/4.9 amplifier cannot be
controlled down to 0V

No. A1130-12/21

STK672-640A-E
2. Overcurrent Detection and Overheat Detection Functions of the STK672-630A-E and STK672-640A-E
Each detection function operates using a latch system and turns output off. Because a RESET signal is required to
restore output operations, once the power supply, VDD, is turned off, you must either again apply power on reset
with VDDON or apply a RESETB=HighLowHigh signal.
[Overcurrent detection]
This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there
is a short between the motor terminals.
Overcurrent detection occurs at 3.5A typ with the STK672-630A-E and at 5.5A typ for the STK672-640A-E.

Current when motor terminals are shorted

PWM period
Set motor
current,
IOH

Over-current detection
IOH max
MOSFET all OFF

No detection interval
(5.5s typ)
Normal operation

5.5s typ

Operation when motor pins are shorted

Overcurrent detection begins after an interval of no detection (a dead time of 5.5s typ) during the initial ringing part
during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the
current exceeds IOH.
[Overheat detection]
Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature
of the aluminum substrate (144C typ).
Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of
reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking.
However, we cannot guarantee operations without breaking in the case of operations other than those recommended,
such as operations at a current exceeding IOH max that occurs before overcurrent detection is activated.

No. A1130-13/21

STK672-640A-E
3. Calculating STK672-640A-E HIC Internal Power Loss
The average internal power loss in each excitation mode of the STK672-640A-E can be calculated from the following
formulas.
Each excitation mode
2-phase excitation mode
2PdAVex=(Vsat+Vdf) 0.5CLOCKIOHt2+0.5CLOCKIOH (Vsatt1+Vdft3)
1-2 Phase excitation mode
1-2PdAVex=(Vsat+Vdf) 0.25CLOCKIOHt2+0.25CLOCKIOH (Vsatt1+Vdft3)
Motor hold mode
HoldPdAVex= (Vsat+Vdf) IOH
Vsat: Combined voltage represented by the Ron voltage drop+shunt resistor
Vdf: Combined voltage represented by the MOSFET body diode+shunt resistor
CLOCK: Input CLOCK (CLOCK pin signal frequency)
t1, t2, and t3 represent the waveforms shown in the figure below.
t1: Time required for the winding current to reach the set current (IOH)
t2: Time in the constant current control (PWM) region
t3: Time from end of phase input signal until inverse current regeneration is complete
IOH

0A

t1

t2

t3

Motor COM Current Waveform Model

t1= (-L/(R+0.20)) In (1-((R+0.20)/VCC) IOH)
t3= (-L/R) In ((VCC+0.20)/(IOHR+VCC+0.20))
VCC: Motor supply voltage (V)
L: Motor inductance (H)
R: Motor winding resistance ()
IOH: Motor set output current crest value (A)
Relationship of CLOCK, t1, t2, and t3 in each excitation mode
2-phase excitation mode: t2= (2/CLOCK) - (t1+t3)
1-2 phase excitation mode: t2= (3/CLOCK) -t1
For Vsat and Vdf, be sure to substitute values from the graphs of Vsat vs. IOH and Vdf vs. IOH while the set current
value is IOH.
Then, determine whether a heat sink is required by comparing with the graph of Tc vs. Pd based on the average HIC
power loss calculated.
When designing a heat sink, refer to the section Thermal design found on the next page. The average HIC power
loss, PdAV, described above does not have the avalanches loss. To include the avalanches loss, be sure to add
Equation (2), STK672-6** Allowable Avalanche Energy Value to PdAV above. When using this IC without a fin
always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of
convection around the HIC.

No. A1130-14/21

STK672-640A-E
STK672-640A-E Output saturation voltage, Vsat - Output current, IOH
Vsat - IOH

05
C

0.8

Tc
=1

Output saturation voltage, Vsat - V

1.0

0.6

C
25

0.4

0.2

0
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output current, IOH - A

4.5
ITF02589

STK672-640A-E Forward voltage, Vdf -Output current, IOH

Vdf- IOH

1.4

Forward voltage, Vdf - V

1.2

25C
Tc=
C
105

1.0

0.8

0.6

0.4

0.2
0
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output current, IOH - A

4.5
ITF02590

Substrate temperature rise, Tc (no heat sink) - Internal average power dissipation, PdAV
Tc - PdAV

Substrate temperature rise, Tc - C

80
70
60
50
40
30
20
10
0
0

0.5

1.0

1.5

2.0

2.5

3.0

Hybrid IC internal average power dissipation, PdAV - W

3.5
ITF02551

No. A1130-15/21

STK672-640A-E
4. STK672-640A-E Allowable Avalanche Energy Value
(1) Allowable Range in Avalanche Mode
When driving a 2-phase stepping motor with constant current chopping using an STK672-6** Series hybrid IC,
the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS.
VDSS: Voltage during avalanche operations

VDS
IOH: Motor current peak value

IAVL: Current during avalanche operations

ID
tAVL: Time of avalanche operations
ITF02557

Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-6** Series when
Driving a 2-Phase Stepping Motor with Constant Current Chopping
When operations of the MOSFET built into STK672-6** Series ICs is turned off for constant current chopping,
the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly
rises due to electromagnetic induction generated by the motor coil.
In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by
VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at
this time, EAVL1, is represented by Equation (1).
EAVL1=VDSSIAVL0.5tAVL ------------------------------------------- (1)
VDSS: V units, IAVL: A units, tAVL: sec units
The coefficient 0.5 in Equation (1) is a constant required to convert the IAVL triangle wave to a
square wave.
During STK672-6** Series operations, the waveforms in the figure above repeat due to the constant current
chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (2) used to find
the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (1).
PAVL=VDSSIAVL0.5tAVLfc ------------------------------------------- (2)
fc: Hz units (fc is set to the PWM frequency of 50kHz.)
For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-6** Series and substitute values when
operations are observed using an oscilloscope.
Ex. If VDSS=110V, IAVL=1A, tAVL=0.2s when using a STK672-640A-E driver, the result is:
PAVL=11010.50.210-650103=0.55W
VDSS=110V is a value actually measured using an oscilloscope.
The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3.
When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL
waveforms during operation, and then check that the result of calculating Equation (2) falls within the allowable
range for avalanche operations.

No. A1130-16/21

STK672-640A-E
(2) ID and VDSS Operating Waveforms in Non-avalanche Mode
Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during
actual operations.
Factors causing avalanche are listed below.
Poor coupling of the motors phase coils (electromagnetic coupling of A phase and AB phase, B phase and
BB phase).
Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor.
Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V.
If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as
shown in Figure 2.
Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss
range of PAVL shown in Figure 3.

VDS
IOH: Motor current peak value

ID
ITF02558

Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-6** Series when Driving a
2-Phase Stepping Motor with Constant Current Chopping

Average power loss in the avalanche state, PAVL- W

Figure 3 Allowable Loss Range, PAVL-IOH During STK672-640A-E Avalanche Operations

PAVL - IOH

5.0
4.5
4.0

Tc=
80
C

3.5
3.0
2.5

105

2.0

1.5
1.0
0.5
0
0

0.5

1.0

1.5

2.0

2.5

Motor phase current, IOH - A

3.0

3.5
ITF02591

Note:
The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current
chopping.
Because it is possible to apply 3W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used
to drive the motor as a zener diode.

No. A1130-17/21

STK672-640A-E
5. Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC.
The value of PdAV increases as the output current increases. To calculate PdAV, refer to Calculating Internal HIC
Loss for the STK672-630A-E, STK672-640A-E in the specification document.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction
during motor rotation and off time both exist during actual motor operations,
IO1
Motor phase current
(sink side)

IO2
0A

-IO1
T1

T2

T3

T0

Figure 1 Motor Current Timing

T1: Motor rotation operation time
T2: Motor hold operation time
T3: Motor current off time
T2 may be reduced, depending on the application.
T0: Single repeated motor operating cycle
IO1 and IO2: Motor current peak values
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1P1+T2P2+T30) TO ---------------------------- (I)
(Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2)
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
c-a in Equation (II) below and the graph depicted in Figure 3.
c-a= (Tc max-Ta) PdAV ---------------------------- (II)
Tc max: Maximum operating substrate temperature =105C
Ta: HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105C or less.
The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation.
To add the loss during avalanche operations, be sure to add Equation (2), Allowable STK672-6** Avalanche Energy
Value, to PdAV.

No. A1130-18/21

STK672-640A-E
Figure 2 Substrate temperature rise, Tc (no heat sink) - Internal average power dissipation, PdAV
Tc - PdAV

Substrate temperature rise, Tc - C

80
70
60
50
40
30
20
10
0
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Hybrid IC internal average power dissipation, PdAV - W

ITF02553

Figure 3 Heat sink area (Board thickness: 2mm) - c-a

c-a - S

Heat sink thermal resistance, c-a - C/W

100
7
5
3
2

Wi t

10

Wi t

7
5

ha

3
2

1.0
10

hn

o su
rfac
e fi
nish
flat
blac
k su
rfac
e fi
nish

100

7 1000

Heat sink area, S - cm2

ITF02554

6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta

Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 3.1W is allowable at Ta=25C, and of up to 1.75W at Ta=60C.
Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta
PdPK - Ta

Allowable power dissipation, PdPK - W

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0
0

20

40

60

80

Ambient temperature,Ta - C

100

120
ITF02511

No. A1130-19/21

STK672-640A-E
7. Example of Stepping Motor Driver Output Current Path (1-2 phase excitation)
2-phase stepping motor

N.C

MODE2
CLOCK
CWB

RESETB

IOAB

N.C

VDD

VDD=5V
MODE1
N.C

IOA

Excitatin
mode setting

Phase
excitation
signal
generation

BB

F3

F4

Latch

FAB
FBO
FBB

VCC
24V

Over
current
detection

+ C02
at least 100F
P.G2

ENABLE
FAULT

F2

FAO

Phase
advnce
counter
Power
on
reset

F1

AB

FAULT
signal
(Opendrain)
Over heat
detection

AI
BI

Chopper
circuit

P.GND

Vref/4.9
Latch

Vref
VSS Amp

P.G1

100k
V

S.G

VSS

Vref

CLOCK

Phase A output
current
IOA
PWM operations

Phase AB output
current

When PWM operations of IOA

are OFF, for IOAB, negative
current flows through the
parasitic diode, F2.

IOAB
When PWM operations of IOAB
are OFF, for IOA, negative
current flows through the
parasitic diode, F1.

No. A1130-20/21

STK672-640A-E

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PS No. A1130-21/21