A Low-Power CMOS Chopper Amplifier For EEG Acquisition Systems

1
A Low-Power CMOS Chopper Amplifier for EEG

Acquisition Systems
B. Narayan, H. Sane, J. Zaveri
I. Introduction
HE demand for technologies that help neuroscientists

and clinicians to actively observe a large number of
neurons in the brain has increased significantly. Currently
the biopotential acquisition systems are bulky and not
portable that makes it difficult for the on-going diagnostics and causes discomfort to the patient. There is a need
to make these systems more compact and to extend their
applications to various fields.
Commonly monitored biopotential signals are EEG,
ECG, and EMG. Figure 1 shows the characteristics of these
signals, and it can be seen that they have a very low signal amplitude and operate at extremely low frequencies
(<150 Hz). This is a major reason their performance is
limited by the offset and the noise of the input amplifiers.
The physical origin of low frequency noise in MOSFETs
is the carrier number fluctuation theory, or the trappingdetrapping model. It is caused by the fluctuation of the
number of inversion layer carriers as they are trapped and
detraped to and from traps located in the oxide, and it accounts for the carrier number and the mobility fluctuations
[1]. It should also be noted that the typical offset voltages
for these applications is around 10 V.
Fig. 1. Frequency and Amplitude of Biopotential Signals
Some techniques that can be employed to remove the

offset and the 1/f noise dynamically include chopper stabilization, autozeroing (AZ), and correlated double sampling (CDS). While the latter two mentioned are sampling
techniques, chopper stabilization is a modulation technique
that can eliminate the effects of op-amp imperfections.
The chopper stabilization technique was first introduced
in 1948 by E.A. Goldberg [2]. Earlier, the chopping techniques involved switched ac coupling of the input signal
and demodulation of this signal back to the dc signal.
While these amplifiers achieved very low offset, and very
high gain, they had limited bandwidth and required filtering to remove the large ripple voltages generated by chopping. This problem was solved by introducing the chopper
stabilized amplifiers that combined the chopper amplifier

with a conventional wideband amplifier that remained in
the signal path [3]. The chopper stabilization technique
Fig. 2. Chopper Stabilization Amplifiers [4]
essentially uses an ac carrier to perform amplitude modulation on the input signal. The principle of chopper amplification is demonstrated in figure 2 [4]. As seen in the figure, the system consists of modulating and demodulating
carriers with period T= 1/fchop , where fchop is the chopper
frequency. It should be noted that the signal is bandlimited to half of the chopper frequency to prevent aliasing.
Basically, amplitude modulation using a carrier transposes
the signal to higher frequencies where there is no 1/f noise,
and then the modulated signal is demodulated back to the
baseband after amplification. A low pass filter with a cut
off frequency slightly above the input signal bandwidth
(>fchop /2) is used to recover the original signal in the amplified form. Noise and offset are modulated only once, and
from the Power Spectral Density Equation, it can be seen
that they will be translated to the odd harmonic frequencies of the modulating signal, leaving the chopper amplifier
without any offset or low-frequency noise [4].
II. Design Details
A. DC Offset Zeroing Technique
Since the EEG signals operate at extremely low voltage
range, they are associated with high common-mode interferences. There is also a significant differential electrode
offset (DEO) voltage created between the biopotential electrodes just before amplification. Many techniques have
been proposed in [5] [6]. This paper will focus on using
the DC Servo Loop outside the choppers that will introduce a high pass filter mechanism. The circuit is shown in
figure 3. It is divided into a coarse low pass filter with discrete out levels and a fine low pass filter with a continuous
output range [7].
first stage. In order to meet the stability requirements,

the cutoff frequency of the first stage will be designed to
a higher frequency when compared to the gain crossover
frequency of the amplifier. As seen in figure 4, the cutoff
frequency of the second stage can be designed lower than
the fchop . The phase compensation capacitor will work as a
narrow band first-order LPF which will satisfy the filtering
requirements [4]. The equation for the input referred noise
of this amplifier will be
Vn,in = Vth1 + Vf n2 + Vtn2 / A1
Fig. 3. DC offset regulation through fine and coarse servo loops [7].
B. Chopping and Filtering Technique

The principle of this technique was discussed in section
I. The input signal is modulated to the chopping frequency,
amplified and then demodulated back to the baseband.
Typically, the offset from the amplifier is modulated only
once and appears at the chopping frequency and its odd
harmonics.
The residual offset of a chopper amplifier exists and typically is in the order of V. Basically the residual offset of
a chopper amplifier mainly arises from the spikes of the input chopper, or from the charge injection mismatch of the
switches. A major reason this arises is due to the input
impedence Rin and the mismatch in parasitic capacitive
coupling between the chopping signal and the input lines.
A technique to solve this problem is using nested choppers.
The idea is to consider the conventional chopper as a regular amplifer with no 1/f noise and a reduced offset. This
offset can be reduced by applying another pair of choppers that now operate at a much lower frequency. Because
this chopper works in a low frequency, the residual offset
is reduced even further. However, it would be hard to implement this technique, since the usage of two amplifiers
shoots up the power dissipation, which is one of the most
critical specification.
In the equation Vtn1 and Vtn2 are the thermal noise of the
first two stages, Vf n2 is the noise of the second stage and
A1 is the first stage gain.
III. Block Diagram and Design Specifications
The figure below is the overall block diagram of the system that was discussed in detail in the previous section.
Following the block diagram is a chart specifying our design specifications. As seen in the figure, the HPF is used
to zero the DC offset, and the method proposed is using
the DC servo-loop outside the choppers. The next block
is the chopper amplifier block - and the proposed method
is using a 2-stage amplifier after the demodulator - that
not only improves the stability, increases gain, but also
acts as a low pass filter to get rid of the higher frequencies
containing the residual offset and the 1/f noise.
Fig. 5. Block diagram of the system.
Fig. 4. Proposed method for filtering technique at the output stage

[4].
After demodulation, the system normally consists of a

low pass filter, that will eliminate high frequencies in which
the offset and the noise were present. The technique for
low pass filtering discussed in this paper consists of a pole
configuration 2-stage amplifier. A dominant pole is placed
at the second stage and a second pole is placed at the
Fig. 6. Design specifications.
B. Narayan, H. Sane, J. Zaveri: A CMOS CHOPPER INSTRUMENTATION AMPLIFIER WITH ...LOW NOISE, LOW FREQUENCY 3
References
[1] Y. Nemirovsky, I. Brouk, C. Kakobson, 1/f Noise in CMOS
Transistors for Analog Applications, IEEE Transactions on
Electron Devices vol. 48, no. 5, May 2001.
[2] http://www.linear-tech.com/pub/document
[3] http://www.analog.com
[4] Y. Masui, T. Yoshida, A. Iwata Low Power and low voltage
chopper amplifier without LPF, IEICE Electronics Express vol.
5, no. 22, 2008.
[5] R.F. Yazicioglu, et. al. A 60 W 60 nV/rt. Hz Readout Frontend
for Portable Biopotential Acquisition Systems, IEEE Journal
of Solid State Circuits pp.1100-1110, May 2007.
[6] T. Denison, K. Consoer, A. Kelly et. al., A 2.2 W 94 nV,
rt. Hz, Chopper-Stabilized Instrumentation Amplifier for EEG
Detection in Chronic Implants ISSCC Dig. Tech. Papers pp.162163, 2007.
[7] R.F. Yazicioglu, et. al. A 200 W Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems, IEEE Journal of
Solid State Circuits vol. 43, no. 12, December 2008.
[8] A. Bakker, K. Thiele, J. Huijsing, A CMOS Nested-Chopper
Intrumentation Amplifier with 100-nV Offset, IEEE Journal of
Solid State Circuits vol. 35, no. 12, December 2000.
[9] M. R. Nuwer, et. al., IFCN Standards for Digital Recording of
Clinical EEG, ECG and Neurophysiology, vol. 106, no. 3, pp.
259-261, Mar. 1998.
IV. Appendix
A. Compairson Chart
The table here shows the advances made by different
groups.
Fig. 7. Comparison chart [4]
References for this chart:

[4] M. R. Nuwer, et. al., IFCN Standards for Digital
Recording of Clinical EEG, ECG and Neurophysiology,
vol. 106, no. 3, pp. 259-261, Mar. 1998.
[5] R.R. Harrison and C. Charles, A low-power low-noise
CMOS Amplifier for Neural Recording Applications IEEE
J. Solid State Circuits, pp. 958-965, June 2003.
[2] R.F. Yazicioglu, et al., A 60 uW 60 nV/rt. Hz Readout
front-end for Portable Biopotential Acquisition Systems,
IEEE J. of Solid State Circuits, pp. 1100-1110, May 2007.
[3] T. Denison, K. Consoer, A. Kelly et. al., A 2.2 uW
94 nV, rt. Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic Implants, ISSCC Dig.
Tech. Papers, pp.162-163, 2007.
B. International Federation of Clinical Neurophysiology

Standards
Below are some guidelines from IFCN:
Prior to sampling at 200 samples/sec, an anti-aliasing high
filter at 70 Hz must be used, with a roll-off of at least 12
dB/octave. Higher filter settings require proportionally
higher sampling rates. Whenever possible the low filter
should be set to 0.16 Hz or less for recording, although the
on-line EEG display during the recording may use a different setting of the low filter. Electrode impedances should
be kept below 5 kQ and preamplifier input impedances
must be more than 100 MQ. The common mode rejection
ratio must be at least 110 dB for each channel measured at
amplifier input. Additional noise in the recording should
be less than 1.5 mV peak-to-peak and 0.5 mV root-meansquare at any frequency from 0.5100 Hz including 5060 Hz.
C. Roles and Responsibilities of Team Members
We decided that the amplifier stage would be critical
and would require two members, while the DC zeroing and
chopper design would require one member. The chopper
and amplifier design would include testing for power consumption, noise considerations, and meeting the specs. as
discussed. The amplifiers would further need more investigation on the stability consideration, number of stages,
layout, etc.
B. Narayan: Team Leader, Design of Chopper and DC
Servo Loop
H. Sane: Design of Amplifier
J. Zaveri: Design of Amplifier

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1

A Low-Power CMOS Chopper Amplifier for EEG

HE demand for technologies that help neuroscientists

Fig. 1. Frequency and Amplitude of Biopotential Signals

Some techniques that can be employed to remove the

stabilized amplifiers that combined the chopper amplifier

Fig. 2. Chopper Stabilization Amplifiers [4]

first stage. In order to meet the stability requirements,

B. Chopping and Filtering Technique

Fig. 5. Block diagram of the system.

Fig. 4. Proposed method for filtering technique at the output stage

After demodulation, the system normally consists of a

Fig. 6. Design specifications.

Fig. 7. Comparison chart [4]

References for this chart:

B. International Federation of Clinical Neurophysiology

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