TDA7449

TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 2 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE, AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7449 is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in TV systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.

DIP20

ORDERING NUMBER: TDA7449

The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.

BLOCK DIAGRAM
MUXOUTL

TREBLE(L)

10

L-IN1

16

BIN(L) BOUT(L)
15

14
RB

100K

L-IN2

9
100K

R-IN1

VOLUME

SPKR ATT
LEFT

BASS

I CBUS DECODER + LATCHES

20
18

100K

R-IN2

6
100K

19

0/30dB
2dB STEP

TREBLE

VOLUME

TREBLE

SPKR ATT
RIGHT

BASS

LOUT

SCL
SDA
DIG_GND

ROUT

VREF
2
SUPPLY

INPUT MULTIPLEXER
+ GAIN

RB
11
MUXOUTR

April 1999

17
TREBLE(R)

12

13

BIN(R) BOUT(R)

VS
AGND

1
CREF

D98AU847A

1/17

TDA7449
ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Value
10.5

Tamb

Operating Ambient Temperature

-10 to 85

Tstg

Storage Temperature Range

-55 to 150

VS

Operating Supply Voltage

Unit

PIN CONNECTION

CREF

20

SDA

VS

19

SCL

PGND

18

DIG_GND

ROUT

17

TREBLE(R)

LOUT

16

TREBLE(L)

R_IN2

15

BIN(L)

R_IN1

14

BOUT(L)

L_IN1

13

BOUT(R)

L_IN2

12

BIN(R)

10

11

MUXOUT(R)

MUXOUT(L)

D98AU848

THERMAL DATA
Symbol
R th j-pin

Parameter
Thermal Resistance Junction-pins

Value

Unit

150

C/W

QUICK REFERENCE DATA

Symbol

Parameter

Min.

Typ.

Max.

10.2

VS

Supply Voltage

VCL

Max. input signal handling

Total Harmonic Distortion V = 1Vrms f = 1KHz

0.01

S/N

Signal to Noise Ratio V out = 1Vrms (mode = OFF)

106

SC

Channel Separation f = 1KHz

Volume Control
Treble Control

(1dB step)
(2dB step)

0.1

%
dB

90

dB

30

dB

-47

dB
dB

-14

+14

Bass Control (2dB step)

-14

+14

dB

Balance Control

-79

dB

Mute Attenuation

2/17

V
Vrms

THD

Input Gain in (2dB step)

Unit

1dB step

100

dB

TDA7449
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K,
RG = 600, all controls flat (G = 0dB), unless otherwise specified)
Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

10.2

60

7
90

mA
dB

THD = 0.3%

100
2.5

K
Vrms

The selected input is grounded

through a 2.2 capacitor

80

100

dB

-1

0
30
2

dB
dB
dB

45
45
0.5

47
47
1

49
49
1.5

dB
dB
dB

-1.0
-1.5

0
0
0

1.0
1.5
1

dB
dB
dB

2
3

80

0
0
0.5
100

dB
mV
mV
dB

+12.0
1

+14.0
2

+16.0
3

dB
dB

18.75

25

31.25

+13.0
1

+14.0
2

+15.0
3

dB
dB

SUPPLY
VS

Supply Voltage

IS
SVR

Supply Current
Ripple Rejection

INPUT STAGE
R IN
V CL

Input Resistance
Clipping Level

SIN

Input Separation

Ginmin
Ginman
Gstep

Minimum Input Gain

Maximum Input Gain
Step Resolution

VOLUME CONTROL
C RANGE
AVMAX
ASTEP

Control Range
Max. Attenuation
Step Resolution

EA

Attenuation Set Error

ET

Tracking Error

VDC

DC Step

Amute

Mute Attenuation

AV = 0 to -24dB
AV = -24 to -47dB
AV = 0 to -24dB
AV = -24 to -47dB
adjacent attenuation steps
from 0dB to AV max

BASS CONTROL (1)

Gb
BSTEP
RB

Control Range
Step Resolution

Max. Boost/cut

Internal Feedback Resistance

TREBLE CONTROL (1)

Gt
TSTEP

Control Range
Step Resolution

Max. Boost/cut

SPEAKER ATTENUATORS
C RANGE

Control Range

SSTEP
EA

Step Resolution
Attenuation Set Error

VDC
Amute

DC Step
Mute Attenuation

76
AV = 0 to -20dB
AV = -20 to -56dB

dB

0.5
-1.5
-2

1
0
0

1.5
1.5
2

dB
dB
dB

0
100

80

mV
dB

adjacent attenuation steps

NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V doest reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.

3/17

TDA7449
ELECTRICAL CHARACTERISTICS (continued.)
Symbol

Parameter

Test Condition

Min.

Typ.

2.1
2
10

2.6

Max.

Unit

AUDIO OUTPUTS
VCLIP
RL
RO

Clipping Level
Output Load Resistance
Output Impedance

VDC

DC Voltage Level

d = 0.3%

VRMS
K
70

15

0
0
106

1
2

dB
dB
dB

40
3.8

GENERAL
ENO

Output Noise

All gains = 0dB;

BW = 20Hz to 20KHz flat

Et

Total Tracking Error

S/N

Signal to Noise Ratio

AV = 0 to -24dB
AV = -24 to -47dB
All gains 0dB; VO = 1VRMS ;

SC
d

Channel Separation Left/Right

Distortion

AV = 0; V I = 1VRMS ;

80

100
0.01

0.08

dB
%

BUS INPUT
V IL
VIH
IIN
VO

4/17

Input Low Voltage

Input High Voltage
Input Current
Output Voltage SDA
Acknowledge

1
VIN = 0.4V
IO = 1.6mA

3
-5
0.4

5
0.8

V
V
A
V

TDA7449
P.C.Board

TEST CIRCUIT

R2 2K

C9
5.6nF

150nF

J5
IN1L

C7

MUXOUTL

J3

TREBLE(L)
10

RCA

1
2

J4

3
4
5

330nF

16

C8

BIN(L)

BOUT(L)

15

14

GND
IN1L
GND
IN2L
GND

CON3

C3 0.47F
L-IN2

RB

OUT_L

100K

5
LOUT

C4 0.47F

100K

VOLUME

TREBLE

OUT_ R

SPKR ATT
LEFT

BASS

J2
RCA

0/30dB
2dB STEP

J1

3
4

IN2R
GND
IN1R
GND

R-IN2

18

DIG_GND

19

SCL

20

SDA

VOLUME

TREBLE

BASS

SPKR ATT
RIGHT

C2 0.47F

4
CON4

1
2
3

J6

ROUT

100K

SUPPLY

MOUTL
GND

RB
11

MUXOUTR

17
TREBLE(R)

MOUTR

13
BOUT(R)

C5

C13
100nF

R3 30

C12
22F

AGND

VS

12
BIN(R)

J10

INPUT MULTIPLEXER
+ GAIN

CON4
100K

VREF

CON

J5

JP1
JUMPER

C1 0.47F
R-IN1

I2CBUS DECODER + LATCHES

CON4
+9 V

J9

OUT_L
L-IN1

IN1R

J8

OUT_R

+V8

+9V

GND

J7

CON2

CREF

C6

GND
C10
5.6nF

150nF
R1

330nF
2K

C11
10F
D98AU849A

5/17

TDA7449
APPLICATION SUGGESTIONS
The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7449 audioprocessor provides 2 bands
tones control.

ternal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows:
FC =

AV =

Bass, Stages

Ri, R2, C1, C2

R2 C2 + R2 C1 + Ri C1

Q=

The Bass cell has an internal resistor Ri = 25K

typical.
Several filter types can be implemented, connecting external components to the Bass IN and OUT
pins.
The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 inFigure 1.

Ri internal
IN

OUT

C1

C2
R2
D95AU313

Figure 2: THD vs. frequency

6/17

R2 C1 + R2 C2

Ri R2 + C1 C2
R2 C1 + R2 C2

Viceversa, once Fc, Av, and Ri internal value are

fixed, the external components values will be:
C1 =

AV 1
2 Ri Q

R2 =

C2 =

Q2 C1
(AV 1) Q2

AV 1 Q2
2 C1 FC (AV 1) Q

Treble Stage
The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25K
typical) and an external capacitor connected between treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREF
The suggested 10F reference capacitor (CREF)
value can be reduced to 4.7F if the application
requires faster power ON.

Figure 3: THD vs. RLOAD

TDA7449
Figure 4: Channel separation vs. frequency

Figure 5: Bass response

Ri = 25k
C1 = 150nF
C2 = 330nF
R2 = 2k

Figure 6: Treble response

7/17

TDA7449
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7449 and vice versa takes place through the
2 wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS

Figure 4: Timing Diagram of I2CBUS

Figure 5: Acknowledge on the I2CBUS

8/17

knowledge bit. The MSB is transferred first.

Acknowledge
The master (P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio
processor, the P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.

TDA7449
address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)

SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7449

CHIP ADDRESS

SUBADDRESS

MSB
S

LSB
0

MSB
ACK

DATA 1 to DATA n
LSB

DATA

MSB
ACK

LSB
DATA

ACK

D96AU420

ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment

EXAMPLES
No Incremental Bus
The TDA7449 receives a start condition, the cor-

CHIP ADDRESS

SUBADDRESS

MSB
S

LSB
0

rect chip address, a subaddress with the B = 0

(no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.

MSB
ACK

DATA
LSB

MSB

0 D3 D2 D1 D0 ACK

LSB
DATA

ACK

D96AU421

Incremental Bus
The TDA7449 receive a start conditions, the correct chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas

CHIP ADDRESS

SUBADDRESS

MSB
S

LSB
0

SUBADDRESS from XXX1000 to XXX1111 of

DATA are ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.

MSB
ACK

DATA 1 to DATA n
LSB

1 D3 D2 D1 D0 ACK

MSB

LSB
DATA

ACK

D96AU422

9/17

TDA7449
POWER ON RESET CONDITION
INPUT SELECTION

IN2

INPUT GAIN

28dB

VOLUME

MUTE

BASS

2dB

TREBLE

2dB

SPEAKER

MUTE

DATA BYTES
Address = 88 HEX (ADDR:OPEN).
FUNCTION SELECTION: First byte (subaddress)
MSB

LSB

SUBADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

INPUT SELECT

INPUT GAIN

VOLUME

NOT ALLOWED

BASS

TREBLE

SPEAKER ATTENUATE R

SPEAKER ATTENUATE L

B = 1: INCREMENTAL BUS ACTIVE

B = 0: NO INCREMENTAL BUS
X = DONT CARE

INPUT SELECTION
MSB

LSB

INPUT MULTIPLEXER

D7

D6

D5

D4

D3

D2

D1

D0

NOT ALLOWED

NOT ALLOWED

IN2

IN1

10/17

TDA7449
DATA BYTES (continued)
INPUT GAIN SELECTION
MSB
D7

D6

D5

D4

LSB

INPUT GAIN

D3

D2

D1

D0

2dB STEPS

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

18dB

20dB

22dB

24dB

26dB

28dB

30dB

LSB

VOLUME
1dB STEPS

GAIN = 0 to 30dB

VOLUME SELECTION
MSB
D7

D6

D5

D4

D3

D2

D1

D0

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB
X

MUTE

VOLUME = 0 to 47dB/MUTE

11/17

TDA7449
DATA BYTES (continued)
BASS SELECTION
MSB
D7

D6

D5

D4

LSB

BASS

D3

D2

D1

D0

2dB STEPS

-14dB

-12dB

-10dB

-8dB

-6dB

-4dB

-2dB

0dB

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

LSB

TREBLE

D3

D2

D1

D0

2dB STEPS

-14dB

-12dB

-10dB

-8dB

-6dB

-4dB

-2dB

0dB

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

TREBLE SELECTION
MSB
D7

12/17

D6

D5

D4

TDA7449
DATA BYTES (continued)
SPEAKER ATTENUATE SELECTION
MSB
D7

D6

D5

D4

D3

LSB

SPEAKER ATTENUATION

D2

D1

D0

1dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB

-48dB

-56dB

-64dB

-72dB

MUTE

SPEAKER ATTENUATION = 0 to -79dB/MUTE

PIN: 1

PINS: 4, 5
VS

VS

VS
20K

24

ROUT
LOUT

CREF
20A

20K

D96AU430
D96AU434

13/17

TDA7449
PINS: 6,7,8,9

PINS: 10,11

VS

VS

VS

20A

20A
MUXOUT

IN

100K
GND

VREF

D96AU425

PINS: 12, 15

D96AU491

PINS: 13, 14

VS

VS
20A

20A

44K

25K

BOUT(L)

BIN(L)
BIN(R)

D98AU850

PINS: 16, 17

BOUT(R)

D96AU429

PIN: 19

VS

20A
20A

SCL

TREBLE(L)
TREBLE(R)
50K

D96AU433

D96AU424
14/17

TDA7449
PIN: 20

20A
SDA

D96AU423

15/17

TDA7449
mm

DIM.
MIN.
a1

0.254

1.39

TYP.

inch
MAX.

MIN.

TYP.

MAX.

0.010
1.65

0.055

0.065

0.45

0.018

b1

0.25

0.010

25.4

1.000

8.5

0.335

2.54

0.100

e3

22.86

0.900

7.1

0.280

3.93

0.155

OUTLINE AND
MECHANICAL DATA

3.3

0.130

DIP20
Z

16/17

1.34

0.053

TDA7449

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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17/17

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