VLSI Programming: Lecture 1

Course 2IN35 Course: Kees van Berkel Rudolf Mak Lab: [email protected] [email protected]

Kees van Berkel, Rudolf Mak Wei Tong, Hrishikesh Salunkhe

www:

http://www.win.tue.nl/~cberkel/2IN35/

Lecture 1

Introduction

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Introduction to VLSI Programming: goals

to acquire insight in the description, design, and optimization of fine-grained parallel computations; to acquire insight in the (future) capabilities of VLSI as an implementation medium of parallel computations; to acquire skills in the design of parallel computations and in their implementation on FPGAs.

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Contents

Massive parallelism is needed to exploit the huge and still increasing computational capabilities of Very Large Scale Integrated (VLSI) circuits: we focus on fine-grained parallelism (not on networks of computers); we assume that parallelism is by design (not by compilation); we draw inspiration from consumer applications, such as digital TV, 3D TV, image processing, mobile phones, etc.; we will use Field Programmable Arrays (FPGA) as finegrained abstraction of VLSI for practical implementation.
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FPGA IC on the Xilinx XUP Board

FPGA

XC2VP30
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Lab work prerequisites

Notebook Exceed (can be obtained through the software distribution of the university) Access to UNIX server Dept. W&I (can be obtained through BCF, HG floor 8) Lab work is by teams of two students. Have FPGA tools (SW) installed on your machine by Feb 28

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VLSI Programming: time table 2012

date Feb 7 class | lab 2 | 0 hours 2 | 0 hours subject (provisional) introduction, DSP representations, bounds pipelining, retiming, transposition, J-slow, unfolding no lecture (carnaval) (have FPGA tools installed) 2 | 0 hours 1 | 3 hours 2 | 2 hours 1 | 3 hours 1 | 3 hours 1 | 3 hours unfolding (cntd), look-ahead, strength reduction Introductions FPGA, Verilog, Lab (A1) systolic computation (A1) folding; FPGAs: pipelining, retiming (A2) DSP processors; FPGAs: parallelism, strength reduc. (A3) FPGAs: sample-rate conversion (A4) 2x no lecture (examinations) 1 | 3 hours 1 | 3 hours FPGAs: video scaler (A5); hand-in report A3 FPGAs: video scaler (A5 cntd) deadline final report A4, A5

Feb 14 Feb 21 Feb 28 Mar 6

Mar 13 Mar 20 Mar 27 Apr 3

Apr10,17 Apr 24 May 1

May 22

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Course grading (provisional)

Your course grade is based on:

the quality of your programs/designs your final report on the design and evaluation of these programs (guidelines will follow) a concluding discussion with you on the programs, the report and the lecture notes intermediate assignments

[30%]; [30%]; [20%]; [20%].

Credits: 5 points = based on 140 hours on your side

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Note on course literature

First half of VLSI programming course is based on:

Keshab K. Parhi. VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999. This book is recommended.

Accompanying slides can be found on: http://www.ece.umn.edu/users/parhi/slides.html http://www.win.tue.nl/~cberkel/2IN35/

Mandatory reading: Keshab K. Parhi. High-Level Algorithm and Architecture Transformations for DSP Synthesis. Journal of VLSI Signal Processing, 9, 121-143 (1995), Kluwer Academic Publishers.

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Introduction

Some inspiration from the technology side

VLSI FPGAs

Some inspiration from the application side

Machine Intellligence Bee, SKA, SETI Digital Signal Processing (Software Defined Radio)

Parhi, Chapters 1, 2
DSP Representation Methods Iteration bounds
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Some inspiration from the technology side

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Vertical cut through VLSI circuit

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Intel 4004 processor [1970]

1970 4-bit 2300 transis tors

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Intel Itanium 2 6M Processor [2004]

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Intel Itanium 2 6M Processor [2004]

Power dissipation 130 W (107 W typical) 3 Levels of Cache: 16k + 16k, 256K, 6M CMOS technology: 130nm Clock frequency1.5 GHz 7,877 pins, 95 percent of the are for power 1,322 Specint base2000 for a single processor! Next generation: 1.7GHz and 9MByte cache!

Rusu et. al [Intel], Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache, IEEE Micro April 2004, vol. 24, Issue 2, pp. 10-18.

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Moores Law

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Rule of two [Hu, 1993]

Every 2 generations of IC technology (6 years) device feature size chip size clock frequency number of i/o pins DRAM capacity logic-gate density 4 x 0.5 x 2x 2x 2x 16 x (no longer true)

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ITRS: INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS

The overall objective of the ITRS is to present industry-wide

consensus on the best current estimate of the industrys research and development needs out to a 15-year horizon.

As such, it provides a guide to the efforts of companies,

universities, governments, and other research providers/funders.

The ITRS has improved the quality of R&D investment decisions

made at all levels and has helped channel research efforts to areas that most need research breakthroughs.

Involves over 1000 technical experts, world wide. a self-fulfilling prophecy? or wishful thinking?

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ST-Ericsson confidential

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2009 ITRSMPU/high-performance ASIC Half Pitch and Gate Length Trends

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ST-Ericsson confidential

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2009 ITRS Functions/chip and chip size

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Transistor counts [M]/ Micro Processor Unit

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ST-Ericsson confidential

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FPGA, the last 10 years

1000

Memory Bandwidth Virtex-II Pro

Price: Speed: Capacity: Source: Xilinx

300x 20x

100

Capacity Speed Price

Virtex-II Pro

10 200x10x

Spartan-3
1 1x 1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 1/00 1/01 1/02 1/03 1/04

Year
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Virtex 4 FPGA: 4VSX55

500MHz clock

Flexible Logic 6,144 CLBs

multi-port RAM 320 18 kbit

Programmable 512 DSP slides

450MHz PowerPC

1Gbps Differential I/O

0.6-11.1Gbps Serial Trx

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Some inspiration from the application side

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All things grand and small [Moravec 98]

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Chess Machine Performance [Moravec 98]

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Evolution computer power/cost [Moravec 98]

brain power equivalent per $1000 of computer

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The Square Kilometer Array (SKA)

... the ultimate exploration tool ... and the ultimate software defined radio

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MPSoC -- 2010, June 30

The Square Kilometer Array (SKA)

antenna surface: 1 km2 (sensitivity 50) large physical extent (3000+ km) wide frequency range: 70 MHz 30 GHz full design by 2010; phase 1: 2017;

phase 2: 2022

1000- 1500 dishes (15m) in the central 5 km (2000-3000 total) + dense and/or sparse aperture arrays connected to a massive data processor by an optical fibre network
Software Defined Radio Astronomy computational load (on-line) 1 exa MAC power budget = 30 MW 30 pJ/MAC allall-in
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(1018 MAC/s)

References

Chip fotos:
http://www-vlsi.stanford.edu/group/chips.html

ITRS Roadmap
http://www.itrs.net/Links/2005ITRS/ExecSum2005.pdf

When will computer hardware match the human brain?

http://www.jetpress.org/volume1/moravec.htm

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BEE & Square Kilometer Array

http://bwrc.eecs.berkeley.edu/Research/BEE/ http://seti.berkeley.edu/casper/papers/BEE2_ska2004_poster.pdf http://www.skatelescope.org/
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VLSI Digital Signal Processing Systems

Parhi, Chapters 1&2

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DSP applications classes

10G 1G

Sample rate

radar HDTV radio video modems audio modems speech control

100M 10M 1M 100k 10k 1k 100 10 1

seismic modeling complexity

# instructions/sample
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Typical DSP algorithms

speech (de-)coding speech recognition speech synthesis speaker identification Hi-fi audio en/decoding noise cancellation audio equalization ambient acoustic
emulation.

sound synthesis echo cancellation modem: (de-)modulation vision image (de-)compression image composition beam cancellation spectral estimation etc.

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Typical DSP algorithms: FIR Filters

Filters reduce signal noise and enhance image or signal quality

by removing unwanted frequencies.

Finite Impulse Response (FIR) filters compute y(n) :

y (i ) = h(k ) x(i k ) = h(n) * x(n)
k =0 N 1

where
x is the input sequence y is the output sequence h is the impulse response (filter coefficients) N is the number of taps (coefficients) in the filter

Output sequence depends only on input sequence and impulse

response.
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Typical DSP algorithms: IIR Filters

Infinite Impulse Response (IIR) filters compute:

y (i) =
M 1 k =1

a(k ) y (i k ) + b(k ) x(i k )

k =0

N 1

Output sequence depends on input sequence, impulse

response,as well as previous outputs

Adaptive filters (FIR and IIR) update their coefficients to

minimize the distance between the filter output and the desired signal.

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Typical DSP Algorithms: DFT and FFT

The Discrete Fourier Transform (DFT) supports frequency domain (spectral) analysis:
2 j =e N

y (k ) = WN nk x(n)
n =0

N 1

WN

j = 1

for k = 0, 1, , N-1, where

x is the input sequence in the time domain (real or complex) y is an output sequence in the frequency domain (complex)
The Inverse Discrete Fourier Transform (IDFT) is computed as
N 1 k =0

x ( n ) = WN

nk

y (k ), for n = 0, 1, ... , n - 1

The Fast Fourier Transform (FFT) and its inverse (IFFT) provide an efficient method for computing the DFT and IDFT.

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Typical DSP Algorithms: DCT

The Discrete Cosine Transform (DCT) and its inverse IDCT are frequently used in video (de-) compression (e.g., MPEG-2):

(2n + 1)k y (k ) = e(k ) cos[ ]x(n), for k = 0, 1, ... N - 1 2N n =0

N 1

2 x ( n) = N

N 1 k =0

e(k ) cos[

(2n + 1)k ] y (n), for k = 0, 1, ... N - 1 2N

where e(k) = 1/sqrt(2) if k = 0; otherwise e(k) = 1. A N-Point, 1D-DCT requires N2 MAC operations.

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Typical DSP Algorithms: distance calcul.

Distance calculations are typically used in pattern

recognition, motion estimation, and coding.

Problem: chose the vector rk whose distance (see below) from

the input vector x is minimum.

Mean Absolute Difference (MAD)

Mean Square Error (MSE)

N 1 i =0

1 d= N

N 1 i =0

| x(i) rk (i) |
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1 d= N

[ x(i ) rk (i )]2

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Typical DSP Algorithms:Matrix Computs

Matrix computations are typically used to estimate parameters in DSP systems.

Matrix vector multiplication Matrix-matrix multiplication Matrix inversion Matrix triangulization

Matrices often have (band) structures or may be sparse.

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Computation Rates

To estimate the hardware resources required, we can use

the equation:

where

RC = RS N S

Rc is the computation rate Rs is the sampling rate Ns is the (average) number of operations per sample

For example, a 1-D FIR has NS = 2N

and a 2-D FIR has NS = 2N2.

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Computational Rates for FIR Filtering

Signal type Speech Music Frequency # taps 8 kHz 48 kHz N =128 N =256 Performance 20 MOPs 240 MOPs

Video phone 6.75 MHz TV HDTV 27 MHz 144 MHz

N*N = 81 1,090 MOPs N*N = 81 4,370 MOPs N*N = 81 23,300 MOPs

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z-k = k units delay edge labeled n = multiplication by n

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Graphical representations: typical usage

block diagram data flow graph signal flow graph LTI systems signal processing general

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Linear Systems
input x, output y: discrete system:

x(n)

results in

y(n)

linear system: x1(n) + x2(n) results in results in y1(n) + y2(n)

c1 x1(n) + c2 x2(n)

c1 y1(n) + c2 y2(n)

for arbitrary c1 and c2 Most of our examples will be linear systems

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Linear Time-Invariant Systems

input x, output y:

x(n+k) = x(n) shifted by integer k sample periods

time-invariant system x(n) =x(n+k) results in y(n) = y(n+k)

Most of our examples will be linear time-invariant systems, or LTI systems

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Commutativity of LTI systems

x(n)

LTI System A

f(n)

LTI System B

y(n)

is equivalent to

x(n)

LTI System B

g(n)

LTI System A

y(n)

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Iteration of a Synchronous Flow Graph

Each actor fires the minimum number of times to return the

graph to a particular state

Example of a
multi-rate DFG:

# firings for 1 iteration A 2 B 2 C 3

# tokens per edge for 1 iteration A 2 AB 4 BC 6 C 3

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Iteration period
Iteration period = the time required for the execution of one iteration of the SFG
a

Example:

x(n)

Let

y(n-1)

Tm = 10 = multiplication time Ta = 4 = addition time

Iteration period = Tm+Ta = 14 = minimum sample period Ts; that is: Ts Tm+Ta

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4 types of delay paths

combinational functions 3 2 1 4
1 2 3

inputs

outputs

from inputs state inputs state

to state outputs outputs state

delay elements = state

Finite state machine (FSM) representation of a DSP system

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DSP references

Keshab K. Parhi. VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999.

Richard G. Lyons. Understanding Digital Signal Processing (2nd edition). Prentice Hall 2004.

John G. Proakis and Dimitris K Manolakis. Digital Signal Processing (4th edition), Prentice Hall, 2006.

Simon Haykin. Neural Networks, a Comprehensive Foundation (2nd edition). Prentice Hall 1999.

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Computer Architecture and DSP references

Hennessy and Patterson, Computer Architecture, a Quantitative Approach. 3rd edition. Morgan Kaufmann, 2002.

Phil Lapsley, Jeff Bier, Amit Sholam, Edward Lee. DSP Processor Fundamentals, Berkeley Design Technology, Inc, 1994-199

Jennifer Eyre, Jeff Bier, The Evolution of DSP Processors, IEEE Signal Processing Magazine, 2000.

Kees van Berkel et al. Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices, EURASIP Journal on Applied Signal Processing 2005:16, 2613-2625.

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VLSI Programming: next lecture

Parhi, Chapters 2, 3

Representations of DSP algorithms Data flow graphs Loop bounds and iteration bounds Pipelining of digital filters Parallel processing Retiming techniques

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THANK YOU