CMOS Process Steps

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EE-612:

Lecture 22:
CMOS Process Steps
Mark Lundstrom
Electrical and Computer Engineering
Purdue University
West Lafayette, IN USA
Fall 2006
NCN
www.nanohub.org
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outline

1) Unit Process Operations


2) Process Variations

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unit process operations


1)

Oxidation

2)

Diffusion

3)

Ion Implantation

4)

RTA/RTP

5)

Chemical Vapor Deposition

6)

Lithography

7)

Etching

8)

Metalization

9)

Well Structures

10) Isolation
11) Source / Drain structures
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useful references
1)

J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI


Technology, Fundamentals, Practice, and Modeling, Prentice
Hall, Upper Saddle River, NJ, 2000.

2)

S.A. Campbell, The Science and Engineering of


Microelectronic Fabrication, 2nd Ed., Oxford Univ. Press, New
York, 2001.

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oxidation
Si + O 2 SiO 2 (dry)
Si+ H 2 O SiO 2 (wet)

wafers
heater

O 2 or H 2 O
+carrier gas

T = 800 - 1100 C

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fused quartz
furnace tube

oxidation and doping


C
phophorous m > 1
boron m < 1

x
CSi
m=
CSiO2
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local oxidation

Si3 N 4
SiO2

Si

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local oxidation (LOCOS)

Si3 N 4
SiO2

field
oxide

Si

'bird's beak'
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constant source diffusion


C
CS

C(x) = CS erfc x / 2 Dt

Q = C (x,t )dx = 2CS Dt


0

dopant-containing
gas (e.g. POCl3)

time

x
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Limited source diffusion


C

C (x,t ) = Q / Dt exp x / 2 Dt

CS
t=0
predep

time

x
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diffusion
Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

substitutional
D(T ) = D0 e EA / kB T

interstitialcy

interstitial

oxidation enhanced diffusion


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ion implantation
energetic ions bombard silicon wafer
magnet
acceleration
wafer

r r
F = Q B

deflection
I

ion source
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ion implantation

Si
RP (E)
RP (E)

N (x ) = N p exp x Rp

2Rp 2 Q = 2 N p Rp

implant damage (anneal)


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ion implantation (ii)

Projected range (m)

1.0

As
0.1

0.01
10

100

1000

Acceleration energy (keV)


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channeling

C (x )
RP
tilted 3 deg

RP

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rapid thermal annealing

lamps

reflector

thermal budget

Dt
quartz window
wafer

gas inlet
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chemical vapor deposition


reaction chamber

gas inlet

Dt

wafer

susceptor

gas exhaust

2SiH 4 + 4NH 3 Si 3N 4 + 12H 2

silicon nitride

SiH 4 Si+2H 2

poly silicon

SiH 4 +O 2 SiO 2 +2H 2

silicon dioxide

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plasma CVD / etching


RF power in

gas inlet

heater

wafer
gas exhaust

lower temperature reduces


thermal budget Dt
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lithography
optical source
wavelength,
lens
shutter

contact
or
proximity

mask
resist
wafer

expose, develop, etch


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projection printing

UV source

lens 1

mask

lens 2

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wafer

20

registration errors

EE

E EE EE EE EE

misalignment

run out

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phase shift lithography


conventional mask

phase shift mask

electric field at mask


electric field at mask

intensity at wafer

intensity at wafer
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pattern transfer
negative resist
(less soluble after exposure)

wafer

wafer

positive resist
(more soluble after exposure)

resist:
optically sensitive polymer which,
when exposed to UV changes its
solubility in specific chemicals
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wafer

23

etching
wet chemical etching
(isotropic)

dry etching (plasma or reactive ion


etching - RIE)
(anisotropic)

wafer

wafer

undercut
chemicals react with
underlying material,
but not resist

ionized gases react


with underlying
material, but not
resist
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pattern transfer (ii)


mask

L Drawn

chrome
lithography
bias
resist

etch
bias

LGate (physical)
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metalization

Tungsten (W) plugs


for first layer
metal dep
CMP

www.itrs.net
2005 Edition

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outline

1) Unit Process Operations


2) Process Variations

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discrete doping effects

V = W L xj

N+

N+

example:
L=
50 nm
W = 100 nm
25 nm
xj =
NA = 1018 cm-3
NTOT = 125

P (NA cm-3)

Number of dopants in the critical volume is a statistical quantity


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discrete doping effects (ii)


source

drain

Effects:
1) VT (10s of mV)
2) lower avg. VT (10s of mV)
3) asymmetry in ID

3D transport leads to inhomogeneous conduction


(see Wong and Taur, IEDM, 1993, p. 705)
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discrete doping effects (iii)

35 nm
MOSFET

AFM measurements, Fujitsu

(simulations from A. Asenov group,


Univ. of Glasgow)

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statistical variability
Line edge roughness
discrete
dopants

From A. Asenov, Univ. of Glasgow


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variability is becoming a major issue

G. Declerck, Keynote talk, VLSI Technol. Symp. 2005


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outline

1) Unit Process Operations


2) Process Variations

For a basic, CMOS process flow for an STI


(shallow trench isolation process), see:
http://www.rit.edu/~lffeee/AdvCmos2003.pdf
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CMOS process flow


For a basic, CMOS process flow for an STI
(shallow trench isolation process), see:
http://www.rit.edu/~lffeee/AdvCmos2003.pdf

The author is indebted to Dr. Lynn Fuller of Rochester


Institute of Technology for making these materials
available. What follows is a condensed version of a
more complete presentation by Dr. Fuller. I regret any
errors that I may have introduced by shortening these
materials.
-Mark Lundstrom 10/19/06
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