CMOS Process Steps
CMOS Process Steps
CMOS Process Steps
Lecture 22:
CMOS Process Steps
Mark Lundstrom
Electrical and Computer Engineering
Purdue University
West Lafayette, IN USA
Fall 2006
NCN
www.nanohub.org
Lundstrom EE-612 F06
outline
Oxidation
2)
Diffusion
3)
Ion Implantation
4)
RTA/RTP
5)
6)
Lithography
7)
Etching
8)
Metalization
9)
Well Structures
10) Isolation
11) Source / Drain structures
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useful references
1)
2)
oxidation
Si + O 2 SiO 2 (dry)
Si+ H 2 O SiO 2 (wet)
wafers
heater
O 2 or H 2 O
+carrier gas
T = 800 - 1100 C
fused quartz
furnace tube
x
CSi
m=
CSiO2
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local oxidation
Si3 N 4
SiO2
Si
Si3 N 4
SiO2
field
oxide
Si
'bird's beak'
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C(x) = CS erfc x / 2 Dt
dopant-containing
gas (e.g. POCl3)
time
x
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C (x,t ) = Q / Dt exp x / 2 Dt
CS
t=0
predep
time
x
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10
diffusion
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
substitutional
D(T ) = D0 e EA / kB T
interstitialcy
interstitial
11
ion implantation
energetic ions bombard silicon wafer
magnet
acceleration
wafer
r r
F = Q B
deflection
I
ion source
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12
ion implantation
Si
RP (E)
RP (E)
N (x ) = N p exp x Rp
2Rp 2 Q = 2 N p Rp
13
1.0
As
0.1
0.01
10
100
1000
14
channeling
C (x )
RP
tilted 3 deg
RP
15
lamps
reflector
thermal budget
Dt
quartz window
wafer
gas inlet
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gas inlet
Dt
wafer
susceptor
gas exhaust
silicon nitride
SiH 4 Si+2H 2
poly silicon
silicon dioxide
17
gas inlet
heater
wafer
gas exhaust
18
lithography
optical source
wavelength,
lens
shutter
contact
or
proximity
mask
resist
wafer
19
projection printing
UV source
lens 1
mask
lens 2
wafer
20
registration errors
EE
E EE EE EE EE
misalignment
run out
21
intensity at wafer
intensity at wafer
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22
pattern transfer
negative resist
(less soluble after exposure)
wafer
wafer
positive resist
(more soluble after exposure)
resist:
optically sensitive polymer which,
when exposed to UV changes its
solubility in specific chemicals
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wafer
23
etching
wet chemical etching
(isotropic)
wafer
wafer
undercut
chemicals react with
underlying material,
but not resist
24
L Drawn
chrome
lithography
bias
resist
etch
bias
LGate (physical)
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25
metalization
www.itrs.net
2005 Edition
26
outline
27
V = W L xj
N+
N+
example:
L=
50 nm
W = 100 nm
25 nm
xj =
NA = 1018 cm-3
NTOT = 125
P (NA cm-3)
28
drain
Effects:
1) VT (10s of mV)
2) lower avg. VT (10s of mV)
3) asymmetry in ID
29
35 nm
MOSFET
30
statistical variability
Line edge roughness
discrete
dopants
31
32
outline
33
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