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    Electrical Engineering Hardware Questions

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    cherry987
    The document contains 6 electrical engineering hardware questions related to logic gates, capacitors in parallel, timing analysis, voltage drops on transmission lines, characteristic impedance of transmission lines, and troubleshooting a miscounting counter.

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    © All Rights Reserved
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    Electrical Engineering Hardware Questions

    Uploaded by

    cherry987
    48 views6 pages
    The document contains 6 electrical engineering hardware questions related to logic gates, capacitors in parallel, timing analysis, voltage drops on transmission lines, characteristic impedance of transmission lines, and troubleshooting a miscounting counter.

    Original Description:

    interview questions hardware

    Original Title

    Hardware Questions

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    The document contains 6 electrical engineering hardware questions related to logic gates, capacitors in parallel, timing analysis, voltage drops on transmission lines, characteristic impedance of transmission lines, and troubleshooting a miscounting counter.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    48 views6 pages

    Electrical Engineering Hardware Questions

    Uploaded by

    cherry987
    The document contains 6 electrical engineering hardware questions related to logic gates, capacitors in parallel, timing analysis, voltage drops on transmission lines, characteristic impedance of transmission lines, and troubleshooting a miscounting counter.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    You are on page 1of 6

    Electrical Engineering Hardware Questions

    Question 1 (5-minutes): Design the black box using simple gates to achieve the
    following:

    Out = In,
    Hi-Z,

    when Tri = 0
    when Tri = 1

    Question 2 (3-5 minutes):

    Two capacitors are connected in parallel through a switch. C1 = 1uF, C2 =


    0.25uF. Initially switch is open and C1 is charged to 10V. What is the voltage
    when switch is closed? Assume no loss in the wires and capacitors.

    Question 3 (10 minutes):

    Given that, tc-q = 200ps, tflight = 500ps, tsu = 150ps, tskew = 50ps, tclk = 2ns.
    What is (tlogic)max?
    If (tlogic) = 1.5ns then what can I change to meet timing? (Pipeline the logic,
    reduce frequency etc.)

    Given that, thold = 500ps, tc-q = 200ps, tflight = 50ps, tsu = 150ps, tskew = 50ps,
    tclk = 2ns. What is (tlogic)min?
    If (tlogic) = 200ps, what should I change to meet timing? Should I increase
    or decrease my frequency to meet timing?

    Question 4 (10 minutes):


    Consider the following board where the FPGA 3.3v power pins are fed from the
    banana jack through a 10 mil trace.

    What voltage do you expect to see at the FPGA pins?

    How can I reduce the voltage drop on the trace so that I see very close to
    3.3V at the FPGA pins?

    What about GND trace? Is it okay to have large resistance on the current
    return path?

    Question 5 (10-minutes):
    What is characteristic impedance of a transmission line?
    What happens if at any point in the transmission line the instantaneous
    impedance is not equal to the characteristic impedance of the line?
    Given that ZT is the termination impedance, Zc is the characteristic
    impedance, Vi is the source signal voltage and Vr is the reflected signal
    voltage, can you write an equation for Vr related to the other parameters?
    Advanced Question 2: (If the candidate is able to answer all three of the above)
    Assume an ideal condition where there is zero attenuation along the transmission
    line. Given Vsource waveform, draw near-end and far-end waveforms for the
    following cases:

    Case 1: Zs = 0 ohm and Zp =

    (open)

    What happens when you consider attenuation in the transmission line?

    Case 2: Zs = 50 ohm and Zp =

    (open). Draw similar waveforms.

    Question 6 (10-minutes):
    I am a customer using a PLD in my application. Programmed into the PLD is a
    16-bit counter. The outputs of the 16-bit counter feed another chip on my board.
    On my board, I notice that the counter sometimes miscounts. What should I do?
    Should I send the PLD back to you?
    Notes: This question is open-ended at this time and is intended to see the
    candidates trouble shooting skills.
    Additional information if the candidate asks for it or you want to open up the
    problem a little bit more:

    The counter counts fine until 4095. Then instead of 4096 it sees 4160.
    Then from 4097 onwards it is fine until 8191. Then instead of 8192 it sees
    8200

    Expected
    Decimal
    4096
    8192
    16384
    32768

    Expected
    Binary
    1000000000000
    10000000000000
    100000000000000
    1000000000000000

    Encountered
    Decimal
    4160
    8200
    16640
    32900

    Encountered Binary
    1000001000000
    10000000001000
    100000100000000
    1000000010000100

    Discussion:
    The previous value before error happens at 4096 is 4095 (1111111111111)
    The previous value before error happens at 8192 is 8191 (11111111111111)
    So on .
    Error happens when all bits switch from 1s to 0s triggering a large amount of
    instantaneous current requirement. If the PDS is not designed properly, then it
    may not be able to provide the required current causing errors.
    Also, due to the large instantaneous current flow between Vcc and GND, there is
    difference in the chip and the board GND voltage (L*di/dt) causing ground
    bounce. Due to different reference (GND) voltage between the counter PLD chip
    and the receiving chip caused by Ground Bounce, a 0 sent by the counter chip
    may be interpreted as a 1 by the receiving chip. Hence, the errors observed
    above.
    Okay, so what should I do now?
    Improve decoupling
    Reduce the number of simultaneously switching outputs (change design to
    GRAY code counter)

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