November 1998

FDS6575
Single P-Channel, Logic Level, PowerTrenchTM MOSFET

General Description Features

This P-Channel Logic Level MOSFET is produced -10 A, -20 V. RDS(ON) = 0.013 Ω @ VGS = -4.5 V,
using Fairchild Semiconductor's advanced PowerTrench RDS(ON) = 0.017 Ω @ VGS = -2.5 V.
process that has been especially tailored to minimize
the on-state resistance and yet maintain low gate charge Low gate charge (50nC typical).
for superior switching performance. High performance trench technology for extremely low
These devices are well suited for notebook computer RDS(ON).
applications: load switching and power management,
High power and current handling capability.
battery charging circuits, and DC/DC conversion.

SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16

D 5 4
D
S
D
D
FD 75 6 3
65
7 2
G
S
SO-8 pin 1 S 8 1
S

Absolute Maximum Ratings TA = 25oC unless otherwise noted

Symbol Parameter FDS6575 Units
VDSS Drain-Source Voltage -20 V
VGSS Gate-Source Voltage ±8 V
ID Drain Current - Continuous (Note 1a) -10 A
- Pulsed -50
PD Power Dissipation for Single Operation (Note 1a) 2.5 W
(Note 1b) 1.2
(Note 1c) 1
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W

© 1998 Fairchild Semiconductor Corporation FDS6575 Rev.C1

Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V

∆BVDSS/∆TJ
o
Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 C -19 mV/oC
IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 µA
TJ = 55°C -10 µA
IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS = 0 V -100 nA
ON CHARACTERISTICS (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.4 -0.8 -1.5 V
∆VGS(th)/∆TJ Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 3 mV/oC
RDS(ON) Static Drain-Source On-Resistance VGS = -4.5 V, ID = -10 A 0.01 0.013 Ω
TJ =125°C 0.015 0.02
VGS = -2.5 V, ID = -9 A 0.013 0.017
ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V -50 A
gFS Forward Transconductance VDS = -4.5 V, ID = -11 A 45 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = -15 V, VGS = 0 V, 4800 pF
f = 1.0 MHz
Coss Output Capacitance 1100 pF
Crss Reverse Transfer Capacitance 460 pF
SWITCHING CHARACTERISTICS (Note 2)

tD(on) Turn - On Delay Time VDS = -10 V, ID = -1 A 30 50 ns

tr Turn - On Rise Time VGEN = -4.5 V, RGEN = 6 Ω 20 35 ns
tD(off) Turn - Off Delay Time 175 250 ns
tf Turn - Off Fall Time 80 110 ns
Qg Total Gate Charge VDS = -15 V, ID = -10 A, 50 70 nC
Qgs Gate-Source Charge VGS = -4.5 V 8 nC
Qgd Gate-Drain Charge 11 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS Maximum Continuous Drain-Source Diode Forward Current -2.1 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A (Note 2) -0.7 -1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.

a. 50OC/W on a 1 in2 pad b. 105OC/W on a 0.04 in2 c. 125OC/W on a 0.006 in2 pad
of 2oz copper. pad of 2oz copper. of 2oz copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

FDS6575 Rev.C1
 Typical Electrical Characteristics
50 2.5
VGS = -4.5V
- I D , DRAIN-SOURCE CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE
-3.0V
40 -2.5V

R DS(ON), NORMALIZED
-2.0V 2
V GS = -2.0V
30

1.5
-2.5 V
20 -3.0 V
-3.5 V
1 -4.5V
10
-1.5V

0 0.5
0 0.6 1.2 1.8 2.4 3 0 10 20 30 40 50
- V DS , DRAIN-SOURCE VOLTAGE (V) - I D , DRAIN CURRENT (A)

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Dain Current and Gate Voltage.

1.6 0.05
I D = -5.0A
DRAIN-SOURCE ON-RESISTANCE

I D= -10A

R DS(ON), ON-RESISTANCE (OHM)

VGS = -4.5V
1.4 0.04
R DS(ON), NORMALIZED

1.2 0.03

1 0.02
T J = 125° C

0.8 0.01
25° C

0.6 0
-50 -25 0 25 50 75 100 125 150 1 2 3 4 5
TJ , JUNCTION TEMPERATURE (° C) - VGS , GATE TO SOURCE VOLTAGE (V)

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with

Temperature. Gate-to-Source Voltage.

50 50
VDS = -5.0V
- I S , REVERSE DRAIN CURRENT (A)

TJ = -55° C VGS = 0V
25° C 10
- I D, DRAIN CURRENT (A)

40
125° C
T J = 125° C
30 1
25° C

0.1
-55° C
20

10 0.01

0 0.001
0.5 1 1.5 2 2.5 0 0.3 0.6 0.9 1.2
- VGS , GATE TO SOURCE VOLTAGE (V) - VSD , BODY DIODE FORWARD VOLTAGE (V)

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage

Variation with Source Current
and Temperature.

FDS6575 Rev.C1
Typical Electrical Characteristics (continued)

5 8000
- V GS , GATE-SOURCE VOLTAGE (V)

ID = -10A C iss
V DS = -5V 4000
4
-10V

CAPACITANCE (pF)
-15V
2000
3

1000 Coss
2

400 f = 1 MHz C rss

1
V GS = 0 V

0 200
0 12 24 36 48 60 0.1 0.2 0.5 1 2 5 10 20
Q g , GATE CHARGE (nC) - V DS , DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

200 50

10 SINGLE PULSE
50 I T 0u
LIM s
- I D , DRAIN CURRENT (A)

N) 40 RθJA =125°C/W
S(O
1m
RD s TA = 25°C
10 10m
POWER (W)

s 30
10
2 0m
s
1s
0.5 10 20
VGS =-4.5V s
DC
SINGLE PULSE
0.1
RθJA =125°C/W 10
TA = 25°C

0.01 0
0.05 0.1 0.3 1 3 10 30 50 0.001 0.01 0.1 1 10 100 300
- VDS , DRAIN-SOURCE VOLTAGE (V) SINGLE PULSE TIME (SEC)

Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power
Dissipation.

1
TRANSIENT THERMAL RESISTANCE

0.5 D = 0.5
r(t), NORMALIZED EFFECTIVE

0.2 R θJA (t) = r(t) * R θJA

0.2
R θJA = 125°C/W
0.1 0.1

0.05 0.05
P(pk)
0.02
0.02 0.01 t1
0.01 Single Pulse
t2

0.005 TJ - TA = P * RθJA (t)

Duty Cycle, D = t1 /t2
0.002
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
t1 , TIME (sec)

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.

FDS6575 Rev.C1
SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging
Configuration: Figure 1.0

Packaging Description:
EL ECT ROST AT IC
SOIC-8 parts are shipped in tape. The carrier tape is
SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
made from a dissipative (carbon filled) polycarbonate
TNR D ATE

PT NUMB ER
resin. The cover tape is a multilayer film (Heat Activated
PEEL STREN GTH MIN ___ __ ____ __ ___gms

MAX ___ ___ ___ ___ _ gms

Adhesive in nature) primarily composed of polyester film,
Antistatic Cover Tape adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
ESD Label 2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
Static Dissipative comes in different sizes depending on the number of parts
Embossed Carrier Tape shipped.

F63TNR
Label

Customized F852
NDS
Label 9959

9959
NDS
F852
9959
NDS
F852

9959
NDS
F852
9959
NDS
F852
SOIC (8lds) Packaging Information Pin 1
Standard
Packaging Option L86Z F011 D84Z
(no flow code)
Packaging type TNR Rail/Tube TNR TNR SOIC-8 Unit Orientation
Qty per Reel/Tube/Bag 2,500 95 4,000 500
Reel Size 13" Dia - 13" Dia 7" Dia
Box Dimension (mm) 343x64x343 530x130x83 343x64x343 184x187x47
Max qty per Box 5,000 30,000 8,000 1,000
Weight per unit (gm) 0.0774 0.0774 0.0774 0.0774
Weight per Reel (kg) 0.6060 - 0.9696 0.1182

Note/Comments

343mm x 342mm x 64mm

Standard Intermediate box

ESD Label
F63TNR Label sample
F63TNLabel
F63TN Label
LOT: CBVK741B019 QTY: 2500

FSID: FDS9953A SPEC:

ESD Label
D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:
N/F: F (F63TNR)3

SOIC(8lds) Tape Leader and Trailer

Configuration: Figure 2.0

Carrier Tape

Cover Tape
Components
Trailer Tape Leader Tape
640mm minimum or 1680mm minimum or
80 empty pockets 210 empty pockets

July 1999, Rev. B

 SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape

Configuration: Figure 3.0 P0 D0
T
E1

K0 W
E2
Wc B0

Tc
A0 P1 D1

User Direction of Feed

Dimensions are in millimeter

Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

0.450
SOIC(8lds) 6.50 5.30 12.0 1.55 1.60 1.75 10.25 5.50 8.0 4.0 2.1
+/-
9.2 0.06
(12mm) +/-0.10 +/-0.10 +/-0.3 +/-0.05 +/-0.10 +/-0.10 min +/-0.05 +/-0.1 +/-0.1 +/-0.10 +/-0.3 +/-0.02
0.150

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C). 0.5mm
20 deg maximum maximum

Typical
component
cavity 0.5mm
B0 center line maximum

20 deg maximum component rotation

Typical
Sketch A (Side or Front Sectional View) component Sketch C (Top View)
A0 center line
Component Rotation Component lateral movement
Sketch B (Top View)
SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation

W1 Measured at Hub

Dim A
Max

Dim A See detail AA

max Dim N

7" Diameter Option

B Min

Dim C

See detail AA
Dim D
W3 min

13" Diameter Option W2 max Measured at Hub

DETAIL AA

Dimensions are in inches and millimeters

Reel
Tape Size Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
Option
7.00 0.059 512 +0.020/-0.008 0.795 2.165 0.488 +0.078/-0.000 0.724 0.469 – 0.606
12mm 7" Dia
177.8 1.5 13 +0.5/-0.2 20.2 55 12.4 +2/0 18.4 11.9 – 15.4

13.00 0.059 512 +0.020/-0.008 0.795 7.00 0.488 +0.078/-0.000 0.724 0.469 – 0.606
12mm 13" Dia
330 1.5 13 +0.5/-0.2 20.2 178 12.4 +2/0 18.4 11.9 – 15.4

 1998 Fairchild Semiconductor Corporation July 1999, Rev. B

 SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1:1

Scale 1:1 on letter size paper

Dimensions shown below are in:
inches [millimeters]

Part Weight per unit (gram): 0.0774

September 1998, Rev. A

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™ ISOPLANAR™ TinyLogic™

CoolFET™ MICROWIRE™ UHC™
CROSSVOLT™ POP™ VCX™
E2CMOSTM PowerTrench™
FACT™ QFET™
FACT Quiet Series™ QS™
FAST® Quiet Series™
FASTr™ SuperSOT™-3
GTO™ SuperSOT™-6
HiSeC™ SuperSOT™-8
DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.