PIC Microcontroller and

E b dd d S
Embedded
Systems
t
Muhammad Ali Mazidi, Rolin McKinlay and Danny Causey

E g Husam
Eng.
m Alzaq
q
The Islamic Uni. Of Gaza

The PIC uCs

1-1

Chapter
p
2:
PIC Architecture And
A
Assembly
bl L
Language
Programming.
Programming
The WREG Register
The PIC File Register
Using instruction with the default

access bank

PIC Microcontroller
and
d Embedded
E b dd d S
Systems
Muhammad Ali Mazidi,
Rolin McKinlay and
D
Danny
Causey
C s , February
F b
2007.

The PIC uCs

1-2

Outline
PIC
P Status Register
PIC data format and directive
Intro. To PIC assembly language
Assembling and linking a PIC program
The Program Counter and program ROM

space in the PIC

RISC Architecture in the PIC
Viewing Register and memory with MPLAB
simulator
The PIC uCs

1-3

Objective
Examine
E
the
h data
d
RAM fileReg
fl
of
f the
h PIC
P uC
Manipulate
p
data using
g the WREG & MOVE
Perform simple operations such ADD and

fileReg using and access bank in the PIC uC

Explain the purpose of the status reg
Discuss data RAM memory space allocation in
the PIC uC
List
Li SFR
SFRs of
f the
h PIC uC
C
Describe PIC data types and directives
The PIC uCs

1-4

The WREG Register

Many
M
registers
i
f
for arithmetic
i h
i and
d llogic
i

operation.
The WREG (WORking Register) Register is
one of the most widely
y used registers
g
of
the PIC
8-bit

register
g
any
y data larger
g than 8 bits
must be broken into 8-bits chunks before it is
processed.
There is only one .

D7 D6 D5 D4 D3 D2 D1 D0

The PIC uCs

3-5

MOVLW
Moves 8-bit
b d
data into WREG
EG
MOVLW k; move literal value k into WREG
Example
MOVLW 25H
MOVLW A5H
Is the following code correct?
MOVLW 9H
MOVLW A23H
The PIC uCs

1-6

ADDLW
ADDLW
DDLW k
k; Add
dd literal
li
l value
l k to WREG (k +WREG)
WREG)
Example:
MOVLW 12H
ADDLW 16H
ADDKW 11H
ADDLW 43H

The PIC uCs

;
;
;
;

1-7

Figure 2-1. PIC WREG and ALU Using Literal

Value

The PIC uCs

1-8

The PIC File Register

It is the
h data
d
memory.
Read/Write Static RAM
Used for data storage, scratch pad and
registers for internal use and function
8-bit width

PIC File Register

General Purpose
RAM

GP RAM

The PIC uCs

Special Function
Registers

EEPROM

1-9

Register File Concept

Data Memory
(Register File)
w

07h

ALU

08h

Data Bus
D

09h

0Ah
0Bh
0Ch
0Dh
0Eh

0Fh
10h

WREG

Decoded Instruction
from Program Memory:

Opcode

Arithmetic/Logic Function to
be Performed

The
The PIC
PICuCs
uCs

d a

Result
Destination

Address
Address of Second Source
Operand

Register File
Concept: All of data
memory is part of
the register file, so
any location in data
memory may be
operated on
directly
All peripherals are
mapped into data
memory as a series
of registers
Orthogonal
g
Instruction Set:
ALL instructions
can operate
p
on ANY
data memory
location
1-10

PIC18F Programming Model

The PIC uCs

1-11

Special Function Registers

dedicated
d d
d to specific
f f
functions such
h as

ALU status, timers, serial communication,

I/O
/ ports, ADC,
D
The function of each SFR is fixed by
y the
CPU designer at the time of design
it

is used for control of the microcontroller or

peripheral

8-bit registers
g
Their numbers varies from one chip to

another
another.

The PIC uCs

1-12

General Purpose RAM

Group
G
of
f RAM locations
l
8-bit registers
g
Larger than SFR
Difficult to manage them by using Assembly
language
Easier to handle them by
y C Compiler.
p
The microchip website provides the data

RAM size, which is the same as GPR size.

The PIC uCs

1-13

File Register Size

FileRegister
PIC12F508
PIC16F84
PIC18F1220
PIC18F452
PIC18F2220
PIC18F458
PIC18F8722
PIC18F4550
The PIC uCs

(Bytes)
32
80
512
1792
768
1792
4096
2048

SFR
(Bytes)
7
12
256
256
256
256
158
160

GPR
(Bytes)
25
68
256
1536
512
1536
3938
1888
1-14

Figure 2-2. File Registers of

PIC12, PIC16, and PIC18

The PIC uCs

1-15

The PIC uCs

1-16

GPRAM VS.
VS EEPROM
An add-on
dd
memory
Can be zero size

The PIC uCs

1-17

File Register and access bank in

the PIC18
The
h PIC18
P 1 Family
F
l can have
h
a max. of
f 4096
40 6

Bytes.
The File Register
has

addresses of 000- FFFH

divided into 256-byte banks
Max. 16 banks (How?)
(
)
At least there is one bank
Known as default access bank.
bank
Bank switching is a method used to access

all the banks

The PIC uCs

1-18

Figure 2-3. File Register for PIC18

Family

The PIC uCs

1-19

Access bank in the PIC18

It is 256-Byte
6 B
b
bank.
k
Divided into equal
q
two discontinuous

sections (each 128 B).

GP

RAM, from 0 to 7FH

SFR, from F80H to FFFH

The PIC uCs

1-20

Figure 2-4. SFRs of the PIC18 Family.

The PIC uCs

1-21

Using instruction with the

default access bank
We need
d instruction to access other
h

locations in the file register for ALU and

other
h operations.
MOVWF
COMF
DECF
MOVF
MOVFF

The PIC uCs

1-22

MOVWF instruction
F indicates
d
for
f a file
f l register

MOVWF Address
It tells the CPU to copy the source
register, WREG, to a destination in the file
register.
A

location in the SPR

A location in GP RAM

WREG
The PIC uCs

1-23

Example 2-1

The PIC uCs

MOVLW 99H
MOVWF 12H
MOVLW 85H
MOVWF 13H
MOVLW 3FH
MOVWF 14H
MOVLW 63H
MOVWF 15H
MOVLW 12H
MOVWF 16H

WRFG
99
85
3F
63
12

Address Data
Add
D t
012H
013H
014H
015H
016H
Address
012H
013H
014H
015H
016H

Data
99
85
3F
63
12
1-24

Note
We cannot move literal
l
l values
l
directly
d
l into

the general purpose RAM location in the

P 18 They
PIC18.
h must be
b moved
d there
h
via
WREG.

The PIC uCs

1-25

ADDWF
Adds
dd together
h the
h content of
f WREG
EG and
da

file register location

ADDWF File Reg. Address, D
The result will be placed in either the
WREG or in the file register location
D

indicates the destination bit

If D=0 or (D=w)
The result will be placed in the WREG
If D=1 or (D=f)
The
Th result
l will
ill be
b placed
l
d in
i the
h file
fil register
i
The PIC uCs

1-26

Example 2-2
State the
h content of
f file
f l register location
l

and WREG after the following program

MOVLW 0
Address
Address
Data
Address Data
Data
0
012H
012H
88

MOVWF 12H
66
012H 22
44
0
013H
013H
013H

MOVLW 22H
22
014H
014H
014H
015H
015H

ADDWF 12H,
12H F
015H
016H
016H
016H

ADDWF 12H, F

ADDWF 12H, F

ADDWF
DDWF 12H,
H, F
The PIC uCs

1-27

Example 2-3
State the
h content of
f file
f l register location
l

and WREG after the following program

MOVLW 0
Address
0

MOVWF 12H
012H
013H

MOVLW 22H
22
014H

ADDWF 12H,
12H F
015H
016H
44

ADDWF 12H, W
66

ADDWF 12H, W

ADDWF
DDWF 12H,
H, W
88
The PIC uCs

Data
0
22

1-28

Figure 2-5. WREG, fileReg, and

ALU in PIC18

The PIC uCs

1-29

COMF instruction
COMF
F File
F l Reg. Address,
dd
D
It tells the CPU to complement
p
the content
of fileReg and places the results in WREG
or in fileReg.
g

The PIC uCs

1-30

Example 2-4
Write a simple
l program to toggle
l the
h SFR
F

of Port B continuously forever.

Solution

MOVLW

MOVWF
B1 COMF
F

GOTO

The PIC uCs

55H
PORTB
P
PORTB,
B F
B1

55

Address Data
Address Data
F81H
55H
F81H
AAH
F82H
F82H
F83H
F83H

1-31

DECF instruction
DECF
DE
F File
F l Reg. Address,
dd
D
It tells the CPU to decrement the content
of fileReg and places the results in WREG
or in fileReg.
g
Address Data
3
012H
23
Example:
MOVLW

3
MOVWF 20H
DECF 20H,
20H F
DECF 20H, F
DECF 20H,
20H F
The PIC uCs

013H
014H
015H
016H

1-32

DECF instruction
DECF
DE
F File
F l Reg. Address,
dd
D
It tells the CPU to decrement the content
of fileReg and places the results in WREG
or in fileReg.
g
Address Data
3
012H
3
Example:
013H
2
MOVLW 3
MOVWF

20H
DECF 20H,
20H w
DECF 20H, w
DECF 20H,
20H w
The PIC uCs

1
0

014H
015H
016H

1-33

MOVF instruction
MOVF
F File
F l Reg. Address,
dd
D
It is intended to p
perform MOVFW
MOVFW

isnt existed

If D=0
D 0
Copies the content of fileReg (from I/O pin) to
WREG
If D=1
The content of the fileReg is copied to itself.
itself
(why?)
The PIC uCs

1-34

MOVF instruction
MOVF
F File
F l Reg. Address,
dd
0

WREG
The PIC uCs

1-35

Example 2-5
Write a simple
l program to get data
d
from
f

the SFRs of Port B and send it the SFRs of

P R C continuously.
PORT
l
Address Data
Data
Address
XX
Solution
AGAIN MOVF PORTB, W

The PIC uCs

MOVWF PORTC
GOTO AGAIN

F81H
F81H
F82H
F82H
F83H
F83H

XX
XX

1-36

Example 2-6
Write a simple
l program to get data
d
from
f

the SFRs of Port B Add the value 5 to it

and
d send
d it the
h SFRs
FR of
fP
PORT
R C

Solution

The PIC uCs

MOVF PORTB,W
ADDLW 05H
MOVWF PORTC

55
5A

Address
F81H
F82H
F83H

Data
55H
55H
5AH

1-37

MOVFF instruction
It copies data
d
f
from one location
l
in FileReg
Fl

to another location in FileReg.

MOVFF Source FileReg, destination FileReg

The PIC uCs

1-38

Example 2-7
Write a simple
l program to get data
d
from
f

the SFRs of Port B and send it the SFRs of

P R C continuously.
PORT
l
Address Data
Address
XX
Solution
AGAIN MOVFF PORTB, PORTC

The PIC uCs

GOTO AGAIN

F81H
F81H
F82H
F82H
F83H
F83H

XX
XX
XX

1-39

PIC Status Register

To indicate
d
arithmetic
h
conditions
d
It is a 8-bit register
g
Five bits are used
D0
D0:
D1:
D2:
D3:
D4:

The PIC uCs

C
DC
Z
OV
N

Carry Flag
Digital Carry Flag
Z
Zero
Fl
Flag
Overflow Flag
Negative Flag

1-40

Figure 2
2-7
7. Bits of Status Register

The PIC uCs

1-41

Example 2-8
Show
h
the
h status of
f the
h C, DC,
D Z flags
fl
after
f

the following addition instruction

MOVLW 38H

ADDLW 2FH
Solution
38H + 2FH = 67H WREG=67H
WREG 67H
C=0
DC 1
DC=1
Z=0
The PIC uCs

1-42

Example 2-9
Show
h
the
h status of
f the
h C, DC,
D Z flags
fl
after the following addition instruction

MOVLW 9CH

ADDLW 64H
Solution
9CH + 64H = 100H WREG=
WREG 00H

C=1
DC 1
DC=1
Z=1
The PIC uCs

1-43

Instruction That Affect Flag

Bits

The PIC uCs

1-44

Instruction That Affect Flag

Bits

The PIC uCs

1-45

Instruction That Affect Flag

Bits

The PIC uCs

1-46

Flag Bits and Decision Making

The PIC uCs

1-47

PIC Data Format and Directives

There
h
is one data
d
type
8 bits
It is the job of the programmer to break down
data larger 8 bits
Data type can be positive or negative
Data format are
Hex (default in PIC) 12 or 0x12 or H'12' or 12H
B
Binary
nary B
B'00010010'
000 00 0
Decimal .12 or D'12'
ASCII A
A'c'
c or a
a'c'
c
The PIC uCs

1-48

Assembler Directives
What
h is the
h difference
d ff
between
b

Instruction and Directives?

EQU
Defines

a constant or fixed address

SET
Defines a constant or fixed address
Maybe reassigned later
ORG (Origin)
END
LIST
The PIC uCs

1-49

Rules for labels in A.L.

AL
Unique name
Alphabetic
p
letters
Upper, lower, digits (0-9),special char. (? . @_
$)
The first letter must be Alphabetic letters
Not a reserved word

The PIC uCs

1-50

Introduction to PIC Assembly

Language
Difficult
D ff l for
f us to deal
d l with
h the
h machine
h

code ( 0s and 1s)

Assembly Language provide
Mnemonic:

codes and abbreviations that are

easy to remember
Faster programming and less prone error
LLL (why?)
Programmer must know all Reg. etc.
Assembler is used to translate the

assembly
m y code into machine
m
code (object
( j
code)

The PIC uCs

1-51

Structure of Assembly
Language
Series of
f lines
l
Instruction
Directives
Consists of four field

[label] mnemonic [operands] [;commands]

Label: refer to line by code (certain length)
Mnemonic and operands are task that
sh ld be
should
b executed.
t d
Directive

dont generate any machine code and

used by assembler

The PIC uCs

1-52

Sample of Assembly Language

Program
SUM
UM EQU 10H ;RAM
R M lloc 10H fro
f SUM
UM
ORG 0H; start at address 0
MOVLW 25H ; WREG = 25
ADDLW 0x34 ;add 34H to WREG=59H
ADDLW 11H ;add 11H to WREG=6AH
ADDLW D18 ; W = W+12H=7CH
ADDLW 1CH ; W = W+1CH=98H
ADDLW b00000110 ; W = W+6H=9EH
MOVWF SUM ;save the result in SUM location
HERE GOTO HERE ;stay here forever
END
; end of asm source file
The PIC uCs

1-53

Assembling and Linking A PIC

Program
Figure 22
8. Steps
to C
Create
a Program
g

The PIC uCs

1-54

List File

The PIC uCs

1-55

The Program Counter and

Program ROM Space in the PIC
Program
P
Counter (PC)
(P ) is used
d by
b the
h CPU
P to

point to the address of the next

instruction to be
b executed
d
The wider the p
program
g
counter, more the
memory locations can be accessed
PIC16

has 14 bits (8K)

( )
PIC18 has 21 bits (2M)
8051 has 16 bits (64K)
(
)

The PIC uCs

1-56

Figure 2-9. Program Counter in

PIC18

The PIC uCs

1-57

The PIC uCs

3-58

Example 2
2-11
11
Find
F d the
h ROM Memory Address
dd
of
f each
h of
f

the following PIC chips:

a) PIC18F2220
b) PIC18F2410
c) PIC18F458

The PIC uCs

1-59

P
Powering
i UP
At what address does the
CPU wake up when power
applied?
The uC wakes up at
mem r address 0000
memory
The PC has the value 0000
ORG directive put the
address of the first op
p
code at the memory
location 0000
The PIC uCs

Figure 2-11. PIC18

Program ROM Space

1-60

Placing Code in program ROM

The PIC uCs

1-61

Program Memory

All instructions are 2Byte

except the GOTO,
which has 4-Byte

The PIC uCs

1-62

Program ROM Width for the

PIC18
Byte
B
addressable:
dd
bl each
h llocation h
holds
ld only
l one

byte

CPU

with 8-Bit will fetch one byte a time

Increasing the data bus will bring more information
Solution: Data bus between CPU and ROM can

be similar to traffic lanes on the highway

g
y
The wide of Data path is 16 bit
Increase

the processing power

Match the PIC18 instruction single
cycle
The PIC uCs

1-63

Figure 2-12. Program ROM

Width for the PIC18

The PIC uCs

1-64

Little endian VS big endian war

The
h low
l
byte
b
goes to the
h low
l
memory

location
The high byte goes to the high memory
location
Intel uP and many uCs use little endian

The PIC uCs

1-65

Figure 2-13. PIC18 Program ROM

Contents for Program 2-1 List File

The PIC uCs

1-66

Harvard Architecture in the

PIC
Von Neumann
N
Architecture:
h
uses the
h same

bus for accessing both the code and data

memory.
Slow

down the processing speed

Get in each others way
Harvard Architecture: uses separate
p
buses

for accessing the code and data memory.

Inexpensive
p

The PIC uCs

for a chip
p

1-67

Figure 2-14. von Neumann vs.

Harvard Architecture

The PIC uCs

1-68

Instruction size of the PIC18

PIC
P Instructions are 2-Byte
B
or 4-Byte
4 B
The first seven or eight
g bits represents
p

the op-code
Most of PIC18 instructions are 2
2-Byte
Byte
MOVLW
ADDLW
MOVWF

0000 1110
0000 1111
0110 111a

kkkk kkkk (0E XX)

kkkk kkkk (0F XX)
ffff ffff (6E XX
F XX))
or 6F

A specifies the default access bank if it is 0 and if a

= 1 we have to use bank switching
The PIC uCs

1-69

Instruction size of the PIC18

4-Byte
4 B
instructions include
l d
MOVFF (move data within RAM, which is 4k)
1100 ssss
1111 dddd
GOTO

is 2M)

1110
1111

The PIC uCs

ssss
dddd

ssss
dddd

(0 fs FFF)
(0 fd FFF)

(th
(the code
d address
dd
b
bus width
idth iis 21,
21 which
hi h
1111
k7kkk kkkk0
k19kkk kkkk kkkk8

1-70

RISC Architecture in the PIC

To increase the
h processing power of
f the
h

CPU
1.
2.
3.

The PIC uCs

Increase the clock frequency of the chip

Use Harvard architecture
change the internal architecture of the CPU
and use what is called RISC architecture

1-71

RISC Architecture in the PIC

RISC

CISC

Simple
p and Small

Complex
p
and large
g

instruction set
Regular and fixed
instruction format
Simple address
modes
Pipelined instruction
execution --> 95%
executed in one cycle
The PIC uCs

instruction set
Irregular instruction
format
Complex address
modes
May also pipeline
instruction execution
1-72

RISC Architecture in the PIC

RISC

CISC

Provide large
g number

Provide smaller number

of CPU registers
Separated data and
program memory
Most operations are
register to register
Take shorter time to
design and debug
The PIC uCs

of CPU registers
Combined data and
program memory
Most operations can be
register to memory
Take longer time to
design and debug
1-73

Viewing Register and memory

with MPLAB Simulater

The PIC uCs

1-74

Figure 2-15. SFR Window in

MPLAB Simulator

The PIC uCs

1-75

Figure 2-16. File Register (Data

RAM) Window in MPLAB Simulator

The PIC uCs

1-76

Figure 2-17. Program (Code)

ROM Window in MPLAB
Simulator

The PIC uCs

1-77

Chapter 2: Summary
Sample PIC18

Instructions
Move,
Move

add,
add subtract
Next:
Branch,, Call and Time
Delay Loo

The PIC uCs

3-78