Electrical Engineering 83 (2001) 137145 Springer-Verlag 2001

Multipulse converters and controls for HVDC and FACTS systems

M. Aredes, A. F. C. Aquino, G. Santos Jr

Contents For very high power applications, it is imperative to limit switching losses in the power converter.
Multipulse converters are made up from several converter
modules, switching at the fundamental frequency, but
properly phase shifted to produce a nearly sinusoidal
output voltage. Robust controls for HVDC and FACTS
systems based on multipulse converters were developed.
The developed HVDC system makes the rectier station to
control the instantaneous active (real) power through the
HVDC voltage link, whereas the inverter station controls
the instantaneous reactive (imaginary) power generation.
The control of real and imaginary powers is independent
one from the other and there is no control signal that is
shared by both converter stations. A complete model of a
100 MW, 33 kVac, 50/60 Hz, 24-pulse HVDC system was
implemented in the electromagnetic transient program
(EMTP/ATP). The static synchronous compensator
(STATCOM) is a shunt type of FACTS controller. It
regulates the voltage magnitude of a controlled ac bus by
drawing variable reactive current from the power system.
The fast dynamic of the STATCOM controller avoids high
uctuations of the dc voltage caused by transients. A
complete model of a 100 MW, 33 kV, 60 Hz, 24-pulse
STATCOM was implemented and the results have conrmed the robustness of the proposed voltage control.

1
Introduction
HVDC systems are very useful for transmitting energy
between two asynchronous ac power systems with high
controllability. Conventional HVDC transmission systems
based on thyristor converters have been widely applied
where exibility and stability improvements are required.
However, thyristor based HVDC systems need high support of local reactive power generation. Moreover, the
active and reactive power cannot be controlled independently from each other. New HVDC systems based on dc
voltage links have been considered feasible [1]. Since they
are based on forced-commutated converters (also known
as voltage source converters (VSC)), they can provide in-

Received: 21 December 2000

M. Aredes (&), A. F. C. Aquino, G. Santos Jr

COPPE/EE, Department of Electrical Engineering,
UFRJ Federal University of Rio de Janeiro,
PO Box 68504, 21945-970 Rio de Janeiro RJ, Brazil
e-mail: [email protected]

dependent control of active (real) and reactive (imaginary)

power or even supply fully passive ac loads.
The STATCOM is an advanced power electronic
equipment for reactive power compensation. It is a very
fast acting, electronic equivalent of the synchronous
condenser. It is considered as a Flexible AC transmission
systems controller (FACTS). The STATCOM is a shunt
compensator [2, 3]. It can draw variable reactive current
from the system to control the voltage magnitude of a
selected bus (controlled ac bus).
Several technological issues limit the switching frequency of power converters for very high power applications. The converters require semiconductor power
switches with high voltage and current ratings, which,
nowadays, can only be obtained with series and parallel
connections of GTOs, GCTs or IGBTs. Therefore, most
power electronics equipments working at very high power
ratings are made up from converters switching at the
fundamental frequency.
The multipulse converter can be obtained from the
combination of several converter modules switching at the
fundamental frequency [4, 5]. Three-phase converters
switching at the fundamental frequency are known as
6-pulse converters. A 24-pulse converter arrangement
made up from four 6-pulse converters is proposed and
employed as the power circuit for an HVDC system and a
STATCOM. Complete digital models of both systems were
implemented in the EMTP/ATP simulator. The control
circuits of the HVDC system and STATCOM work based
on the same principles and are very similar. Some simulation results are already presented separately in [6] and in
[7]. Here, improved versions of the HVDC and the
STATCOM control systems are proposed to minimize
overvoltages and overcurrents due to ac system voltage
unbalances and faults. It will be seen that these improvements were possible without increasing the reduced
number of voltages and currents measurements, as proposed in [6, 7]. The proposed HVDC control system does
not need any communication between the converter station controls. No dc voltage or current measurements are
needed in both HVDC and STATCOM control systems.

2
The 24-pulse converter
The coupling transformer is an important component for
composing the output voltage waveform of a multipulse
converter. Four 6-pulse converters connected in series at
the primary side form an equivalent 24-pulse voltage, as
shown in Fig. 1. Two ordinary three-phase transformers

137

Electrical Engineering 83 (2001)

138

Fig. 1. Output voltage of a 24-pulse

converter

have their secondary windings connected in D and the

other two in ungrounded Y. This approach was preferred
due to its simplicity. Although it reduces drastically the
11th and 13th voltage harmonics, it cannot cancel them
completely.
Figure 2 shows the phase (van) and line (vab) voltage
waveforms of an ideal 6-pulse converter that are applied to
the secondary windings, in case of Y or D connection,
respectively. Each GTO valve conducts during 180 and the
pulses are shifted 120 between phases. In this case, the
output voltages that appear, with respect to the midpoint
of the dc link, are those named as vao, vbo and vco. in Fig. 2.
The line voltages vab, vbc, vca are determined from these
output voltages, that is,

8
Vab Vao
>
>
<
Vbc Vbo
>
>
:
Vca Vco

Vbo
Vco :

Vao

Then, the phase

8
Van Vab
>
>
<
Vbn Vbc
>
>
:
Vcn Vca

voltages van, vbn, vcn are determined as

Vca =3
Vab =3 :

Vbc =3

It is possible to see that the fundamental component of vab

leads by 30 the voltage vao, whereas van is in phase with
vao. A 12-pulse voltage waveform can be made up from two
6-pulse converters, one connected in D and the other
connected in ungrounded Y. However, to compensate the
30 phase shift (leading) of vab, the ring pulse sequence of
the D-connected converter must be delayed by 30 with
respect to the corresponding sequence of the Y-connected
converter. The converters #1 and #2 in Fig. 1 produce a 12pulse voltage that is 15 phase shifted from the 12-pulse
voltage composed by converters #3 and #4. In order to put
the resultant 24-pulse voltage in phase with the reference
(0), one Y-connected converter (#1) begins to re at )7.5
(lagging), and the second Y-connected converter (#3)
begins at +7.5 (leading), as illustrated in Fig. 1. Thus,
the converter #2 begins to re at )37.5 and converter
#4 at )22.5.

Fig. 2. Output voltages of a 6-pulse converter

2.1
Active and reactive power generation
Six-pulse voltage source converters do not need capacitor
or reactor banks to produce reactive power. Actually, the
converter dc capacitors in Fig. 2 act as dc voltage source
and are not related with the generated reactive power.
Figure 3 represents a multipulse converter connected to
an ac bus. If the output voltage (V24P) is in phase with the
ac bus voltage (VM), no active power ows through the
converter transformer. When the fundamental component
of the 24-pulse voltage is greater than the ac bus voltage,
leading reactive current is drawn from the ac bus and the
equipment behaves as a capacitor. When the 24-pulse
voltage is smaller than the ac bus voltage, lagging
reactive current is drawn (inductive current), as shown in
Fig. 3.
By switching at the fundamental frequency, the amplitude of the generated multipulse voltage is directly

M. Aredes et al.: Multipulse converters and controls for HVDC and FACTS systems

139

Fig. 3. Control of active and reactive power generation in a multipulse converter

proportional to the dc voltage magnitude. The proposed

HVDC and STATCOM controllers exploit this important
feature of the multipulse converter.
The controller of the multipulse converter should cause
a temporary ow of real power, sufcient to charge or
discharge the dc capacitor, to set properly the dc voltage
and the ac output voltage. This is achieved by lagging or
leading slightly and temporarily shifting by d the 24pulse voltage with respect to the controlled ac bus voltage,
as shown in Fig. 3. In practice, a small amount of real
power is also drawn from the power system to compensate
for losses in the converters and transformers.

3
The multipulse STATCOM
Figure 4 shows the basic conguration of the proposed 24pulse STATCOM for voltage regulation. The controller of
the STATCOM is quite simple. For control purposes, only
the primary voltage of the converter transformer must be
measured. As explained before, the principle of voltage
regulation consists of drawing capacitive currents to raise,
or inductive currents to lower, the controlled ac bus voltage (v), respectively. The control scheme for the proposed
multipulse STATCOM is composed by a synchronizing
circuit (PLL circuit), a power angle control circuit and a
ring control. These control circuits were rst proposed in
[7]. Further, more simulations were carried out, and the
control gains were optimized, focusing on minimization
of overvoltages and overcurrents. The operation under
unbalanced system voltage was also investigated and the
new results are shown in the following sections.

Fig. 4. Basic conguration of a 24-pulse STATCOM

real power ow into (from) the STATCOM is forced to

charge (discharge) the dc capacitor. While the phase angle
of the 24-pulse voltage lags d < 0 the bus voltage, energy
is owing to the dc capacitor, charging it and making the
STATCOM draw more and more capacitive current.
3.1
Contrarily, more inductive current is drawn while d > 0.
Power angle control circuit
Figure 5 shows the control block diagram of the power
The ac bus voltage v in Fig. 4 is controlled by drawing
angle control. The inputs of this circuit are the per unit
variable reactive current from the system. Leading (cavalues (pu) of the instantaneous phase voltages of the
pacitive) reactive current to the STATCOM increases the controlled ac bus. The reference voltage (Vref) is compared
voltage amplitude of the controlled ac bus. Inductive
to the ltered, instantaneous aggregate voltage VR ,
current decreases the ac voltage. To force the STATCOM which, in steady state, is a constant value and equal to the
to draw more capacitive or inductive current, a temporary, line voltage, if the voltages are balanced and sinusoidal. If

Electrical Engineering 83 (2001)

the phase voltages are unbalanced or distorted, VR will

contain an oscillating portion. The signal d corresponds to
the displacement angle of the generated 24-pulse voltage
with respect to the controlled ac bus voltage (primary
voltage of the converter transformer). Ideally, d is zero
in steady state and 24-pulse voltage is in phase with the
controlled ac bus voltage.

140

3.2
Synchronizing circuit (PLL circuit)
The synchronizing circuit (PLL circuit) is responsible for
determining the power system frequency and the phase
angle of the fundamental positive-sequence voltage of the
controlled ac bus. Figure 6 shows the scheme of the used
PLL circuit. The inputs are the per unit (pu) values of the
line voltages vab va vb and vcb vc vb . This circuit
has proved to be very effective, even under high-distorted
system voltages.
The algorithm is based in the instantaneous active
power expression:

3.3
Firing control circuit
Figure 7 shows the ring control circuit for a 6-pulse
converter. Thus, the 24-pulse converter has four of such
circuits. The angular frequency x, given by the PLL circuit
(Fig. 6), and the power angle d, given by the power angle
control (Fig. 5), are unique for all four 6-pulse converters.
Only /conv differs from each other, that is, converter #1:
)7.5; converter #2: )37.5; converter #3: +7.5; and
converter #4: )22.5. As explained before, the function
sinxt leads 90 the phase voltage va of the ac bus. Thus,
sinxt p=2 lays in phase with va. Three logic functions
[sign(x)] generates the ring pulse for the upper GTOs #1,
#3 and #5 (see Fig. 2); their complements correspond to the
ring pulse of the lower GTOs #4, #6 and #2, respectively.

4
The multipulse HVDC system
An advantage of using self-commutated converters (multipulse converters), instead of thyristor-based converters,
in HVDC systems is the possibility of generating controlled
p3/ va ia vb ib vc ic vab ia vcb ic :
3 inductive or capacitive reactive power independently from
the transmitted active power. The proposed multipulse
Note that ia ib ic 0 is considered in (3). As no
current is measured from the power circuit, one may nd HVDC system is composed by two converter stations using
the 24-pulse converter as explained in Fig 1. Figure 8 shows
difcult to understand how the circuit works. Current
the basic conguration of the proposed 24-pulse HVDC
feedback signals of Fig. 6 ia xt sinxt and
system. The dc capacitor gives a voltage source characteric xt sinxt 2p=3 are built up by the PLL circuit,
just using the output x of the PI-controller kP 50,
kI 3000). The PLL reaches a stable operation point only
if the input p3/ of the PI-controller has a zero average
value. This is found if x equals the system frequency and
the current ia xt becomes orthogonal to the phase voltage
va of the power system. However, if the point where ia xt
lags va by 90 is reached, this is still an unstable point of
operation. At this point, an eventual disturbance that
slightly increases the system frequency (given by the line
voltages vab and vcb in Fig. 6) will make the phase angle
between va and ia xt become greater than 90. This leads
to a negative input p3/ and consequently to a decrease in
the output x, making the phase angle between va and
ia xt even greater. This positive feedback characterizes
an unstable point. Thus, the PLL has only one stable point
Fig. 6. Block diagram of the PLL circuit
of operation: ia xt leading 90 the phase voltage va.
This fundamental characteristic of the PLL circuit can be
exploited to compose the needed sinusoidal functions,
properly phase-shifted, to achieve ring pulse logic for the
GTO valves.

Fig. 5. Block diagram of the STATCOM power angle control

Fig. 7. Firing control of a six-pulse converter

M. Aredes et al.: Multipulse converters and controls for HVDC and FACTS systems

141
Fig. 8. The 24-pulse HVDC system

istic for the dc link. For simplicity, no dc transmission line

was considered and the rectier and inverter stations are
connected back-to-back to the dc capacitor. No dc or ac
lters were provided, since it is reasonable to expect that
the power system can tolerate the current harmonics
excited by the resultant 24-pulse output voltages.
A relatively simple control scheme for the proposed
multipulse HVDC system was developed and rst presented in [6]. The control of each converter station has the
same basic control circuits as used previously in the
STATCOM controller. Actually, the synchronizing circuit
(PLL Circuit), Fig. 6, and the ring control circuit, Fig. 7,
are exactly the same. Only the power angle controls are
different, as shown in the next sections.

reactive power orders, and reclosings of the HVDC system.

The difcult here is to choose adequate values that still
allow high system performance, but can protect the system
against high overvoltages and overcurrents. As system
requirements changes case by case, the development of an
optimization method for choosing such values might be
interesting.

4.2
Inverter power angle control circuit
The inverter station controls the instantaneous reactive
(imaginary) power at the inverter ac bus. Hence, the inverter station acts like a STATCOM. In fact, it can behave
as a STATCOM even if the rectier station is out of operation, since it does not need any information from the
rectier control system. On the other hand, the rectier
cannot continue to operate if the inverter shuts down,
because the active power ow imposed by the rectier
control would cause overvoltages in the dc capacitor.
Figure 10 shows the control block diagram of the
inverter power angle control. If no real power is owing
through the dc link (Porder 0), the generated 24-pulse
voltage of the inverter is in phase with the inverter ac bus
voltage VI (Fig. 8). Like in the STATCOM application, the
amplitude of the 24-pulse voltage must be greater or
smaller than the ac bus voltage to generate capacitive or
inductive reactive (imaginary) power, respectively. Thus,
the inverter power angle control must cause temporary
active power ow from (to) the dc link dI  0, to properly
charge or discharge the dc capacitor, in order to achieve
the required imaginary power order (Qorder). Unfortunately, changes in dc voltage also affect the amplitude of
the rectier ac output voltage. Hence, the reactive (imaginary) power of the rectier and inverter cannot be con-

4.1
Rectifier power angle control circuit
The rectier station dictates the instantaneous active (real)
power ow through the dc link. The instantaneous active
and reactive power calculation in the HVDC control
system is based on the p-q theory [8]. The rectier power
angle control provides fast and bi-directional power ow
controllability. Figure 9 shows the control block diagram
of the rectier power angle, dR . The signal dR corresponds
to the displacement angle of the generated 24-pulse voltage
with respect to the rectier ac bus voltage VR (Fig. 8). If
dR < 0, the 24-pulse voltage lags VR, which forces real
power to ow from the rectier to the inverter. The inverse
occurs if dR > 0. Positive real power order (Porder) means
power owing from the rectier to the inverter station.
In order to avoid high overvoltages and overcurrents
during faults, an auxiliary control circuit was added, but
still using the same reduced number of measurements like
in the previous version of this control system [6]. During
faults, high dp/dt occurs, which is sensed by the difference
e between the input and the output of the low-pass lter.
When this difference becomes greater than 0.25 pu, a
counter in this auxiliary control circuit freezes instantaneously dR 0, for 20 ms, in order to drop to zero the
average real power into the dc link. However, if during this
period e becomes lower than 0.25 pu and greater again, the
counter is reset and begins to count for more 20 ms. Only
if e goes down and remains lower than 0.25 pu, after
20 ms, dR is released slowly. The limit value of 0.25 pu and
the frozen time 20 ms were chosen after several simulation
test cases involving faults, step changes in the active and Fig. 9. Block diagram of the rectier power angle control

Electrical Engineering 83 (2001)

142

trolled independently from each other in real time. On the

other hand, in steady state, the inverter power angle dI
assumes the inverse value of the rectier power angle,
because power ow through the dc link must be balanced.
Otherwise, the dc voltage does not stabilize at a level that
generates the required imaginary power order. Qorder > 0
means that the inverter ac system ``sees'' an inductive
``load'' (lagging currents owing to the inverter).
Another auxiliary control for the inverter was added to
protect against overcurrents and overvoltages during
faults. Here, the difference e due to high dq/dt, freezes
instantaneously dI 0, for 10 ms, if e becomes greater
than 0.8 pu. This circuit releases instantaneously dI , after
10 ms, if e goes down and remains lower than 0.8 pu.
Again, the set up of the limit value (0.8 pu) and the frozen
time (10 ms) were chosen after several simulation test
cases.

5
Multipulse STATCOM simulation results
A complete model of the 24-pulse STATCOM (Fig. 4) for
dynamic analysis was implemented in the ATP/EMTP
simulator. The STATCOM is connected to a very weak ac
system. The short circuit power at the controlled ac bus is
300 MVA. The power rating of the STATCOM is 100 MVA,
33 kV (60 Hz). The YY transformers are dimensioned as
8.25/8.25 kV, 25 MVA,pXT 15%, whereas the YD
transformers are 8:25= 3
8:25 kV, 25 MVA, XT 15%.
With these transformer voltage ratios, the controller of the
24-pulse STATCOM adjust the dc voltage at 10.6 kV, if the
controlled ac bus voltage is 33 kV (1 pu) and no compensating current is drawn from the network. The dc link
capacitance is set equal to 3 mF. To given an idea how low
is this dc capacitance, the ``unit capacitance constant''
(UCC), calculated as
2
CVdc
;
4
2P
gives only 1685 ls, if P 100 MW and the dc voltage is
10.6 kVdc. Some authors consider UCC < 5000 ls as low
values [1, 5].
Several simulation cases were carried out. Some of them
were presented in [7]. The control gains and the dc capacitance were modied to optimize compensation under
unbalanced system voltages. Here, two simulation cases,
with balanced system voltages and with unbalanced system
voltage (5% of fundamental negative sequence voltage),

UCC

Fig. 10. Block diagram of the inverter power angle control

are compared. The total simulation time of these two cases

is 1 s. During the simulation the following events occur:
 closing of the STATCOM circuit breakers at 150 ms;
 ring start of the STATCOM valves at 200 ms, with
Vref 1.0 (pu);
 connection of a 100 MVA, PF 0.85 (inductive), load
at 400 ms;
 step change in Vref from 1.0 to 0.85 pu, at 600 ms;
 step change in Vref from 0.85 to 1.10 pu, at 800 ms.
Figure 11 shows the instantaneous active (real) power,
PC, owing to the STATCOM to charge (discharge) the dc
capacitor and achieve the proper dc voltage level. Thus,
the dc voltage varies to generate the necessary reactive
(imaginary) power, QC, and keep the controlled ac bus
voltage regulated (equal to Vref). The system voltage (VG in
Fig. 4) is balanced and was set at 1 pu (33 kV). Hence,
before the load connection (t < 0.4 s) no compensation is
needed and the STATCOM draws only a very small active
current to compensate for switching losses. After the
connection of the load, the STATCOM is regulating the ac
bus voltage at 1.00 pu (0.4 < t < 0.6 s), then, at 0.85 pu
(0.6 < t < 0.8 s), and 1.10 pu (0.8 < t < 1.0 s). Figure 12
shows in details the STATCOM output voltage (V24P),
the controlled ac bus voltage (V), and the compensating
current (IC) drawn from the network, around t 0.8 s,
during the step change in Vref, from 0.85 to 1.10 pu.
Another simulation including unbalance of 5% of negative sequence voltage in VG (Fig. 4) was carried out for
comparison with the previous case. Figure 13 shows the
instantaneous aggregate values VR of the controlled ac
bus voltage and the dc capacitor voltages (Vdc), for both
balanced and unbalanced system voltage cases. Multipulse
STATCOMs generate inherently balanced multipulse
voltages. Hence, it cannot avoid negative-sequence currents owing to it, if they are excited by unbalances in the
system voltage. Unfortunately, the product between the
fundamental negative-sequence current and the fundamental positive-sequence voltage causes oscillating real
power ow at twice (120 Hz) the system frequency [8].
This leads to oscillations in the dc voltage at equal
frequency, which degenerate the 24-pulse output voltage.
These voltage oscillations at twice the system frequency
can be seen in details in the upper and lower graphics of
Fig. 13, for VR and Vdc, respectively.

Fig. 11. Instantaneous active (real) and reactive (imaginary)

power of the 24-pulse STATCOM

M. Aredes et al.: Multipulse converters and controls for HVDC and FACTS systems

6
Multipulse HVDC system simulation results
Two simulation cases are shown below. The rst shows
several step changes in the real and imaginary power orders and the other shows the recovery of the HVDC system
after a phase-to-ground fault at the inverter ac bus.
The power rating of the 24-pulse HVDC model is
100 MW. The GTO valves were modeled using ideal
switches. The HVDC system interconnects two weak
asynchronous (50 and 60 Hz) ac systems, as suggested
in Fig. 8. The short circuit power at the inverter and at
the rectier ac buses are made as low as 300 MVA, and
the rated ac voltage is 33 kV (50 and 60 Hz). The YY
transformers are dimensioned as 8.25/8.25 kV, 25 MVA,

XT p
15%
(50 or 60 Hz), and the YD transformers are
8:25= 3
8:25 kV, 25 MVA, XT 15%. The dc link
capacitance is set equal to 500 lF. Note that this dc
capacitance corresponds to 1/6 of that used in the
STATCOM model. Thus, ``unit capacitance constant''
(UCC), gives only 270 ls, if P 100 MW and the dc
voltage is around 10.4 kVdc to produce unit power
factor (Qorder equal to zero).
The total harmonic distortion (THD) of the resultant
24-pulse voltage shown in Fig. 1 is less than 7%. Although
relatively high THD, no ac or dc lter was implemented,
because the high leakage inductance of the transformers
behaves as low-pass lters.

6.1
Full power reversion
This simulation case involves several events:
 start of the HVDC link at 200 ms with Porder 0 and;
Qorder 0 pu;
 step change in Porder from 0 to +1.0 pu, at 300 ms;
 step change in Porder from +1.0 to )1.0 pu, at 550 ms;
 step change in Qorder from 0 to +0.3 pu, at 850 ms;
 step change in Qorder from +0.3 to )0.3 pu, at 1000 ms;

Although both asynchronous ac systems are very weak,

Fig. 14 and Fig. 15 demonstrate that a very fast system
dynamics could be achieved. The power angles of the
Fig. 12. STATCOM output voltage (V24P), controlled ac bus
stations are symmetric. For instance, before t 300 ms,
voltage (V) and compensating current (IC)
Porder and Qorder are zero (no power ow and zero imaginary power generation) and dR and dI are zero. Then, the
rectier begins to pump energy to the dc link capacitor,
charging it. This increases the amplitude of the ac output
voltages at both stations, which makes them temporarily
work as ``capacitor banks'' (negative imaginary power),
as shown in Figure 14b. The power angle control of the
inverter senses this disturbance and begins to open the
power angle in opposite direction, pushing energy from
the dc link to discharge the dc capacitor. After the transient, the active power ow is balanced and the inverter
returns to produce zero imaginary power. Figure 14b
shows that the control of the inverter imaginary power
affects also the rectier imaginary power, because both
station are made up from multipulse converters (fundamental switching frequency). As mentioned before, this
kind of converter generates reactive power proportionally
to the dc voltage level. If independent control of imaginary
powers is desired, PWM control for the 6-pulse converters
should be provided at least in the rectier station. In this
case, another control system should be designed. Another
alternative is to provide on-load tap changer for the
rectier transformers. However, this does not provide
real time controllability (fast response), although it is
commonly used in conventional thyristor-based HVDC
systems.
A full power reversion at t 550 ms and a step change
from +j0.3 pu (inductive) to )j0.3 pu (capacitive) is
induced through step changes in the real (Porder) and
imaginary (Qorder) power orders. Details from the phase
voltage and line current at the rectier and inverter ac
Fig. 13. STATCOM performance under balanced and unbalanced bus can be seen in Figs. 16 and 17. One can see that the
system voltages
24-pulse output voltage of the multipulse converters

143

Electrical Engineering 83 (2001)

144

Fig. 16a, b. Active power reversion: (a) rectier and (b) inverter
ac voltages and currents
Fig. 14a, b. (a) Instantaneous real power and (b) instantaneous
imaginary power of the converter stations

Fig. 15. Power angle of the rectier and inverter station

is well smoothed by the leakage inductance of the

transformers. After t 550 ms the power transfer from
the inverter to the rectier is kept constant at 1 pu
(Porder )1 pu). Then, the system is overload at
t 850 ms, and the inverter turns to draw (power into
the inverter) 100 MW + j33 Mvai (inductive). After
t 1.0 s, the reactive power generation passes from
+j33 Mvai (inductive) to )j33 Mvai (capacitive). One can
see the corresponding phase shift in Fig. 17.

6.2
Phase-to-ground fault at the inverter ac bus
In order to show the robustness of the control and the high
performance of the proposed multipulse HVDC system,
asymmetric faults were applied to the system. Here, a
phase-to-ground fault at the ac bus of the inverter station
is shown. Before the fault is applied, the rectier is
supplying full power (100 MW, Porder 1.0 pu) to the
inverter, and the inverter is operating at unity power
factor (Qorder 0 pu). Then, the fault is applied at
t 600 ms and cleaned at t 700 ms.
Figures 18 and 19 show the very fast recovery of the
system, after fault cleaning. Moreover, no severe overvoltage or overcurrent is veried at the primary side of the
converter transformer of the inverter station, where the

Fig. 17a, b. Step change in imaginary power: (a) rectier and (b)
inverter ac voltages and currents

fault is applied. Figure 19 shows the currents owing into

the primary side of the converter transformer. Thus, iIb
and iIc are equal to the currents of the inverter ac system,
but iIa is the difference between ac system current and fault
current.
Figure 20 shows the dc voltage and the dc current
owing from the rectier to the dc capacitor and inverter
station. The effectiveness of the auxiliary control circuit
that freezes temporarily the power angles dR and dI
(Figs. 9 and 10) during disturbs is evidenced if compared
with the results of the previous version without it [6].

7
Conclusions
A relatively simple and robust control strategy for multipulse converters is proposed. This control strategy is
suitable for both HVDC and FACTS applications. The
proposed controllers for the multipulse STATCOM and the
multipulse HVDC are very similar.
It has been shown that conventional three-phase
transformers, instead of using special interphase magnetics, are viable to compose multipulse converters, which
can bring reduction in cost. From the proposed approach,
a 48-pulse converter for very high power applications
could be easily derived.

M. Aredes et al.: Multipulse converters and controls for HVDC and FACTS systems

Fig. 18. Phase-to-ground fault: inverter ac bus voltages

Complete digital models of multipulse HVDC and

STATCOM were implemented and validated through
simulation results. A reduced number of measurements is
needed to implement the control strategy. For control
purposes, neither in the HVDC system, nor in the STATCOM, there are needs of measurements at the dc link.
The high performance and robustness of the proposed
STATCOM controller has avoided high uctuations in the
dc voltage, caused by transients, faults, or unbalances in
the system voltages.
In the HVDC system, the converter stations do not
share any information or control signal, in normal operation or during non-permanent faults at the ac systems.
It provides bi-directional active power ow control independently from the controlled reactive power generated by
the inverter station.

References

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current from the rectier station

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