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    Homework 5

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    dogudogu
    This document outlines homework assignments for an EE685 VLSI broadband communication circuits course. It includes designing a linear and bang-bang phase detector for 1Gb/s data, a charge pump circuit, and a voltage controlled oscillator macromodel. The assignments require simulating transfer curves and output waveforms to characterize circuit performance.

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    Homework 5

    Uploaded by

    dogudogu
    90 views2 pages
    This document outlines homework assignments for an EE685 VLSI broadband communication circuits course. It includes designing a linear and bang-bang phase detector for 1Gb/s data, a charge pump circuit, and a voltage controlled oscillator macromodel. The assignments require simulating transfer curves and output waveforms to characterize circuit performance.

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    homework 5

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    This document outlines homework assignments for an EE685 VLSI broadband communication circuits course. It includes designing a linear and bang-bang phase detector for 1Gb/s data, a charge pump circuit, and a voltage controlled oscillator macromodel. The assignments require simulating transfer curves and output waveforms to characterize circuit performance.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    90 views2 pages

    Homework 5

    Uploaded by

    dogudogu
    This document outlines homework assignments for an EE685 VLSI broadband communication circuits course. It includes designing a linear and bang-bang phase detector for 1Gb/s data, a charge pump circuit, and a voltage controlled oscillator macromodel. The assignments require simulating transfer curves and output waveforms to characterize circuit performance.

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    EE685: VLSI Broadband Communication Circuits; HW5

    Nagendra Krishnapura ([email protected])


    due on 5 Nov. 2007
    Linear phase detector: Design a linear (Hogge)
    phase detector for 1 Gb/s data using ip ops de-
    signed in the rst assignment and CML gates. Sim-
    ulate the transfer curve of average output volt-
    age (Average value of the difference between UP and
    DN waveforms from the phase detector) versus input
    phase difference over the input range of the phase
    detector. Use closely spaced points around = 0.
    Use alternating binary data input for the simulation.
    Bang Bang phase detector: Design a bang-
    bang (Alexander) phase detector for 1 Gb/s data us-
    ing ip ops designed in the rst assignment and
    CML gates. Simulate the transfer curve of average
    output voltage (Average value of the difference be-
    tween UP and DN waveforms from the phase de-
    tector) versus input phase difference over the input
    range of the phase detector. Use closely spaced
    points around = 0. Use alternating binary data
    input for the simulation.
    Charge pump: Design a charge pump using nMOS
    and pMOS differential pairs and 10 A cascode cur-
    rent sources. It should be able to operate over an
    output voltage range of V
    DD
    /2 0.5 V. Design the
    circuit for biasing the cascode current sources from a
    single 10 A reference. Use identical common mode
    voltages for UP and DN signals.
    Terminate the charge pump output with a V
    DD
    /2
    voltage source and drive it with alternating UP and
    DN signals with 0.5 ns width with a 1 ns period. Plot
    the output current waveform. Determine the aver-
    b
    i
    a
    s
    g
    e
    n
    e
    r
    a
    t
    o
    r
    reference
    current
    10A
    UP UP
    DN DN
    +

    V
    dd
    /2
    V
    dd
    I
    out
    0.5ns
    1ns
    UP
    DN
    Figure 1: Charge pump
    age output current of the charge pump over 100 cy-
    cles. This gives you the dynamic offset current of
    the charge pump. What phase offset does it corre-
    spond to? Repeat the offset simulations for termina-
    tion voltages of V
    DD
    /2 0.5 V
    VCO macromodel: Use the schmitt trigger oscil-
    lator in Fig. 2 to model a voltage controlled oscil-
    lator. For the opamp, use a voltage controlled volt-
    age source with a gain of 100 and saturation voltages
    of 1 V. Adjust RC and the feedback multiplication
    circuitry to get an oscillation frequency of 900 MHz
    for V
    ctl
    = V
    dd
    /2 and K
    vco
    = 250 MHz/V. To drive
    ip ops and other circuits differentially, scale the
    1
    2

    +
    R C
    V
    ctl
    voltage
    controlled
    attenuator
    +1
    -1
    slope=100
    A polynomial source
    can be used for the
    voltage controlled
    attenuator
    Figure 2: Voltage controlled oscillator
    opamp output appropriately and add the desired com-
    mon mode voltage.
    Time taken to do the assignment: How many hours
    did you spend on this assignment? Of those, how
    many were spent in writing up the report?

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