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    Exa/iaq/01 (01) Exa/iaq/01 (01) Exa/iaq/01 (01) : U I T U I T

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    This document contains an exam for a digital electronics course taken by students in their third semester of an electrical engineering program. The exam has two parts: Part A consists of 5 short answer questions covering topics like Boolean logic laws, prime implicants, logic families, and minimizing logic expressions. Part B consists of longer form questions involving minimizing logic expressions using Karnaugh maps, implementing Boolean functions with logic gates, describing the operation of CMOS inverters and tristate gates, and designing a full adder circuit. The exam is assessing students' understanding of foundational digital logic concepts as well as their ability to analyze and design basic digital circuits.

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    Exa/iaq/01 (01) Exa/iaq/01 (01) Exa/iaq/01 (01) : U I T U I T

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    This document contains an exam for a digital electronics course taken by students in their third semester of an electrical engineering program. The exam has two parts: Part A consists of 5 short answer questions covering topics like Boolean logic laws, prime implicants, logic families, and minimizing logic expressions. Part B consists of longer form questions involving minimizing logic expressions using Karnaugh maps, implementing Boolean functions with logic gates, describing the operation of CMOS inverters and tristate gates, and designing a full adder circuit. The exam is assessing students' understanding of foundational digital logic concepts as well as their ability to analyze and design basic digital circuits.

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    This document contains an exam for a digital electronics course taken by students in their third semester of an electrical engineering program. The exam has two parts: Part A consists of 5 short answer questions covering topics like Boolean logic laws, prime implicants, logic families, and minimizing logic expressions. Part B consists of longer form questions involving minimizing logic expressions using Karnaugh maps, implementing Boolean functions with logic gates, describing the operation of CMOS inverters and tristate gates, and designing a full adder circuit. The exam is assessing students' understanding of foundational digital logic concepts as well as their ability to analyze and design basic digital circuits.

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    32 views2 pages

    Exa/iaq/01 (01) Exa/iaq/01 (01) Exa/iaq/01 (01) : U I T U I T

    Uploaded by

    srisridivine
    This document contains an exam for a digital electronics course taken by students in their third semester of an electrical engineering program. The exam has two parts: Part A consists of 5 short answer questions covering topics like Boolean logic laws, prime implicants, logic families, and minimizing logic expressions. Part B consists of longer form questions involving minimizing logic expressions using Karnaugh maps, implementing Boolean functions with logic gates, describing the operation of CMOS inverters and tristate gates, and designing a full adder circuit. The exam is assessing students' understanding of foundational digital logic concepts as well as their ability to analyze and design basic digital circuits.

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    EXA/IAQ/01 (01)

    UNITED INSTITUTE OF TECHNOLOGY


    Periyanaickenpalayam, Coimbatore- 641 020.
    Academic Year - 2013-2014
    Internal Assessment I
    Degree & Branch: B.E &
    ECE-A/ECE-B
    Semester :III
    Date: 0 .08.2013 Time:
    EC2203- DIGITAL ELECTRONICS
    PART-A Max. Marks-50

    (Answer all the Questions) (5 X 2 = 10 Marks)
    1. State Basic Laws & De-Morgan theorem.
    2. What is prime Implicant & Essential prime Implicant?
    3. State the Advantages & Disadvantages of TTL & CMOS Logic.
    4. Find the minterms & Maxterms of the logic expression
    Y=ABC+ABC+ABC.
    5. List out the general characteristics of logic families?

    PART B (40 Marks)
    6. (a) Minimize the given terms
    m(A,B,C,D)= m(1,3,4,5,9,10,11) + d(2,6) using Quine
    Mc-Clusky methods and verify the results using K-
    Map techniques. (16)
    (OR)
    (b) Reduce the following expression
    (i).a AB+ (AC)+ABC (AB+C) &
    (i).b Y= (A+B) (A+C) (B+C) (7+7)
    (ii). Prove that the logical sum of all minterms of a Boolean
    function of a 2 variable is 1. (2)
    7. (a) (i) Simplify the following Boolean expression using five
    variable K-map (8)
    (A,B,C,D,E)= (0,2,4,6,9,13,21,23,25,29,31).
    (ii) Simplify the following Boolean function in SOP &POS
    Form (4+4)
    F(A,B,C,D)= (0,1,2,5,8,9,10).

    (OR)
    (b) Explain the design procedure of Full Adder using two Half
    adders and an OR gate? (16)
    8. (a). Draw the schematic and explain the operation of CMOS
    INVERTER with truth table & TRISTATE GATES (8)
    (OR)
    (b) (i) Implement the following function using NOR gates only (8)
    Output=1 when the inputs are m (0, 1, 2, 3, 4)
    Output =0 when the inputs arem (5, 6, 7)





    UNITED INSTITUTE OF TECHNOLOGY
    Periyanaickenpalayam, Coimbatore- 641 020.
    Academic Year - 2013-2014
    Internal Assessment I
    Degree & Branch: B.E &
    ECE- A/ECE-B
    Semester :III
    Date: 0 .08.2013 Time:
    EC2203- DIGITAL ELECTRONICS
    PART-A Max. Marks-50

    (Answer all the Questions) (5 X 2 = 10 Marks)
    1. State Basic Laws & De-Morgan theorem.
    2. What is prime Implicant & Essential prime Implicant?
    3. State the Advantages & Disadvantages of TTL & CMOS Logic.
    4. Find the minterms & Maxterms of the logic expression
    Y=ABC+ABC+ABC.
    5. List out the general characteristics of logic families?

    PART B (40 Marks)
    6. (a) Minimize the given terms
    m(A,B,C,D)= m(1,3,4,5,9,10,11) + d(2,6) using Quine
    Mc-Clusky methods and verify the results using K-
    Map techniques. (16)
    (OR)
    (b) Reduce the following expression
    (i).a AB+ (AC)+ABC (AB+C) &
    (i).b Y= (A+B) (A+C) (B+C) (7+7)
    (ii). Prove that the logical sum of all minterms of a Boolean
    function of a 2 variable is 1. (2)
    7. (a) (i) Simplify the following Boolean expression using five
    variable K-map (8)
    (A,B,C,D,E)= (0,2,4,6,9,13,21,23,25,29,31).
    (ii) Simplify the following Boolean function in SOP &POS
    Form (4+4)
    F(A,B,C,D)= (0,1,2,5,8,9,10).

    (OR)
    (b) Explain the design procedure of Full Adder using two Half
    adders and an OR gate? (16)
    8. (a). Draw the schematic and explain the operation of CMOS
    INVERTER with truth table & TRISTATE GATES (8)
    (OR)
    (b) (i) Implement the following function using NOR gates only (8)
    Output=1 when the inputs are m (0, 1, 2, 3, 4)
    Output =0 when the inputs arem (5, 6, 7)
    EXA/IAQ/01 (01) EXA/IAQ/01 (01)
    EXA/IAQ/01 (01)

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