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    CSM51A F10 Midterm Solutions

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    krazykrnxboy
    The document provides solutions to 6 problems on a midterm exam for a digital logic course. It includes instructions that the exam is closed book, no calculators or laptops are allowed, and collaboration is penalized. It then provides the solutions to 6 problems related to combinational logic design, Boolean algebra, CMOS circuit design, and delay calculation.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    CSM51A F10 Midterm Solutions

    Uploaded by

    krazykrnxboy
    37 views8 pages
    The document provides solutions to 6 problems on a midterm exam for a digital logic course. It includes instructions that the exam is closed book, no calculators or laptops are allowed, and collaboration is penalized. It then provides the solutions to 6 problems related to combinational logic design, Boolean algebra, CMOS circuit design, and delay calculation.

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    Midterm f10 Sols

    Original Title

    Midterm f10 Sols

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    The document provides solutions to 6 problems on a midterm exam for a digital logic course. It includes instructions that the exam is closed book, no calculators or laptops are allowed, and collaboration is penalized. It then provides the solutions to 6 problems related to combinational logic design, Boolean algebra, CMOS circuit design, and delay calculation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    37 views8 pages

    CSM51A F10 Midterm Solutions

    Uploaded by

    krazykrnxboy
    The document provides solutions to 6 problems on a midterm exam for a digital logic course. It includes instructions that the exam is closed book, no calculators or laptops are allowed, and collaboration is penalized. It then provides the solutions to 6 problems related to combinational logic design, Boolean algebra, CMOS circuit design, and delay calculation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    CSM51A F10 Midterm Solutions

    11/01/2010
    Closed book and notes (2 pages cheat sheets allowed)
    No programmable calculators / laptops.
    This is strictly your own work: any form of collaboration will be penalized.
    Name
    ID
    Problem Points Score
    1 20
    2 15
    3 20
    4 10
    5 15
    6 20
    Total 100
    1
    Problem 1
    Given two inputs x, y {0, 1, 2, 3}, design and implement a combinational module which computes x/y, where
    a is the smallest integer b such that b a, e.g. 2.1 = 3, 1.6 = 2. Division by zero cannot happen.
    1. Let x = x
    1
    x
    0
    and y = y
    1
    y
    0
    , write a truth table with input bit ordering x
    1
    x
    0
    y
    1
    y
    0
    .
    Solution
    x
    1
    x
    0
    y
    1
    y
    0
    z
    1
    z
    0
    0 0 0 0
    0 0 0 1 0 0
    0 0 1 0 0 0
    0 0 1 1 0 0
    0 1 0 0
    0 1 0 1 0 1
    0 1 1 0 0 1
    0 1 1 1 0 1
    1 0 0 0
    1 0 0 1 1 0
    1 0 1 0 0 1
    1 0 1 1 0 1
    1 1 0 0
    1 1 0 1 1 1
    1 1 1 0 1 0
    1 1 1 1 0 1
    2
    2. Find the most ecient Nand-Nand or Nor-Nor two level implementations for the network. Assume comple-
    mented inputs are available.
    Solution
    1 - 0 1
    y
    1
    y
    0
    x
    0
    x
    1
    - 0 0 0
    -
    0 0 0
    -
    1 0 0
    -
    1 1 0
    - 0 0 0
    - 1 1 1
    -
    0 1 1
    y
    1
    y
    0
    x
    0
    x
    1
    z
    1
    = x
    1
    (y

    1
    + y

    0
    )(y

    1
    + x
    0
    )
    = x
    1
    x
    0
    y

    0
    + x
    1
    y

    1
    z
    0
    = (x
    0
    + y
    1
    )(x
    1
    + x
    0
    )(x

    1
    + x

    0
    + y
    0
    )
    = x

    1
    x
    0
    + x
    0
    y
    0
    + x
    1
    x

    0
    y
    1
    y
    0

    y
    1

    y
    1

    x
    0
    x
    1

    z
    1
    x
    0
    y
    1
    x
    1
    x
    0
    x
    1

    x
    0

    y
    0
    z
    0
    OR
    z
    0
    x
    1

    x
    0
    x
    0
    y
    0
    x
    1
    x
    0

    y
    1
    z
    1
    x
    1
    y
    1

    x
    1
    x
    0
    y
    0

    OR
    3
    Problem 2
    Analyze the following network and nd the minimized SOP expression.
    x
    4
    x
    3
    x
    2
    x
    1
    x
    0
    Solution
    x
    4
    x
    3
    x
    2
    x
    1
    x
    0
    x
    4
    x
    3
    x
    2
    x
    1
    x
    0

    x
    4
    x
    3
    x
    2
    x
    1
    x
    0

    x
    4
    x
    3
    x
    2
    x
    1
    x
    0
    4
    Problem 3
    1. Find the product of sums form of the following switching function.
    f(a, b, c) = (c(a b))

    + ((c + b) (cb))

    Solution
    f(a, b, c) = (c(a b))

    + ((c + b) (cb))

    = c

    + a b + c b
    = c

    + ab + a

    + cb + c

    = ab + a

    + c

    + b
    = ab + a

    + c

    + b
    = a

    + b + c

    2. What are the minterms of f(a, b, c)? Provide your answer in m-notation.
    Solution

    m(0, 1, 2, 3, 4, 6, 7)
    3. Does f(a, b, c) implement a universal gate?
    Solution
    Yes. f(a, 0, c) = NAND(a, c).
    4. Assume a c = 0. Is f(a, b, c) a universal gate under these conditions?
    Solution
    a c = 0 a = c.
    f(a, b, c) = a

    + b + c

    = a

    + b + a

    = a

    + b
    Yes, f(a, 0, 0) = NOT(a) and f(NOT(a), b) = OR(a, b), giving the set {NOT, OR}, which is universal.
    5
    Problem 4
    Find x and y to satisfy the following equations:
    1. ACB6713D
    16
    = x
    8
    Solution:
    ACB6713D
    16
    = 1010 1100 1011 0110 0111 0001 0011 1101
    2
    = 010 101 100 101 101 100 111 000 100 111 101
    2
    = 25455470475
    8
    = x
    2. 66
    7
    + 88
    9
    = y
    8
    Solution:
    66
    7
    + 88
    9
    = 6 7 + 6 + 8 9 + 8
    = 48 + 80 = 128 = 2 64 + 0 8 + 0 = 200
    8
    = y
    6
    Problem 5
    Design a CMOS circuit which implements the following switching expression:
    z = (a

    + b

    )(a

    + c

    ) + a

    1. Draw a naive CMOS implementation (without simplication).


    Solution: z

    = (ab + ac)(a + b + c).


    2. Simplify the expression rst and draw the new implementation.
    Solution: z = a

    + a

    + a

    + b

    + a

    = a

    + b

    , and z

    = a(b + c).
    V dd
    a b
    a
    b
    z
    a c
    a
    b
    c
    a
    c
    b c a
    (a) naive implementation
    V dd
    a
    b
    z
    b
    c
    a
    c
    (b) simplied implementation
    7
    Problem 6
    Calculate the network delay t
    pLH
    (net) and t
    pHL
    (net) for the following circuit, using the following table of CMOS
    gates characteristics. (Hint: Find out the critical path rst.)
    G 2
    a
    b
    c
    d
    G 1
    G 3
    G 4
    G 5 z
    L z=1
    1.1
    2.0
    Gate t
    pLH
    (ns) t
    pHL
    (ns) Load Factor I
    Nor2 0.06+0.075L 0.07+0.016L 1
    Xor2 0.30+0.036L 0.30+0.021L As Marked
    Solution:
    The critical path is G1 G2 G3 G5.
    t
    pLH
    (c z) = t
    pLH
    (G5) + t
    pHL
    (G3) + t
    pHL
    (G2) + max {t
    pLH
    (G1), t
    pHL
    (G1)}
    = (0.06 + 0.075) + (0.07 + 0.016) + (0.30 + 0.021) + max {0.06 + 0.075 (2 + 1), 0.07 + 0.016 (2 + 1)}
    = 0.8270(ns)
    t
    pHL
    (c z) = t
    pHL
    (G5) + t
    pLH
    (G3) + t
    pLH
    (G2) + max {t
    pLH
    (G1), t
    pHL
    (G1)}
    = (0.07 + 0.016) + (0.06 + 0.075) + (0.30 + 0.036) + max {0.06 + 0.075 (2 + 1), 0.07 + 0.016 (2 + 1)}
    = 0.8420(ns)
    8

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