IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.

2, FEBRUARY 2006 425

A Regulated Charge Pump With Small Ripple

Voltage and Fast Start-Up
Jae-Youl Lee, Member, IEEE, Sung-Eun Kim, Student Member, IEEE, Seong-Jun Song, Student Member, IEEE,
Jin-Kyung Kim, Student Member, IEEE, Sunyoung Kim, Student Member, IEEE, and
Hoi-Jun Yoo, Senior Member, IEEE

Abstract—A regulated charge pump circuit is realized in a load current. To reduce the dependence, the regulated charge
3.3-V 0.13- m CMOS technology. The charge pump exploits an pump was proposed [7]. This charge pump generates constant
automatic pumping control scheme to provide small ripple output output voltage regardless of load current by employing a
voltage and fast start-up by decoupling output ripple and start-up
time. clock blocking scheme blocking an input clock signal when
The automatic pumping control scheme is composed of two the output voltage is higher than the required voltage. Fig. 1
schemes, an automatic pumping current control scheme and shows a conceptual schematic of this charge pump. Using this
an automatic pumping frequency control scheme. The former scheme, constant output voltage with large load current of the
automatically adjusts the size of pumping driver to reduce ripple charge pump can be achieved. However, large ripple voltage
voltage according to output voltage. The latter changes the
pumping period by controlling a voltage-controlled oscillator is incurred due to the clock blocking, especially in case of the
(VCO). The output frequency of the VCO varies from 400 kHz to large load current.
600 kHz by controlling the input bias voltage of the VCO. This paper describes a new regulated charge pump incorpo-
The prototype chip delivers regulated 4.5-V output voltage from rating an automatic pumping control scheme to reduce ripple
a supply voltage of 3.3 V with a flying capacitor of 330 nF, while voltage while delivering large load current. The proposed
providing 30 mA of load current. The area is 0.25 mm2 and the
measured output ripple voltage is less than 33.8 mV with a 2- F regulated charge pump generates approximately 4.5-V output
load capacitor. The power efficiency is greater than 70% at the voltage and 33.8-mV ripple voltage with 30-mA load current.
range of load current from 1 to 30 mA. An analytical model for In Section II, the steady state and dynamic analysis of the con-
ripple voltage and recovery time is proposed demonstrating a rea- ventional regulated charge pump are described to develop the
sonable agreement with SPICE simulation results. output ripple voltage generation processes and output voltage
Index Terms—Automatic pumping control, large load current, recovery time. In Section III, a new charge pump is proposed
regulated charge pump, small ripple voltage. to reduce ripple voltage and decrease the recovery time of the
output voltage. To verify the function of the proposed charge
I. INTRODUCTION pump, the charge pump is analyzed by dynamics with state
equations. Experimental results are provided and discussed in

I N MANY semiconductor devices, such as DRAM,

EEPROM, and switched-capacitor transformers, charge
pumps are frequently used to provide voltage higher than a
Section IV. Finally, conclusions are presented in Section V.

II. CONVENTIONAL REGULATED CHARGE PUMP

power supply because high voltage level in a charge pump is
generated by transferring charge to a capacitive load, without In the conventional regulated charge pump, the clock
any amplifiers or regular transformers [1]. Many charge blocking scheme is adopted to isolate the output voltage level
pump approaches have focused on the design of the Dickson from the value of a load resistor, which determines the load
charge pump, such as [2]–[4], since the conventional applica- current. Although its average output voltage has a constant
tions have required a high voltage with only limited current value regardless of load resistor, large output ripple voltage is
drive capability. However recent applications like USB-OTG generated during the pumping and blocking periods.
(On-The-Go) not only require a high voltage level, but also The operation of clock blocking is shown in Fig. 2. The output
require high current drive capability [5]. load capacitor is charged only during pumping period and dis-
According to [6], output voltage of the charge pump de- charged through the load resistor continuously. If the pumping
creases as load current increases. The dependence prevents period is much shorter than the blocking period, output ripple
the charge pump from generating high voltage with high voltage at the load capacitor during the pumping period [4] is
determined by

Manuscript received December 26, 2004; revised October 4, 2005. (1)

J.-Y. Lee is with the Advanced DDI Design Team, System LSI Division, Sam-
sung Electronics, Yongin 449-711, Korea (e-mail: [email protected]).
S.-E. Kim and J. K. Kim are with the Basic Research Laboratory, Electronics where is the pumping current into the flying capacitor
and Telecommunications Research Institute, Daejeon 305-700, Korea. during the pumping and blocking periods which is equal to
S.-J. Song, S. Kim, and H.-J. Yoo are with the Division of Electrical Engi- in a steady state, is the output load capacitance, and
neering, Department of Electrical Engineering and Computer Science, Korea
Advanced Institute of Science and Technology, Daejeon 305-701, Korea. is the switching frequency between the pumping and blocking
Digital Object Identifier 10.1109/JSSC.2005.862340 periods.
0018-9200/$20.00 © 2006 IEEE
426 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

Fig. 1. Conceptual schematic of a conventional regulated charge pump.

Fig. 2. Operation of a regulated charge pump.

To reduce output ripple voltage, voltage variation during the where is the maximum gained voltage at the flying capac-
pumping and blocking periods should be minimized. During the itor, and (2) is expressed by the number of clock cycles. Large
pumping period, it is clear that either small pumping current is essential in reducing the rise time. However, it creates
or large output load capacitor or high switching frequency is large ripple voltage in a steady state, because it increases the
required to achieve small ripple voltage. However, in practice, charge at load capacitor during the pumping period. Therefore,
changing the load capacitor value is difficult when this value is in a dynamic state, during the pumping period should be
given in a specification, and reducing the charge pumping ability maximized for fast rise time, and in a steady state, minimized
may lose load current supplying capability. Therefore, in order for small ripple voltage.
to reduce the output ripple, control of the pumping current and
switching frequency, according to the load current, is required.
During the blocking period, turning off the operation of the III. PROPOSED REGULATED CHARGE PUMP
charge pump causes a relatively large voltage drop. Therefore, A. Automatic Pumping Current Control Scheme
another novel scheme rather than the blocking scheme is re-
quired. The proposed charge pump exploits the automatic pumping
It is important to decrease the rise time for the robustness of current control scheme; it changes pumping current according
the output voltage. If the charge pump has a fast rise time in a to the magnitude of the output voltage. At the low output
power-up state, fast recovery time is also shown after the output voltage, the proposed charge pump uses large pumping current
voltage drops abruptly. Using dynamic analysis of charge pump, to rapidly increase output voltage. On the other hand, at the
rise time [3], output voltage raises to the required voltage high output voltage, it reduces boosting power by turning
level, is derived as off some of pumping drivers. Fig. 3 shows the reduction of
output ripple voltage in the automatic pumping current control
scheme, compared to the clock blocking scheme. In case of
the conventional regulated charge pump, the output voltage
(2) is independent of the load resistance and has large ripple
voltage because it always pumps the flying capacitor with full
power. However the proposed charge pump using the automatic
(3) pumping current control scheme create a small ripple voltage
with output voltage independent of load resistance.
LEE et al.: A REGULATED CHARGE PUMP WITH SMALL RIPPLE VOLTAGE AND FAST START-UP 427

Fig. 3. Reduction of output ripple voltage in automatic pumping control.

Fig. 4. Proposed charge pump.

The automatic pumping current control scheme is realized by positive feedback of M10 and M11 to accomplish hysteresis. It
three functional blocks; a main charge pump (MCP), an output detects output voltage levels of 4.5, 4.8, and 5 V.
level detector (OLD), and an automatic driver (ADR), as shown The ADR optimizes the pumping current by adjusting the
in Fig. 4. The operation of the MCP is to charge the load capac- number of buffers using the output value of the OLD, since the
itor. The OLD senses the output voltage level and generates con- pumping current in (1) determines the ripple voltage. The opera-
trol signals for the ADR. By using resistor chain, scaled values tion of the ADR according to output voltage is shown in Fig. 6.
of output voltage are compared to the reference voltage of 0.7 V When output voltage is low, the ADR provides full pumping
in each comparator. The voltage reference and the comparator current to the flying capacitor and as output
are shown in Fig. 5(a) and (b), respectively. voltage rises, the pumping current delivered to the flying capac-
The bandgap reference voltage generator generates an output itor is stepwise reduced down to .
voltage of 1.2 V and the reference voltage of 0.7 V is generated
using a voltage divider. It adopts a self-biased cascade struc- B. Automatic Pumping Frequency Control Scheme
ture [8] to reduce the effect of supply voltage variations and To further reduce output ripple voltage, the proposed charge
can effectively remove switching noise. The comparator has two pump also exploits the automatic pumping frequency control
feedback paths: the negative feedback of M1 and M2, and the scheme that has been developed in previous works [9], [10].
428 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

Fig. 6. Simulation result of the proposed charge pump.

Fig. 7. Relationship between clock frequency and ripple voltage in the

proposed charge pump.

2) Parasitic capacitance is negligibly small compared with

the charge pump capacitance.
The pumping current of the proposed charge pump is
Fig. 5. (a) Comparator. (b) Voltage reference. expressed as

In (1), the switching frequency of the charge pump is related (4)

to the output ripple voltage. The switching frequency is equal
to the pumping clock frequency because the proposed charge
where is the pumping current delivered by each buffer in the
pump repeats the current pumping on every clock cycle, while
ADR, and is the index number of operating buffers which are
the conventional charge pump with the clock blocking scheme
operated by the output value of the OLD. The ripple voltage is
continues to charge the load capacitor during the pumping pe-
obtained from (1) as
riod and stops during the blocking period. This switching fre-
quency is larger than the pumping clock frequency. Fig. 7 shows
the relationship between the output ripple voltage and the clock (5)
frequency. As (1) implies, the ripple voltage is inversely pro-
portional to the switching frequency. The block diagram for The pumping current is equal to that of the load resistor in a
the automatic pumping frequency control is shown in Fig. 4. steady state. As load current increases, the output voltage level
A voltage-controlled oscillator (VCO) generates a clock signal, decreases, and the number of operating buffers increases.
linearly determining the switching frequency. After the output Fig. 8 shows the dependence of the ripple voltage on the
voltage is detected, a bias block compares the voltage divided by load current and the switching frequency under the condition of
resistors with the reference voltage and linearly converts that to V and F. The output ripple voltage is pro-
the control voltage of the VCO. The operating clock frequency portional to the load current and inversely proportional to the
of the charge pump changes from 400 kHz to 600 kHz as output pumping clock frequency.
voltage rises. It is important to guarantee the fast recovery of the output
voltage after the output voltage drops abruptly. In order to model
C. Analysis of Proposed Charge Pump the recovery time, Thevenin equivalent circuit for this charge
pump is derived from a large signal model in a steady state
To reduce the output ripple voltage and the recovery time after and then the time constant of output node is calculated from
the drop in output voltage, a at each cycle is controlled the output resistance and capacitance of the equivalent circuit.
according to output voltage. To analyze the proposed charge Fig. 9(a) shows the operation of the proposed charge pump in
pump, the following assumptions are made: steady state. The currents and flow through and
1) The diode has constant forward bias voltage drop in the pumping period and the blocking period, respectively. If
when the diode is on. the resistances of and are sufficiently smaller than the
LEE et al.: A REGULATED CHARGE PUMP WITH SMALL RIPPLE VOLTAGE AND FAST START-UP 429

Fig. 8. Comparison of the analytical result with the SPICE simulation for the
ripple voltage.

those of and is or and changes

linearly as shown in Fig. 9(b) since and operate in triode
region. The current and can be obtained from the current
equation of MOSFET in a triode region as

Fig. 9. (a) Operation of the proposed charge pump. (b) Timing diagram of
V and V .
(6)
the charge flowing into load resistance for and the charges
stored in the capacitors and at time .

(7)

where and are the averages of in the pumping (11)

period and the blocking period, respectively.
In a steady state, the output current is equal to the currents (12)
supplied by and for half cycle time
because the does not change according to clock From (10) and (12)
cycle, and assuming and

(13)

By differentiating (6) and using (13)

(9)

(10)

(14)
According to the charge conservation law, the total charge
stored in the circuit at time is equal to the sum of
430 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

Fig. 10. Comparison of the analytical result with SPICE simulation for
recovery time.

From (14), the relationship between the variations of and

is expressed as
Fig. 11. Microphotograph of proposed charge pump.

(15)

represents the equivalent output series resistance of the

proposed charge pump and is dependent on the electrical char-
acteristics, the dimensions of transistors and the gate voltage.
The recovery time that gets back up to 63% of is the time
constant .
Fig. 10 shows the comparison of the analytical result with
the SPICE simulation for the recovery time as a function of the
size of driver buffer under the condition of V
V and F. The analytical data have been in good
agreement with the SPICE simulation results. Fig. 10 indicates
that the recovery time does not depend on the switching fre-
quency and , and is inversely proportional to the width
of the pMOS . Therefore, the recovery time of the pro-
posed charge pump compared to the conventional charge pump Fig. 12. Measurement results of output voltage.
decreases by stepwise increasing the size of the driving buffer
when the output voltage reduces below the specified voltages.
Fig. 12 shows that the output ripple voltage is 33.8 mV with
the automatic pumping control scheme when the load current is
IV. EXPERIMENTAL RESULTS 30 mA and the output voltage is 4.5 V. The rise time and fall time
The approach of the proposed charge pump is focused on of the output voltage are equal to each other since the pumping
producing small output ripple voltage while delivering large operation is performed on every clock cycle and the clock duty
load current. To validate the results of our schemes, the pro- cycle is 50%. In the conventional charge pump, these times are
posed charge pump was fabricated using 3.3-V 0.13- m CMOS different because the charge pump stops pumping operations
technology as the power supply circuit in an USB-OTG trans- until the output voltage drops lower than the required output
ceiver. The microphotograph is shown in Fig. 11. Its active area voltage level.
is 0.25 mm except for a 330-nF external flying capacitor. On Fig. 13 shows the measured output and the ripple voltage
the bottom right side, the pumping MOS diodes are designed versus the load current. A set of measurements has been per-
as large as possible to supply enough load current. The output formed by changing the value of the variable load resistor con-
stage of the proposed charge pump is composed of a variable nected to the output. As load current increases, output voltage
load resistor and a 2- F load capacitor mounted on a test PCB. gradually drops to 4.5 V and output ripple voltage changes from
LEE et al.: A REGULATED CHARGE PUMP WITH SMALL RIPPLE VOLTAGE AND FAST START-UP 431

Fig. 13. Measurement results of output and ripple voltage as a function of load Fig. 15. Measurement results of output and ripple voltage as a function of
current. clock frequency.

TABLE I
PERFORMANCE SUMMARY OF THE PROPOSED CHARGE PUMP

output voltage and the output ripple voltage is inversely pro-

portional to the pumping clock frequency at a load current of
Fig. 14. Measurement results of power efficiency. 30 mA. In a steady state, output ripple voltage shows a linear
triangle wave as shown in Fig. 12. Although clock frequency is
18 mV to 33.8 mV. The ripple voltage is proportional to load changed, output voltage increase during a positive clock phase
current. However, the difference between the measured ripple equals to the decrease during a negative clock phase. Therefore,
voltage and the SPICE simulation result shown in Fig. 8 in- the output voltage is not affected by frequency change.
creases as the load current increases because the simulation re- Table I summarizes the performance characteristics of the
sult does not include the noise caused by parasitic components. proposed charge pump.
The leakage current was through the pMOS used as SW1 in
Fig. 9(a). This can also increase ripple voltage. V. CONCLUSION
Power efficiency of a charge pump [11] is shown as A new regulated charge pump with low output ripple voltage
and high load current drive capability is proposed enhancing
(16) tolerance of the output voltage variation. This proposed charge
pump adopts the automatic pumping current control scheme
The corresponding result is higher than 70% regardless of load and automatic pumping frequency scheme. The analysis of the
current, as shown in Fig. 14. When the load current becomes charge pump is carried out to model the ripple voltage and the
smaller, the dynamic power loss caused by switching large tran- recovery time. The proposed charge pump is implemented using
sistors does not change and the ratio of the power loss over the a 3.3-V 0.13- m CMOS technology. The test chip generates
output power increases. As a result, the power efficiency de- 4.5-V output from a 3.3-V supply with supplying up to 30 mA of
grades as load current decreases. load current. Its ripple voltage is less than 33.8 mV with a 2- F
To verify the effect of the pumping clock frequency on the load capacitor. The power efficiency is higher than 70% at the
output voltage and the output ripple voltage, the VCO is turned range of load current from 1 mA to 30 mA. The proposed charge
off and an external clock is applied as a pumping clock. Fig. 15 pump is used as the power supply circuit in the USB-OTG trans-
shows that the pumping clock frequency does not influence the ceiver.
432 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

ACKNOWLEDGMENT Seong-Jun Song (S’01) received the B.S. (summa

cum laude) and M.S. degrees in electrical engineering
The authors would like to thank Samsung Electronics Corpo- and computer science from the Korea Advanced In-
ration for the test chip and test PCB fabrication. stitute of Science and Technology (KAIST), Daejeon,
Korea, in 2001 and 2004, respectively. He is currently
working toward the Ph.D. degree in electrical engi-
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Jae-Youl Lee (M’00) received the B.S. degree in Hoi-Jun Yoo (M’95–SM’05) graduated from the
metallurgical engineering from Hanyang University, Electronic Department of Seoul National University,
Seoul, Korea, in 1992, and the M.S. and Ph.D. Seoul, Korea, in 1983, and received the M.S. and
degrees in materials science and engineering from Ph.D. degrees in electrical engineering from the
the Korea Advanced Institute of Science and Tech- Korea Advanced Institute of Science and Technology
nology (KAIST), Daejeon, Korea, in 1994 and 1999, (KAIST), Daejeon, in 1985 and 1988, respectively.
respectively. His Ph.D. work concerned the fabrication process
From 1999 to 2003, he was with a DRAM design for GaAs vertical optoelectronic integrated circuits.
group at Hynix Semiconductor and designed a family From 1988 to 1990, he was with Bell Communi-
of SDRAMs. In 2003, he was a visiting Professor cations Research, Red Bank, NJ, where he invented
with KAIST. He joined Samsung Electronics, Korea, the two-dimensional phase-locked VCSEL array,
and has been involved in the development of high-speed serial interface from the front-surface-emitting laser, and the high-speed lateral HBT. In 1991,
2004. he became Manager of a DRAM design group at Hyundai Electronics and
designed a family of fast-1M DRAMs and synchronous DRAMs, including
256M SDRAM. From 1995 to 1997, he was a faculty member with Kangwon
National University. In 1998, he joined the faculty of the Department of
Electrical Engineering at KAIST, and led a project team on RAM Processors
(RAMP). In 2001, he founded a national research center, System Integration
Sung-Eun Kim (S’04) was born in Busan, Korea, and IP Authoring Research Center (SIPAC), funded by Korean government
in 1978. He received the B.S. degree in electrical to promote worldwide IP authoring and its SOC application. Currently, he
and computer engineering from Hanyang University, serves as the Project Manager for IT SoC and Post-PC in Korea Ministry
Seoul, Korea, in 2002, and the M.S. degree in of Information and Communication. His current interests are SOC design,
electrical engineering and computer science from the IP authoring, high-speed and low-power memory circuits and architectures,
Korea Advanced Institute of Science and Technology design of embedded memory logic, optoelectronic integrated circuits, and
(KAIST), Daejeon, Korea, in 2004. novel devices and circuits. He is the author of the books DRAM Design (Seoul,
He subsequently joined the Basic Research Korea: Hongleung, 1996; in Korean) and High Performance DRAM (Seoul,
Laboratory of Electronics and Telecommunications Korea: Sigma, 1999; in Korean).
Research Institute (ETRI), Daejeon. Since then, he Dr. Yoo received the Electronic Industrial Association of Korea Award for
has been engaged in the research and development his contribution to DRAM technology in 1994 and the Korea Semiconductor
of MEMS switch driver and intrabody communication system. Industry Association Award in 2002.