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Bio-Inspired Imprecise Computational Blocks for Efcient VLSI Implementation of Soft-Computing Applications
H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas
AbstractThe conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efcient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efciently implement a three-layer face recognition neural network and the hardware defuzzication block of a fuzzy processor. Index TermsBio-inspired, face recognition, fuzzy processor, imprecise computational blocks, neural networks, very-large-scale integration.

I. INTRODUCTION ANY of the existing scientic and engineering problems are solved using deterministic, precise, and explicit models and algorithms. These rigorous techniques that are known as hard-computing are normally used to solve a category of problems with similar properties such as high precision, predictability, and strict analysis [1]. These well-known and well-developed techniques are widely used to solve some of the existing engineering problems. However; these are in conict with two frequent observations [2]. The rst is that most of the real-world applications and problems are naturally imprecise and with low degrees of certainty while the second one is that using higher precision than the minimum necessary imposes higher implementation cost. The soft-computing paradigm uses the above two guiding principles [2] as its fundamental base to enhance the traditional hard-computing problem-solving strategy. Soft-computing is an evolving collection of methodologies, which aim to exploit tolerance for imprecision, uncertainty, and partial truth to

achieve robustness, tractability, and low cost [1]. Soft-computing methodologies are very popular today, because they have formed a major stream in practice of modern articial intelligence. Neural networks (NN), fuzzy logic, and evolutionary computing are the core methodologies of soft-computing. Looking at the number of publications on various combinations of these three methods and their applications, it is concluded that the soft-computing methodologies have already been advantageous in numerous areas [1]. We introduce an important problem associated with conventional implementations of soft-computing systems in Section II. In Section III, we present our proposal to alleviate the problem and deliver more efcient implementations at improved cost and speed. Sections IV and V include the simulation and synthesis results to show how our solution can be applied to efciently implement a three-layer NN for face recognition as well as a defuzzication block that is used in a fuzzy inference engine. The last section concludes the paper. II. PROBLEM DESCRIPTION All soft-computing methodologies are based on the fact that most of the real-world applications and problems tolerate some natural imprecision and embody some degrees of uncertainty [2]. Therefore, it is not recommendable to develop and use deterministic, explicit, and precise models and algorithms to solve such problems. On the other hand, it is a fact that practical soft-computing applications are mostly implemented using digital hardware [3][12] that is based on binary logic with high degree of predictability and precision. A key problem arises here while a naturally precise and certain implementation bed should be used to realize the methodologies that are intrinsically relaxed to have higher imprecision and uncertainty. This conict suppresses the main advantage of the soft-computing methodologies (i.e., their inherent tolerance to accommodate some imprecision and uncertainty) when they are implemented using conventional digital hardware. The analog implementations of the soft-computing applications try to solve this problem by choosing a more relaxed implementation bed. An analog implementation is more efcient in terms of chip area, processing speed, and power consumption while this comes at the price of its limited accuracy with respect to its digital rivals [12][16]. However; digital technology has some unique features that prevent it to be replaced by analog implementations. Digital ICs are reliable, drift-free, and relatively noise immune, and have a repeatable and predictable behavior

Manuscript received December 28, 2008; revised May 02, 2009. First published December 31, 2009; current version published April 09, 2010.This paper was recommended by Asssociate Editor S. Callegari. H. R. Mahdiani is with the School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran, and also with the Computer and Electronics Department, Sh. Abbaspour University of Technology, Tehran 16589-53571, Iran (e-mail: [email protected]). A. Ahmadi, S. M. Fakhraie, and C. Lucas are with the School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identier 10.1109/TCSI.2009.2027626

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[17]. Also the digital design process is simple and straightforward [11], [14] and there are many advanced digital system development tools that can be used to design complex digital systems with hundreds of millions of transistors. Furthermore, for analog implementation of a NN, there are several other issues to deal with [18] such as choosing a compatible training algorithm, nonvolatile weight storage and restoration, non-ideal response, and variations of the analog computational blocks [15], [18], [19]. The nanoelectronics, quantum, and molecular computing are the other most likely directions of the system development technologies [20][23]. However; it takes a long time to practically use them in commercial products. The next section introduces our proposed solution that helps to reconcile the discussed conict without abandoning the digital realm. III. THE SOLUTION: USING BIO-INSPIRED IMPRECISE COMPUTATIONAL BLOCKS (BICS) CONCEPT Human brain as an intelligent computing entity has been a good inspiration source for development of some important articial intelligence concepts such as NN and fuzzy computations. One of the important brain paradigms is that the collective behavior of the nature-made computational units in the brain when responding to computationally intensive tasks is such that it is less sensitive to the detail behavior of individual blocks. As a result, the total system continues to function properly despite possible imprecision or even failure in some computational units. This implies that from the implementation viewpoint, although the brain as a whole guaranties to preserve tremendous degrees of precision, performance, and reliability even in inconvenient situations, it is implemented using low precision neurons that perform their internal imprecise computations through transfer of ions across the cell membranes [24]. The inspiration that follows this paradigm is that it is not mandatory to use fully-precise and completely-deterministic building blocks for the implementation of bio-inspired systems. This inspiration from the nature-made computational blocks, relaxes the design process of the traditional human-made computational building blocks that might lead to different benets such as decreased complexity and cost, or increased speed and performance. As an instance in digital VLSI territory, a designer might utilize some irregular adders and multipliers that are intentionally relaxed to provide an approximation of the computation result instead of its precise value. This relaxation also might imply decreased implementation costs of these bio-inspired computational blocks (BICs) in terms of area, delay, and power consumption with respect to the traditional precise components. A traditional computational block (that provides the precise results of the computations) is entirely described with its physical properties or synthesis results such as area, delay, and power consumption. However; as a BIC structure provides approximations of the computations instead of their precise values, a complete description of a BIC should also include its error behavior (in addition to its synthesis results) that evaluates its result approximation approach. To clearly dene the error behavior of a BIC structure, it is recommendable to represent or map its output results imprecision into some well known and well dened criteria. Some of the most useful error denition criteria that might

be utilized to evaluate a BIC structure consist of: Probability of Error (PE) that indicates the probability of producing an erroneous result, Mean output Error (ME), mean relative error, Mean Squared output Error (MSE), MAXimum output error (MAX), and MINimum output error (MIN) [25]. All these factors are computable with comparison to the output results of a similar precise structure. This can be achieved performing some analytic studies or running some simulations. Error behavior denition of a BIC is important because it guides us to properly design or pick suitable BIC structures for different application areas. For example, an imprecise adder structure which has a high PE is introduced in the next section. Although it mostly provides a different result with respect to a precise adder, it has a low output ME. The experimental results show that this adder might be efciently used to implement a computationally intensive NN. We introduce efcient instances of bio-inspired imprecise adders and multipliers. The error behavior and also synthesis results of the introduced imprecise adder and multiplier structures are discussed and compared with traditional precise ones. To provide the error simulation results of the individual BIC structures, the bit-true C models of the introduced blocks are prepared and added to our previously developed C Finite-Length Arithmetic Modeling Extension (C-FLAME) [26] bit-true modeling library. In addition, the error behavior of each BIC structure is presented using some analytic equations that are veried using C-FLAME simulation results. The synthesis results of the BIC structures are also presented by introducing an analytic study that is compared by practical synthesis results. To show the applicability as well as the efciency of the introduced BIC structures as a reliable approach for hardware implementation of soft-computing applications, we used them to successfully implement a three-layer face-recognition NN and the defuzzication block of a hardware fuzzy processing engine as two challenging cases. Instead of extensive further simulations, we sufce to the above two crucial applications and point out the following arguments. The genetic algorithm eld does not involve any computations and is mainly based on random number generation. In fuzzy eld, the fuzzy control is the most practical aspect of the fuzzy theory. The fuzzy control mostly consists of three distinct processes, fuzzication, fuzzy inference, and defuzzication. The defuzzication process in Mamdani fuzzy control is crucial among the others because of its high computational power demand with respect to fuzzication and fuzzy inference processes [5]. In NN eld, the face-recognition benchmark discussed in the paper is a typical example of a computationally-intensive application and can be considered as a critical case analysis. Generally, if the computational load is not too demanding, then the need for hardware realization is not the rst choice. A. A Bio-Inspired Imprecise Adder: Lower-Part-OR Adder 1) Lower-Part-OR Adder Structure Description: Addition is a fundamental operation that can signicantly inuence the overall achievable performances [27]. The Lower-part-OR Adder (LOA) divides a -bit addition into two -bit and -bit . As shown in Fig. 1, a -bit LOA exsmaller parts ploits a regular smaller precise adder (is called sub-adder) that

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Fig. 1. Hardware structure of the Lower-part-OR Adder (LOA).

computes the precise values of the most signicant bits of the result (upper-part) along with some OR gates that approximate the least signicant result bits (lower-part) by applying bitwise OR to the respective input bits. An extra AND gate is used to generate a carry-in for the upper part sub-adder when the most signicant bits of both lower-part inputs are one. This helps to take into account the trivial carries from lower to upper parts of the LOA adder to decrease its imprecision. The sub-adder might have any desired precise structure such as carry look-ahead or ripple-carry adder, while using more efcient precise adders [27], [28] as the sub-adder directly leads to more efcient LOA. For a LOA with a constant Word-Length (WL or ), higher or Lower-Part Length (LPL) values decrease the area, delay, and power consumption of the LOA while at the same time increase its imprecision. The error behavior and also the synthesis results of the LOA is presented and discussed in the following. 2) Lower-Part-OR Adder Error Behavior: The rst parameter that might be useful to know about the LOA is that how often it provides an erroneous result (PE) as described in (1): (1) Equation (1) shows that in a LOA, the error probability is independent of the WL and only depends on LPL. Fig. 2 shows that how fast the PE grows with increasing the LPL. It shows that for the LPL values of 2 and 8, the LOA provides about 40% and 90% erroneous results with respect to a precise adder of the same WL. Therefore, the LOA is not suitable to be used in applications that are sensitive to the number of errors regardless of their relative magnitude. Although the LOA seems not to be a useful structure at the rst glance based on its high number of erroneous results, it is important to discover more about the distribution and statistics of its error values. Equations (2) and (3) explain the maximum and minimum differences between the outputs of a LOA and a precise adder of the same WL. As shown by equations, the LOA provides both larger and also smaller results with respect to a precise adder based on its input values. Therefore, an important feature of the LOA is that it has a nearly unbiased and symmetric for signed output error range between or unsigned additions (2) (3)

Fig. 2. Probability of producing an erroneous result by LOA for different LPL values.

Equation (4) demonstrates the mean output error of the LOA based on our analytic studies and simulation results. As another good feature, it shows that an LOA with any desired WL and LPL, provides a constant mean output error (that does not depend on the WL or LPL). This is achieved due to the symmetric output error range of the adder. Also the slightly negative bias of the ME value is due to the inequality that exists between MAX and MIN as shown in (2) and (3) (4) The mean squared error of the LOA is described using (5) . It shows that the MSE grows exponentially with for increasing of LPL (5) 3) Lower-Part-OR Adder Synthesis Results: Using the unit-gate model [29], [30], (6) and (7) describe and gate-delay the gate-count complexities of LOA in general. The signicance of these equations lies in their generality. They show that the gate-count and gate-delay of a WL-bit LOA depends on WL and LPL values, as well as the gate-count and gate-delay of its precise sub-adder with the length of WL-LPL (WL minus LPL) bits. They also show that in general, higher LPL values lead to smaller and faster LOAs with respect to the precise adder of the same WL

(6) (7) The unit-gate model is chosen because it perfectly reects the structure of the complex gates such as adders and multipliers by modeling their basic individual logic operators and so is commonly used in literature [30]. Comparison of the unit-gate model area/delay results with precise transistor-level synthesis results [31] show that this model yields acceptable relative accuracy at a high abstraction level using only simple analytic calculations [30]. To support these general analytic studies with a specic

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Fig. 3. LOA area for different WL and LPL values.

Fig. 5. (a) Hardware structure of the Broken-Array Multiplier (BAM), (b) CSA cell, and (c) vector merging adder cell.

B. A Bio-Inspired Imprecise Multiplier Structure: Broken-Array Multiplier (BAM) 1) Broken-Array Multiplier Structure Description: Fig. 5(a) demonstrates the basic structure of a 6 6 broken-array multiplier (BAM) which is very similar to the structure of an array multiplier. An Array multiplier with a -bit multiplicand and -bit multiplier array multiplier similar cells called carry-save adder (CSA) consists of array whose cells are shown by squares, followed by a -bit vector merging adder (whose cells are shown by rounded squares) to convert the carry-save redundant form into regular binary format [34]. Each cell contains a 2-input AND gate that forms partial product and a full-adder (CSA) to add the partial product into the running sum [35]. Fig. 5(b) illustrates the internal gate-level structure of each CSA array and also vector merging adder cell [35]. The rst row CSA cells in Fig. 5(a) however; might be replaced with only one AND or NAND gate. A BAM breaks the CSA array and omits some cells that lead to a smaller and faster circuit while provides approximate results. As shown in Fig. 5(a), the number and position of the omitted cells (that are hatched) depend on two introduced parameters: Horizontal Break Level (HBL) and Vertical Break means that there is no horizontally Level (VBL). The omitted CSA cell. Increasing the HBL, moves the horizontal dashed line downward and all cells that fall above the dashed do not omit any CSA line are omitted. Similarly the cells while as the VBL increases, the vertical dashed line moves left and all separated right-side cells are omitted. The respective output values of the all omitted cells are considered to be null. A similar technique might be applied to other multipliers such as Wallace-tree and Booth encoding structures to build new imprecise multipliers. Although our main focus is on unsigned multiplication, the basic structure and operation of the signed and unsigned BAM are the same [35]. Their main difference is that in an unsigned BAM all the CSA cells are identical and can be omitted based

Fig. 4. LOA delay for different WL and LPL values.

real case study, Figs. 3 and 4 demonstrate our practical synthesis results of a LOA with ripple-carry sub-adder, for different WL and LPL parameter values when they are synthesized with 0.13 CMOS technology library cells using Leonardo Spectrum synthesis tool. In both gures, a LOA with zero LPL value corresponds to a precise ripple carry adder of the same WL. Increasing LPL above zero reduces the length of the sub-adder that results in decreased area and delay of the whole LOA. Fig. 3 shows that for different WLs, the LOA gate-count decreases between 21 to 31 gates as LPL increases by 1 unit. Fig. 4 also demonstrates 0.16 to 0.55 ns reduction in LOA delay with 1 unit increment of the LPL parameter. Considering LOA power consumption, a brief analytic study shows that it consumes less power with respect to a precise adder. The dynamic power consumption of a circuit which dominates its total power dissipation [32] is given by [33] (8) is the load capacitance, is where is the activity factor, the supply voltage, and is the clock frequency. Therefore, as LOA has lower gate count as indicated before, it has lower total with respect to a precise adder of the same WL. At the same time, as the LOA lower-part is constructed using lower activity . OR gates, it also has smaller activity factor

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Fig. 6. Probability of producing erroneous result by BAM for different HBL . and VBL values when

WL = 10

WL = 10

Fig. 7. BAM mean relative error for different HBL and VBL values when .

on HBL/VBL values while in a signed BAM, the CSA cells that operate on the sign bits of the partial products are not omitted at all to preserve the correct result sign. Therefore, increasing the HBL/VBL in an unsigned BAM leads to higher number of omitted CSA cells with respect to a signed BAM. 2) Broken-Array Multiplier Error Behavior: The accuracy of the BAM depends on three parameters: WL, HBL, and VBL. The simulation results show that increasing both HBL and VBL imply higher number of erroneous results while the HBL value has greater effects on the number of incorrect results than that of VBL. Fig. 6 demonstrates the probability of producing an erroneous result (PE) by BAM structure based on the values of HBL and VBL when . It shows that when HBL and VBL are and the BAM provides 100% correct results both zero, and corresponds to a precise array multiplier completely. The maximum and minimum differences between the output of a BAM and a precise multiplier of the same WL are determined by (9) and (10). They show that a BAM always provides smaller results with respect to a precise multiplier of the same WL

of 1 and 2, the output error of the BAM is less than 1% of the precise result. The simulation results show that HBL values of 1 or 2 are acceptable for most applications with different WLs

(11)

(9) (10) Equation (11) shows the mean error of the BAM in terms of WL, HBL, and VBL. To have a better understanding about the mean error values, Fig. 7 also demonstrates the mean relative error values of the BAM (in %) for and different HBL/VBL parameter values. The relative error is computed by dividing the BAM output error by the precise result of the computation [25]. Fig. 7. shows that a BAM with corresponds to a precise multiplier and provides a zero mean error. As the VBL and HBL increase, the relative ME of the BAM increases with different rates. For a constant HBL, increasing the VBL does not affect the BAM mean relative error and as a result mean error signicantly. On the other hand, increasing the HBL itself by one unit, greatly affects the multiplier mean relative error. The gure shows that for the HBL values

3) Broken-Array Multiplier Synthesis Results: Based on the analytic studies, (12) to (15) demonstrate the gate-count and gate-delay complexities of signed and unsigned BAM with and bit multiplicand and multiplier respectively. The equations are correct when HBL and VBL are less than . They show that the physical properties of a BAM depend on the size of the multiplicand and multiplier (m and n), HBL and VBL values, and nally the gate-count and gate-delay of its m-bit vector merging adder. It can be concluded that higher HBL/VBL values result in smaller and faster BAM structures. These equations also show that changing HBL has higher effects on area/delay of both signed and unsigned BAM with respect to VBL. As HBL has also greater effects on the error factors of BAM (as discussed before), the HBL and VBL should be treated as the coarse and ne tuning parameters of the area, delay, and precision of BAM respectively. Comparison of the gate-count and gate-delay equations of the signed and unsigned BAM also shows that for an unsigned BAM, increasing the HBL and VBL causes higher reductions in gate-count and delay with respect to its corresponding signed architecture

(12)

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Fig. 8. BAM area for different HBL and VBL values when

WL = 10.

Fig. 9. BAM delay for different HBL and VBL values when

WL = 10.

IV. USING BIC FOR VLSI IMPLEMENTATION OF A THREE-LAYER NEURAL NETWORK This section contains the simulation and synthesis results to show the efciency of using the introduced BIC structures for VLSI implementation of a computationally-intensive face-recognition three-layer NN. A. BIC Implementation of a Neural Network for Face Recognition Application The main objective of different implementations of a NN is to optimize three main constraints: accuracy, area, and processing speed [15] while preserving the scalability and exibility of the network. In a digital VLSI implementation, the physical properties of a network tightly depend on cost, speed, and power consumption of the neurons. The most important factor that affects both the precision and physical properties of an individual neuron is its internal Word-Length (WL). Lower WLs lead to smaller and faster neurons. There are many reports on determining the efcient WL of different NN structures for different applications [15], [37]. The suitable WL of a NN depends on many parameters such as network structure, its number of layers and neurons, number of inputs, the application context, and its training method [15]. Our implemented NN is a three-layer network that is used for face-recognition application [38]. It consists of eight internal-layer neurons each with 960 inputs (and the same number of synaptic weights) that correspond to different pixels of a 32 by 30 grayscale photo. It also includes nine output neurons to determine different features of the input subject photo: the users identication number (four neurons to encode 13 different persons), expression (two neurons to encode four different situations, sad, happy, angry, and neutral), users head direction (two neurons to encode left, right, up, and straight), and if the user is wearing sunglasses or not (one neuron) [38]. The network is trained using back-propagation algorithm and with chip-in-the-loop approach [15]. The BIC model is prone for introducing new sources of imprecision. Therefore, using the chip-in-the-loop approach, the NN will also learn some of these imprecision sources and adjust the weights appropriately to account for them [18]. Also the network is considered to work properly only when it provides correct values (for all of its nine

(13)

(14)

(15) To verify the discussed analytic studies about physical properties of BAM, Figs. 8 and 9 demonstrate the practical synthesis results of a 10 10 unsigned BAM with a ripple-carry vector merging adder for different HBL and VBL parameter values. The synthesis library is that of a 0.13 CMOS technology. They verify that increasing HBL provides higher area and delay reduction than VBL. The gures show that the precise multiplier (that corresponds to a BAM with zero HBL and VBL) has the highest area and delay. As VBL and HBL grow above zero, BAM gains good area/delay savings with respect to the precise multiplier. As to power consumption of the BAM, experimental results are not reported here. However; there is some previous work showing that preventing an array multiplier of always performing a full-length multiplication greatly reduces its power consumption [32], [36]. As a result, the BAM that always eliminates some part of the multiplication (based on the HBL/VBL values) is expected to yield some power reduction. Also as an analytic proof, as BAM has fewer number of gates with respect to a precise array multiplier, it has lower overall and so based on (8) it has lower power capacitance consumption.

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output neurons) for all of the testing and training patterns. The next two subsections compare the simulation and synthesis results of the network with BIC and with precise computational blocks to show that the BIC model of the NN is capable of tracking the behavior of a normal model while delivers lower implementation cost and higher performance. B. Simulation Results Two different C language bit-true models of the discussed NN are developed using C-FLAME. The rst C model which is named precise or normal model consists of conventional adders and multipliers while the second C model is made using LOA and BAM structures and is called imprecise or BIC model. The Word-Length (WL) is the single controllable parameter of the normal model while the BIC model has three more parameters, namely LPL, HBL, and VBL. Choosing optimal value for WL in the precise model as well as four parameters of the BIC model (according to accuracy constraints of the application) [39], is a critical task that greatly affects performance, hardware cost, and power consumption [40]. It is possible to analytically determine the optimized parameter values of some simple systems however; when dealing with a complex nonlinear system, simulation is a more convenient and more feasible method [39], [41]. To have a fair comparison, two types of C simulation results are provided to observe and compare the external behavior as well as the internal activities of the two NN models. To observe the external behavior of the NNs, it sufces to determine if they are able to correctly recognize all features of all of the testing and training photos or not. However; it is more important to compare the internal activities of the two models to show that the BIC model can trace the internal behavior of the precise model correctly. To demonstrate the internal behavior of the networks, two different factors are measured, number of necessary training epochs (TE) to achieve the correct results and the network remaining mean squared error (MSE). The TE determines the convergence speed while the MSE stands for the convergence precision of the NN. The network MSE is determined as the average MSE values of the network outputs for all testing and training patterns based on [42]

Fig. 10. Precise model behavior due to changes in WL.

(16) where and are the number of output neurons and input patterns respectively. The training phase is stopped if either the network MSE becomes less than a dened Epsilon (0.001) or the TE takes longer than a MAX EPOCH (100). The rst conrms the network has strongly detected all features of the input photos while the latter assumes that continuing the training does not improve the network MSE any more. Fig. 10 shows the external as well as the internal behavior of the precise NN model for different WLs. The gray area in the diagram denotes the faulty external behavior of the network and

species some areas in which the network provides at least one error. The network works properly in the white areas. and are two According to Fig. 10, the critical points of the simulation. For the network fails to recognize at least one pattern. On the other side, increasing WL to more than 13 bits, does not improve any of the network internal activity indicators (MSE and TE#). Increasing WL from 9 to 13 does not improve the network MSE signicantly and only causes the network to converge faster with fewer training leads to the smallest and fastest epochs. Therefore, VLSI implementation of the network that correctly recognizes all of the input photos while its training convergence speed is not optimized. If the designer tends to achieve the best convergence speed, he should increase the WL to 13 and pay its extra cost and speed penalties. leads to the most efcient normal implemenWhile tation of the NN, the simulation results of the BIC model of the same WL show that it is able to track the external as well as the internal behaviors of the precise model of the same WL. Equations (6), (7), (14), and (15) show that choosing higher LPL, HBL, and VBL values decreases the cost and increases the speed of the BIC structures and the resulting NN model. However; increasing each of these parameters implies introducing higher imprecision in the corresponding BIC component and as a result adding higher errors inside neurons that might ultimately cause a neuron or the network to fail. Therefore, the maximum acceptable values of these parameters are limited and should be determined through simulations. Figs. 1113 indicate the internal/exwith respect ternal behavior of the BIC model when to changes in only one of its parameters (LPL, HBL, and VBL) while the two other parameters do not introduce any imprecision and are ineffective or zero. Again, the gray area in each diagram denotes the faulty external behavior of the network and species the regions that the network fails due to the intolerable amount of imprecision. The gures also imply that the LPL, HBL and VBL should be less than or equal to 4, 2, and 6 respectively. In such cases, the MSE and TE curves show that the BIC model tracks the precise model activities with negligible difference. It even sometimes provides better MSE values and less TE# due to the nonlinearity of the NN. However, it should be mentioned that increasing the value of each parameter limits the maximum allowable values of the two others. It means that increasing the imprecision in one of the BIC

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TABLE I ERROR VALUES AND SYNTHESIS RESULTS OF THE PRECISE (P#1) AND BIC (B#1 TO B#3) MODELS WHEN

WL = 9

0, and VBL = 0.

Fig. 11. BIC model behavior due to changes in LPL when

WL = 9 HBL =
;

Fig. 14. Sequential architecture for VLSI implementation of a NN.

0, and VBL = 0.

Fig. 12. BIC model behavior due to changes in HBL when

WL = 9 LPL =
;

where stands for precise and for BIC models. The fth and sixth table columns include the MSE and TE# simulation results of the precise and BIC models. It shows that B #1 and B#3 provide the best TE# and MSE among the others. The difference between MSE of the precise and anyone of the BIC models is that is negligible. Although the BIC in order of maximum models provide similar MSE values, their main difference lies in their synthesis results which are discussed in the following section. C. Synthesis Results The face recognition NN might be implemented in several different ways such as fully-combinational, fully-sequential, or any other combination between these two extremes. In a fullysequential implementation of a neural network, there exists only one hardware neuron that is scheduled to sequentially perform the computations of all neurons of the network one by one. In this paper, the fully-sequential structure that is shown in Fig. 14 is used to implement the NN both with normal and BIC components. Its data-path and critical-path consist of a single multiplier and an adder. The precise model is built using an array multiplier and a ripple-carry adder (RCA) while the BIC model exploits a BAM and a LOA. The sub-adder of the LOA, and the vector-merging adders of the multipliers in both models are RCAs. The three last columns of Table I include the critical-path delay delay, data-path area without registers, and area product for the precise and BIC models. The second row shows the synthesis results of the precise model. The following rows demonstrate the physical properties of the BIC model for some of its best parameter combinations as discussed. The table values show the synthesis results of the models on 0.13 CMOS technology library cells using Leonardo Spectrum synthesis tool. Table values show that the normal implementation of the NN has respectively 12%, 20%, and 30% higher clock periods than BIC implementations while it also needs higher number of gates. Table values show that the precise model has 30%, 54%,

0, and HBL = 0.

Fig. 13. BIC model behavior due to changes in VBL when

WL = 9 LPL =
;

components inside the neuron, limits the amount of the tolerable imprecision in other BIC components. In other words, there is a correlation between the acceptable imprecision levels in different BIC components of a system that are determined by nal values of these three parameters. Therefore, a nal concurrent analysis is necessary to consider this correlation and simultaneously examine the allowable values of these parameters. Table I includes the error simulation results of the precise and . The results of the BIC model are BIC models when presented for some of its best acceptable combinations of the LPL, HBL, and VBL parameters in which the BIC model works properly. The rst column determines the type of the model

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and 101% higher delay, area, and area delay product with respect to the BIC#1 while both of them recognize properly and have similar internal behaviors. As another instance, the precise model has about 20% longer critical path delay, 43% delay product with higher gate count, and 72% worse area respect to the BIC#2 as another suitable parameter combination of the BIC model. As a conclusion, the BIC implementation of the NN lead to some hardware with lower costs and higher speeds with respect to a normal implementation while their external behavior are entirely the same and there are only some differences in their internal activities and their number of training epochs. The complementary simulation and synthesis results show that if we choose a WL more than 9, the area, delay, and power efciency of the BIC over precise model improves more. Also choosing other implementation methods (such as combinational) or other adder/multiplier structures to implement the NN does not affect the natural efciency of the BIC over normal implementation. However; they might lead to different combinations of the BIC model parameters due to their different synthesis results. V. USING BIC FOR VLSI IMPLEMENTATION OF THE DEFUZZIFICATION BLOCK OF A FUZZY PROCESSOR In this section, we show that how the introduced BIC sample structures might be exploited to enhance the realization cost and speed in VLSI implementation of the defuzzication block [5] as one of the critical issues in almost any fuzzy set theory application. A. BIC Implementation of the Defuzzication Block The main operation of the defuzzication process in a fuzzy system is to provide the linguistic to numeric conversion [43] that makes it possible to bind the fuzzy outputs of the system to common sensors and actuators. The most popular defuzzication method is the true Center Of Gravity (COG) [43]. It is the preferred method for most applications because of its unique features such as high precision and continuous and smooth change of its crisp output due to the continuous change of the controller inputs [44]. However, the most important drawback of this method is its high computational power demand and as a result implementation cost [45]. Therefore, there are a wide range of other defuzzication methods with less computational power demands and also less output accuracies [43]. Most of these new methods should be viewed as the simplied COG methods. In other words, the new methods are proposed to trade a piece of precision with reduced implementation cost and complexity [5] while they remain yet applicable. From the fuzzy control perspective, a defuzzication method is applicable whenever it can be used to solve a practical problem [43]. We observe that this cost-precision trade is similar to the same idea that is used in BIC. The main difference between these two concepts is that different defuzzication methods try to enhance the solution by reducing the precision at algorithmic level while the BIC reduces the precision at implementation level. Therefore, it is convenient to use BIC for the hardware implementation of different defuzzication methods as demonstrated below.

Fig. 15. Basic weighted-average structure for implementing different defuzzication methods.

Fig. 16. Plateau Midpoint and Height of a membership function which are used to compute the WPA defuzzied output.

Most of the existing defuzzication methods such as COG, Center Of Sum, Plateau Average, Weighted Plateau Average (WPA), Trapezoid Median Average (TMA), Trapezoidal Weighted TMA, and Rectangular Weighted TMA use a similar approach based on (17) to compute a weighted average of the fuzzy number membership functions as the defuzzied output [5] (17) In the above equation, is the number of output memberand are some specications ship functions, and of the th membership function which are determined by each defuzzication method. According to (17) the major difference between these defuzzication methods lies in their input and weight values. Fig. 15 illustrates a common hardware structure of all these methods which can be used to implement (17). To provide an accuracy analysis of the defuzzication block using normal or BIC arithmetic blocks, it is necessary to focus on one of the above defuzzication methods. The WPA is picked because it is widely used in existing hardware fuzzy processors [5] due to its simple hardware implementation. In this method, the nal defuzzied output value is computed as the weighted average of the midpoints of all fuzzy output plateaus based on [5] (18) where is the number of output membership functions. Conforming (18) to the basic infrastructure of Fig. 15 and to (17) shows that the input and the weight in WPA are the plateau midand the height of the th memberpoint ship function respectively. Fig. 16 demonstrates that how the Midpoint and Height of a general membership function shape is determined. B. Simulation Results Two different C language bit-true models of the WPA are developed using bit-true C-FLAME library facilities and compo-

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Fig. 17. Selected output membership function test cases. Fig. 18. MAE, AEV and MAX of the precise model with different WLs.

nents. The rst model which is named precise or normal model consists of some conventional precise adders and multipliers while the second model is made using LOA and BAM structures and is called imprecise or BIC model. The Word-Length (WL) is the single adjustable parameter of the normal model while the BIC model has three other parameters, that is LPL, HBL, and VBL. The target of this section is to show that the BIC model is able to track the behavior of the normal model with negligible (and also controllable) difference while has lower cost and higher performance. To have a fair comparison, three different error criteria are measured and compared for both models: Mean Absolute Error (MAE), Absolute Error Variance (AEV) and MAXimum absolute error (MAX) that are computed based on

(19)

(20)

(21) In the above, is the total number of fuzzy numbers, is the accurate center of gravity of the th fuzzy number (that is computed using the true COG method as the base of comparison for error measurements) and the represents the center of gravity estimation that is provided by the bit-true precise or imprecise WPA model that is under simulation. To more elaborate on the achieved results, the MAE, AEV, and MAX factors show the mean, variance, and maximum absolute change of the center of gravity with respect to the whole fuzzy number width (FuzzyWidth) in percentage. To generalize the results, three different output fuzzy membership function sets with different properties and from different application areas [46] are selected as the test case on which the simulations are run. Fig. 17 illustrates the shapes of these membership function sets. As shown in the gure, these sets cover regular and irregular as well as triangular and trapezoidal membership functions to achieve more general simulation results.

Fig. 18 shows the MAE, AEV and MAX curves of the precise bit-true model (PRE) with different WLs. The horizontal and vertical axes demonstrate the WL and error percentage respectively. There are two important notes about the curves. The rst note is that increasing the WL more than six bits, does not affect any of the error factors signicantly. So a WL of at least six is suitable for hardware implementation of WPA. The second observation that points to an important fact is that in contrast to the expectation that increasing the WL results in lower errors, all three error factors increase as the WL increases between 6 . This and 10 and then saturate to a constant value for occurs because the defuzzication output is formed by the division of two accumulation results as shown in (18). Although the error of the individual aggregations decreases and each saturates at a constant limit by increasing the WL, difference in the saturation rates for the numerator and denominator accumulations causes the discussed undesired uctuations. This phenomenon might cause more signicant uctuations in case of BIC implementation due to their inherently added imprecision. So the defuzzication should be considered as a critical case that reveals the efciency or weaknesses of using BIC structures. Organizing the simulations for the BIC model is not as straightforward as for the precise model due to its higher number of parameters. Different approaches might be exploited to explore the BIC model parameter space and extract appropriate values for its four available parameters. In the previous section, we used a concurrent approach that simultaneously determines all the parameter values of the BIC structures which are used to implement the NN. In this section we introduce and use an iterative approach that determines and xes the parameters one by one based on their effect on system error and/or physical properties. According to this approach, parameters that have greater effects should be xed earlier (the coarse tuning) while the less effective parameters are used for further ne tuning. In defuzzication problem, the simulation results show the suitable order for xing the parameters of the BIC model as rst WL, then LPL, HBL and VBL. Although choosing higher LPL, HBL and VBL values lead to faster and smaller BIC components and as a result defuzzication block, the maximum values of these parameters are limited by the application. As our discussion in this paper is to generally show the efciency of the BIC units regardless of the application context, the parameter values are chosen in a manner to highly preserve the same error levels as those of the precise WPA with less than 1% relaxation that is suitable for most applications.

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Fig. 19. MAE, AEV and MAX of the precise and BIC models for different LPLs while ; and .

WL = 6 HBL = 0 VBL = 0

Fig. 21. MAE, AEV and MAX of the precise and BIC models for different VBLs while ; and .

WL = 6 LPL = 2 HBL = 1

TABLE II THE PHYSICAL PROPERTIES AND ERROR FACTORS OF PRECISE AND BIC MODELS OF THE WPA DEFUZZIFICATION METHOD WITH DIFFERENT PARAMETER VALUES

Fig. 20. MAE, AEV and MAX of the precise and BIC models for different and . ; HBLs while

WL = 6 LPL = 2 VBL = 0

To determine the WL while all other parameters are inactive (zero values for LPL, HBL and VBL that imply using precise adders and multipliers), the same results of the precise simula. tions are achieved (Fig. 18) that is The LPL is the next parameter that should be tuned with inactive HBL and VBL values (i.e., inserting only the imprecise adder into design rst). The results show that for any desired WL, the LPL values of WL-4 and WL-5 lead to less than 1% and 0.3% worse mean and variance errors with respect to the precise WPA model of the same WL. For example when (Fig. 19), the BIC model provides 0.9% and 0.2% higher MAE, AEV and MAX errors for LPL values of 2 and 1 respectively. As the LPL increases above 2, the difference between BIC and precise model errors grows to about 5%. Fig. 20 demonstrates the HBL simulation results when , and VBL is ineffective or zero. It shows that for and , the mean and variance errors of the imprecise WPA are less than 0.8% and 1.2% higher than those of is suitable to provide the precise WPA. Therefore, the less than 1% difference. , and , Fig. 21 shows the With simulation results of the imprecise WPA with different VBLs. If we increase the VBL up to ve, the mean and variance of the errors of the imprecise model increase by only 0.63% and 0.85% with respect to the precise WPA and the maximum error increases by 4%. As a conclusion, , and determine an optimum point of the BIC model in which, the error behavior of the BIC model tracks that of the precise model very closely (with less than 1% difference) while it is more efcient and has lower cost as shown next.

After choosing some optimum points of the parameter space for the BIC model, these results are then used along with the synthesis results of the implied model to guide the designer through choosing the best precision-cost-performance trade-off as shown in the next sub-section. C. Synthesis Results Table II includes the synthesis results of the WPA precise and BIC models in some optimum points of the parameter space when synthesized with 0.13 CMOS library cells using Leonardo Spectrum synthesis tool. The rst column determines the type of the model (P for precise and B for BIC models). The last three columns of the table show area, delay, and delay product of each model respectively. The error area simulation results for each optimum point are also included in the table for clear comparison. There are some considerations about the table values. According to Fig. 15, the defuzzication block critical path consists of a multiplier and an adder. Also its datapath consists of a multiplier; two adders and a divider. We set the divider aside because it works with much lower frequencies with respect to other components (the division frequency is related to the number of the output membership functions) and might be implemented in different styles with different area/delay trade-offs. To provide the numeric synthesis results, the precise model is built using an array multiplier with Ripple-Carry (RCA) merging adder, and

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two other RCA adders. In a similar way, the BIC model consists of a BAM with RCA merging adder and two LOAs (with RCA sub-adders). The second and third rows of Table II include the experiand 7 respecmental results of the precise model with tively. The next rows contain the results of the BIC model with different WL, LPL, HBL, and VBL values. The results show that all the imprecise models provide much better clock frequencies and implementation areas with respect to the precise model of the same WL while have slightly lower accuracy. As an example, the BIC#1 and BIC#3 instances provide less than 0.8% and 1.1% worse average and variance errors with respect to the precise model of the same WL (P#1) while have 35% and 54% higher clock frequencies. Also the hardware implementation of delay product of about 130% the precise model has an area and 220% higher than BIC#1 and BIC#3 models respectively. A more interesting observation is that the P#1 provides 37% delay product with respect to two BIC and 68% higher area models with higher WL (B#5 and B#6) while their accuracy factors are quite similar. VI. CONCLUSION A new category of bio-inspired approximate hardware arithmetic blocks with enhanced implementation cost and performance is introduced. The BIC structures provide an estimation of the result instead of its precise value while are smaller, faster, and consume less power with respect to the conventional precise blocks. As case studies, two bio-inspired imprecise adder and multiplier structures are introduced. The error behavior and synthesis properties of these novel structures are discussed and presented. The applications of these BIC structures are then introduced in fuzzy and neural network elds. The simulation and synthesis results are provided that show these blocks can be exploited to efciently implement the WPA defuzzication method as well as a three-layer computationally-intensive neural network for face recognition application at reduced cost. REFERENCES
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Ali Ahmadi received the B.Sc. degree in computer engineering from the University of Isfahan, Isfahan, Iran, in 2006, and the M.Sc. degree in computer architecture from the University of Tehran, Tehran, Iran, in 2009. His research interests are fault-tolerant design of digital systems and Neural Networks, digital testing, and recongurable architectures.

Sied Mehdi Fakhraie was born in Dezfoul, Iran, in 1960. He received the M.Sc. degree in electronics from the University of Tehran, Tehran, Iran, in 1989, and the Ph.D. degree in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada, in 1995. Since 1995, he has been with the School of Electrical and Computer Engineering, University of Tehran, where he is now an Associate Professor. He is also the Director of Silicon Intelligence and the VLSI Signal Processing Laboratory. From September 2000 to April 2003, he was with Valence Semiconductor Inc. and has worked in Dubai, UAE, and Markham, Canada ofces of Valence as Director of application-specic integrated circuit and system-on-chip (ASIC/SoC Design) and also technical lead of Integrated Broadband Gateway and Family Radio System baseband processors. During the summers of 1998, 1999, and 2000, he was a Visiting Professor at the University of Toronto, where he continued his work on efcient implementation of articial neural networks. He is coauthor of the book VLSI-Compatible Implementation of Articial Neural Networks (Kluwer, 1997). He has also published more than 120 reviewed conference and journal papers. He has worked on many industrial IC design projects including design of network processors and home gateway access devices, Digital Subscriber Line (DSL) modems, pagers, and one- and two-way wireless messaging systems, and digital signal processors for personal and mobile communication devices. His research interests include system design and ASIC implementation of integrated systems, novel techniques for high-speed digital circuit design, and system-integration and efcient VLSI implementation of intelligent systems.

Hamid Reza Mahdiani was born in Neyshabour, Iran, in 1976. He received the B.Sc. degree in computer engineering, and the M.Sc. degree in computer architecture from University of Tehran, Iran, in 1998 and 2001, respectively. Since 2004, he has been pursuing the Ph.D. degree in computer engineering with the School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran. Since 2004, he has been a Research Associate and Lab Manager with the Silicon Intelligence and VLSI Signal Processing Laboratory, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran. From 2004, he has also worked as an instructor with Computer and Control Department, Sh. Abbaspour University of Technology, Tehran, Iran. His research interests include VLSI design of data communication and articial intelligence systems, low-power and fault tolerant design in nano-level CMOS.

Caro Lucas received the M.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1973 and the Ph.D. degree from the University of California, Berkeley, in 1976. He is a Professor at the Center of Excellence for Control and Intelligent Processing, School of Electrical and Computer Engineering, University of Tehran, as well as a Researcher at the Intelligent Systems Research Faculty (ISRF), Institute for Studies in Theoretical Physics and Mathematics (IPM), Tehran, Iran. His research interests include biological computing, computational intelligence, uncertain systems, intelligent control, neural networks, multi-agent systems, data mining, business intelligence, nancial modeling, and knowledge management.