Verilog HDL Syllabus

Verilog HDI
EE 499-3 / 599-3
CS 499-3 / 599-3

Course Coordinator: Dr. Mike Ellis

Instructor: Brad Olsen
Phone: 233-4690 x7137 (AMI Semiconductor)
E-mail: bolsenamis.com
Class Web Page(s):
http://www2.elen.utah.edu/bolsen/verilog/index.htm
http://www.mosIet.isu.edu/classes/EECS499Veriloghdl/index.htm

Class Hours: Mon/Wed - 3 to 4:15 PM
Iocation: BA 412

OIIice Iocation: TBD
OIIice Hours: TBD

Prerequisites
EE/CS 374, and some programming experience (II you`re enrolled in the class
and do not meet the prerequisites, please talk to me).

Text
Required: Verilog HDI, A Guide to Digital Design and Synthesis, 2
nd
ed., Samir
Palnitkar.
ReIerence: Cadence Verilog-XI ReIerence (Available on class web page).

SoItware
There are two options Ior soItware:
o Students may use the Xilinx ISE 6 / ModelSim tools on their PC at home.
I have copies oI the soItware that I can provide. Xilinx requires
registration Ior a ModelSim license (Iree).
o Students may use the Cadence tools in the VISI/UNIX lab at Colonial
Hall.
I will provide in-class training Ior the Xilinx/ModelSim tools. I will schedule a
time to provide training Ior the Cadence tools.
You are welcome to use other soItware. But, I will only be able to answer
questions about the Xilinx ISE 6 / ModelSim soItware or the Cadence soItware
tools.

Grading
Homework and design project (50), 2 mid-term exams (15 each), Final Exam
(20).
Graduate students are required to complete an additional design project exercise
that will count toward their overall homework and design project score.
Grade breakdown:

o 100 90 A
o 89 80 B
o 79 70 C
o 69 60 D
o Below 60 E

Homework Assignments
You are welcome to share ideas with each other on the homework and project
sections, but each student is responsible to write their own Verilog code. A loss
oI points will result iI it is determined that a student is copying another student`s
code.
The Iirst Iive homework assignments will be Irom the textbook.
The remaining homework assignments will be sections Irom a design project.
InIormation on the design project will be provided at a later time.
All homework assignments shall be submitted via e-mail on the day they are due.

Homework Grading
For the Iirst Iive homework assignments, I will grade one problem at random out
oI the assigned set. However, I expect you to do each problem and will deduct
points Ior incomplete assignments.
For the project sections, your score will be based on the how well your simulation
output compares to the correct simulation output Ior each project section. Any
mismatches in simulations will result in a loss oI points. I will do my best to
determine the source oI the errors (iI any) in your code, but I will not spend a lot
oI time debugging your code.

Exams
2 mid-term exams will be held during normal class times. The Iinal exam will be
per University schedule.
Class Outline (topics may vary Irom exact dates):

Date Topic Due
1/12/04 Introduction and Ievels oI Abstraction
1/14/04 Verilog Module and Hierarchical Design Concepts
1/19/04 No Class (Martin Luther King Day)
1/21/04 Simulation Demonstration HW |1
1/26/04 Basic Concepts Iexical Conventions
1/28/04 Basic Concepts Data Types HW |2
2/2/04 Basic Concepts - System Tasks and Compiler Directives
2/4/04 Modules and Ports HW |3
2/9/04 Gate Ievel Modeling
2/11/04 DataIlow Modeling HW |4
2/16/04 No Class (President`s Day)
2/18/04 1
st
Mid-Term Review HW |5
2/23/04 1
st
Mid-Term
2/25/04 Synthesis Demonstration
3/1/04 Project Introduction and Overview
3/3/04 Operators Project Sections 1, 2, 3
3/8/04 Behavioral Modeling Procedures and Timing Controls
3/10/04 Behavioral Modeling Conditional Statements Project Sections 4, 5
3/15/04 No Class (Spring Break)
3/17/04 No Class (Spring Break)
3/22/04 Behavioral Modeling Ioops
3/24/04 Behavioral Modeling Procedural Blocks Project Sections 6, 7
3/29/04 Tasks and Functions
3/31/04 2
nd
Mid-Term Review
4/5/04 2
nd
Mid-Term
4/7/04 RTI and Testbench Modeling Techniques Project Section 8
4/12/04 RTI and Testbench Modeling Techniques
4/14/04 RTI and Testbench Modeling Techniques Project Section 9
4/19/04 Timing and Delays Path Delay Modeling
4/21/04 Timing and Delays Timing Checks Project Section 10
4/26/04 Switch Ievel Modeling
4/28/04 User-DeIined Primitives Project Section 11
5/3/04 Final Review 1
5/5/04 Final Review 2 Project Section 12
(Grad. Students Only)
Week oI
5/10/04

Final Exam (Time/Date per University Schedule)

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