CD74HC238
CD74HC238
CD74HC238
Features
Select One Of Eight Data Outputs Active Low for 138, Active High for 238 l/O Port or Memory Selector Three Enable Inputs to Simplify Cascading Typical Propagation Delay of 13ns at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
[ /Title (CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8) /Subject (High Speed
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 (PDIP, SOIC) TOP VIEW
A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 (Y7) Y7 7 GND 8 16 VCC 15 Y0 (Y0) 14 Y1 (Y1) 13 Y2 (Y2) 12 Y3 (Y3) 11 Y4 (Y4) 10 Y5 (Y5) 9 Y6 (Y6)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
Ordering Information
PART NUMBER CD74HCT138E CD74HC238E CD74HCT238E CD74HC138M CD74HCT138M CD74HC238M CD74HCT238M CD74HC138SM NOTES: 1. When ordering, use the entire part number. Add the sufx 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SSOP PKG. NO. E16.3 E16.3 E16.3 M16.15 M16.15 M16.15 M16.15 M16.209
Ordering Information
PART NUMBER CD74HC138E TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld PDIP PKG. NO. E16.3
Functional Diagram
HC/HCT HC/HCT 238 138 A0 A1 3 A2 12 Y3 4 E1 5 E2 E3 6 9 Y6 7 Y7 Y7 Y6 10 Y5 Y5 11 Y4 Y4 Y3 13 Y2 Y2 1 2 15 14 Y0 Y1 Y0 Y1
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Dont Care TRUTH TABLE CD74HC238, CD74HCT238 INPUTS ENABLE E3 X L X H H H H H H H H E2 X X H L L L L L L L L E1 H X X L L L L L L L L A2 X X X L L L L H H H H ADDRESS A1 X X X L L H H L L H H A0 X X X L H L H L H L H Y0 L L L H L L L L L L L Y1 L L L L H L L L L L L Y2 L L L L L H L L L L L OUTPUTS Y3 L L L L L L H L L L L Y4 L L L L L L L H L L L Y5 L L L L L L L L H L L Y6 L L L L L L L L L H L Y7 L L L L L L L L L L H
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
VCC (V)
-4
4.5
3.98
3.84
3.7
0.02
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
0 0 -
100
0.1 8 360
1 80 450
1 160 490
A A A
NOTE: Unit Load is ICC limit specied in DC Electrical Table, e.g., 360A max at 25oC.
SYMBOL
2 4.5
13 -
150 30 26
190 38 33
225 45 38
ns ns ns ns
CL = 15pF CL = 50pF
5 6
(Continued) 25oC VCC (V) 2 4.5 6 MIN TYP 67 MAX 150 30 26 75 15 13 10 -40oC TO 85oC MIN MAX 190 38 33 95 19 16 10 -55oC TO 125oC MIN MAX 265 53 45 110 22 19 10 UNITS ns ns ns ns ns ns pF pF
SYMBOL
TEST CONDITIONS
2 4.5 6
Power Dissipation Capacitance, (Notes 5, 6) Input Capacitance HCT TYPES Propagation Delay Address to Output
CPD CIN
CL = 15pF -
5 -
14 67 -
35 35 40 15 10
44 44 50 19 10
53 53 60 22 10
ns ns ns ns ns pF pF
Enable to Output HC/HCT138 Enable to Output HC/HCT238 Output Transition Time (Figure 2) Power Dissipation Capacitance, (Notes 5, 6) Input Capacitance NOTES:
tPLH, tPHL CL = 50pF tPLH, tPHL CL = 15pF tTLH, tTHL CL = 50pF CPD CIN CL = 15pF -
5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
GND
tTHL
INVERTING OUTPUT
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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