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    Arm Datasheet

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    Milena Novato Silva
    Arm Datasheet

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    Arm Datasheet

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    Arm Datasheet

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    Arm Datasheet

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    117 views8 pages

    Arm Datasheet

    Uploaded by

    Milena Novato Silva
    Arm Datasheet

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    ARM SIMULATOR (v4.6.10.

    0) SPRS397- Aug 2007


    features

    Integrated with Code Composer Studio with unified loader support for both Microsoft Windows and Linux platforms Pin connect for injecting interrupts to peripherals Advanced profiling Ease of configuring the simulator through enhanced Code Composer Studio setup Full instruction set architecture for ARM11, ARM9e, Cortex M-3, and Cortex R-4 simulators Endianness (Little, Big, BE-8: byte invariant; and BE-32: word invariant) Cycle count accurate simulator (but specific for ARM968 simulator) Protocol memory compliant interfaces (but specific for Cortex M-3 and ARM968 simulator)

    description ARM simulators are available with the Code Composer Studio for ARM based devices. The complete instruction set is modeled for ARM11, ARM9e, Cortex M-3, and Cortex R-4 simulators. ARM simulators support device level features such as, profiling, cycle accuracy, pin or port connect, and simulator analysis. ARM simulators have been validated for correctness. ARM968 simulator has been validated for cycle accuracy against cycle accurate simulators provided by ARM. Functional device simulators (ARM 11, Cortex M-3, and Cortex R-4) for ARM based devices model the functionality of peripherals without accounting for cycle effects. They are fast and can be used for application validation and cache analysis.

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    summary of architecture features Table 1.
    FEATURE

    Architecture Features
    ARM968 CORTEX R-4 CORTEX M-3

    ARM11

    Cycle count accurate Protocol compliant memory interface Exception model Memory Protection Unit

    2 2 3 -

    3 3 3

    2 2 3

    2 3 3 3

    summary of simulator configurations Table 2.


    DEVICE SIMULATED CCS CONFIGURATION

    Simulator Configurations
    CYCLE ACCURACY SPEED IN MIPS SPEED IN MCPS

    ARM11

    ARM968 Cortex M-3 Cortex R-4

    Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Big Endian [BE-8]

    2 2 2 3 3 2 2 2 2 2 2

    3.5 3.5 3.5 0.59 0.59 0.59 3.05 3.05 3.05

    1.85 1.85 -

    1) Refer to table 7 for details.

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    summary of capabilities Table 3.
    CCS CONFIGURATION CYCLE ACCURACY

    Capabilities of Simulator Configurations


    CACHE TUNE PROFILER COMPILER CONSULTANT CODE SIZE TUNE PIN/PORT CONNECT SIMULATOR ANALYSIS

    ARM11

    ARM968

    Cortex M -3

    Cortex R-4

    Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Big Endian [BE-8]

    2 2 2 3 3 2 2 2 2 2 2

    2 2 2 2 2 2 2 2 2 2 2

    3 3 3 3 3 3 3 3 3 3 3

    2 2 2 2 2 2 2 2 2 2 2

    2 2 2 2 2 2 2 2 2 2 2

    3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2

    2 2 2 2 2 2 2 2 2 2 2

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    summary of events Table 4.
    CCS CONFIGURATION DEVICE CYCLES

    Events Supported
    STALL EVENTS INSTRUCTION RELATED EVENTS

    CPU CYCLES

    ARM11

    ARM968

    Cortex M-3

    Cortex R-4

    Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Little Endian Big Endian Big Endian [BE-8] Little Endian Big Endian Big Endian [BE-8]

    2 2 2 3 3 2 2 2 2 2 2

    2 2 2 3 3 2 2 2 2 2 2

    2 2 2 2 2 2 2 2 2 2 2

    3 3 3 3 3 3 3 3 3 3 3

    peripherals supported Table 5.


    MODULE ARM11

    Peripherals Supported
    ARM968 CORTEX R-4 CORTEX M-3

    AHBLite slave memory model Memory Protection Unit

    2 2

    3 -

    2 2

    3 3

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    pins supported Table 6.
    PIN NAME ARM11

    Pins Supported
    CORTEX R-4 CORTEX M-3

    ARM968

    IRQ FIQ NMI ISR_0 ISR_1 ISR_2 ISR_3 ISR_4 ISR_5 ISR_6 ISR_7

    3 3 -

    3 3 -

    3 3 -

    2 2 3 3 3 3 3 3 3 3 3

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    performance numbers Table 7.
    SIMULATOR CONFIGURATION TEST CASE

    Performance Numbers
    MIPS MCPS

    ARM968 (Flat memory)

    g723_arm9 g729_arm9 gsm51_arm9 gsmAMR_arm9 Gsmefr_arm9 mpeg4_arm9 wbamr_arm9

    g723_arm9 g729_arm9 gsm51_arm9 ARM968 (AHBLite compliant gsmAMR_arm9 memory interface) gsmefr_arm9 mpeg4_arm9 wbamr_arm9 g723_arm-m3 g729_arm-m3 gsm51_arm-m3 Cortex M-3 gsmAMR_arm-m3 gsmefr_arm-m3 mpeg4_arm-m3 wbamr_arm-m3 g723_thumb g729_thumb gsm51_thumb Cortex R-4 gsmAMR_thumb gsmefr_thumb mpeg4_thumb

    0.62 0.60 0.60 0.60 0.60 0.60 0.60 2.82 2.76 2.80 2.91 2.79 2.51

    3.92 2.59 3.75 3.63 3.71 2.98 3.81 2.00 1.86 2.51 2.02 1.81 1.07 2.28

    wbamr_thumb 2.80 2) All benchmarks were Run on Windows machines with P4 Processor and 1 GB RAM

    ARM SIMULATOR (v4.6.10.0) SPRS397- Aug 2007


    references ARM968 Technical reference manual http://www.arm.com/pdfs/DDI0311D_arm968es_r0p1_trm.pdf ARM11 Technical reference manual http://www.arm.com/pdfs/DDI0360D_arm11mpcore_r1p0_trm.pdf Cortex M-3 Technical reference manual http://www.arm.com/pdfs/DDI0337D_cortexm3_r1p1_trm.pdf Cortex R-4 Technical specification manual http://www.arm.com/products/CPUs/ARM_Cortex-R4.html

    glossary Cycle Accuracy acronyms MIPS MCPS MPU Million instructions per second Million cycles per second Memory protection unit Correlation between cycles reported by simulator versus the real hardware

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