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    To View An RTL Schematic: Sources Tab

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    binhnhi0007
    The document discusses how to view an RTL schematic in Vivado and provides examples of VHDL code for basic logic gates and circuits including AND gates, OR gates, and a 4-1 multiplexer. It also lists some VHDL design exercises including logic gates, 2-bit adders, decoders, and BCD to 7-segment decoders.

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    To View An RTL Schematic: Sources Tab

    Uploaded by

    binhnhi0007
    33 views5 pages
    The document discusses how to view an RTL schematic in Vivado and provides examples of VHDL code for basic logic gates and circuits including AND gates, OR gates, and a 4-1 multiplexer. It also lists some VHDL design exercises including logic gates, 2-bit adders, decoders, and BCD to 7-segment decoders.

    Original Description:

    Digital design with vhdl

    Original Title

    Cac Thao Tac VHDL

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    © Attribution Non-Commercial (BY-NC)

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    The document discusses how to view an RTL schematic in Vivado and provides examples of VHDL code for basic logic gates and circuits including AND gates, OR gates, and a 4-1 multiplexer. It also lists some VHDL design exercises including logic gates, 2-bit adders, decoders, and BCD to 7-segment decoders.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    33 views5 pages

    To View An RTL Schematic: Sources Tab

    Uploaded by

    binhnhi0007
    The document discusses how to view an RTL schematic in Vivado and provides examples of VHDL code for basic logic gates and circuits including AND gates, OR gates, and a 4-1 multiplexer. It also lists some VHDL design exercises including logic gates, 2-bit adders, decoders, and BCD to 7-segment decoders.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 5

    Chuyn i code to RTL schematic:

    To View an RTL Schematic


    1. In the Sources tab, select Synthesis/Implementation from the Design View dropdown list. 2. Select the top module .

    3. In the Processes tab, expand Synthesize - XST. 4. Double-click View RTL Schematic. Chn Regenerate schematic xem mch c th. V d testbench v component:
    -----------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity OR_GATE is port( X: in std_logic; Y: in std_logic; F2: out std_logic ); end OR_GATE; architecture behv of OR_GATE is begin process(X,Y) begin F2 <= X or Y; end process; end behv; -- component #1

    -- behavior des.

    ------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity AND_GATE is port( A: in std_logic; B: in std_logic; F1: out std_logic ); end AND_GATE; architecture behv of AND_GATE is begin -- component #2

    process(A,B) begin F1 <= A and B; end process; end behv;

    -- behavior des.

    -------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use work.all; entity comb_ckt is port( input1: in std_logic; input2: in std_logic; input3: in std_logic; output: out std_logic ); end comb_ckt; architecture struct of comb_ckt is component AND_GATE is port( A: in std_logic; B: in std_logic; F1: out std_logic ); end component; component OR_GATE is port( X: in std_logic; Y: in std_logic; F2: out std_logic ); end component; signal wire: std_logic; begin -- use sign "=>" to clarify the pin mapping Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire); Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output); end struct; ----------------------------------------------------------------- as entity of AND_GATE -- top level circuit

    -- as entity of OR_GATE

    -- signal just like wire

    Testbench
    -------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity CKT_TB is -- empty entity

    end CKT_TB; ------------------------------------------------------------------architecture TB of CKT_TB is -- declare the whole circuit(entity of comb_ckt.vhd) as a component component comb_ckt is port( input1: in std_logic; input2: in std_logic; input3: in std_logic; output: out std_logic ); end component; -- declare all I/O ports from unit under test as signals. -- signals are usually declared within architecture signal T_input1, T_input2, T_input3, T_output: std_logic; begin U_UT: comb_ckt port map (T_input1,T_input2,T_input3,T_output); process variable err_cnt: integer := 0; begin -- Test case 1 T_input1 <= '0'; T_input2 <= '0'; T_input3 <= '0'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 2 T_input1 <= '1'; T_input2 <= '1'; T_input3 <= '1'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 3 T_input1 <= '1'; T_input2 <= '0'; T_input3 <= '1';

    wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 4 T_input1 <= '0'; T_input2 <= '1'; T_input3 <= '0'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- summary of all the tests to see if any errors if (err_cnt=0) then assert false report "Testbench completed successfully!" severity note; else assert true report "Something wrong, try again pls!" severity error; end if; wait; end process; end TB; ------------------------------------------------------------------configuration CFG_TB of CKT_TB is for TB end for; end CFG_TB; --------------------------------------------------------------------- stop running

    Bi tp VHDL: 1. Mch cng AND, OR, NOR, EXOR, EXNOR. 2. Mch cng 2 bit: c bit nh ng vo v khng c bit nh ng vo. 3. Mch a hp mux4:1 4. Mch gii a hp demux1:4 5. Mch gii m 2 ng sang 4 ng 6. Mch 4 cng tc iu khin 1 bng n. 7. Mch gii m bcd sang 7 on.

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