2.7V Dual Channel 12-Bit A/D Converter With SPI Serial Interface

1999-2011 Microchip Technology Inc.
DS21034F-page 1
MCP3202
Features
12-bit resolution
1 LSB maximum DNL
1 LSB maximum INL (MCP3202-B)
2 LSB maximum INL (MCP3202-C)
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI Serial Interface (Modes 0,0 and 1,1)
Single supply operation: 2.7V-5.5V
100 ksps maximum sampling rate at V
DD
= 5V
50 ksps maximum sampling rate at V
DD
= 2.7V
Low power CMOS technology
500 nA typical standby current, 5 A maximum
550 A maximum active current at 5V
Industrial temp range: -40C to +85C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Applications
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Functional Block Diagram
Description
The MCP3202 is a successive approximation 12-bit
analog-to-digital (A/D) converter with on-board sample
and hold circuitry.
The MCP3202 is programmable to provide a single
pseudo-differential input pair or dual single-ended
inputs. Differential Nonlinearity (DNL) is specified at
1 LSB, and Integral Nonlinearity (INL) is offered in
1 LSB (MCP3202-B) and 2 LSB (MCP3202-C)
versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of conversion rates of up to 100 ksps
at 5V and 50 ksps at 2.7V.
The MCP3202 operates over a broad voltage range,
2.7V to 5.5V. Low-current design permits operation with
typical standby and active currents of only 500 nA and
375 A, respectively.
The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP
and 150 mil SOIC packages.
Package Types
Comparator
Sample
and

Hold
12-Bit SAR
DAC
Control Logic
CS/SHDN
V
SS
V
DD
CLK D
OUT
Shift
Register
CH0
Channel
Mux
Input
CH1
D
IN
M
C
P
3
2
0
2
1
2
3
4
8
7
6
5
CH0
CH1
V
SS
CS/SHDN V
DD
/V
REF
CLK
D
OUT
D
IN
PDIP, MSOP, SOIC, TSSOP
2.7V Dual Channel 12-Bit A/D Converter
with SPI Serial Interface
MCP3202
DS21034F-page 2 1999-2011 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
V
DD
- V
SS
.........................................................................7.0V
All Inputs and Outputs w.r.t. V
SS
............. -0.6V to V
DD
+ 0.6V
Storage Temperature.....................................-65C to +150C
Ambient temperature with power applied.......-65C to +150C
Maximum Junction Temperature (T
J
) ......................... .+150C
ESD Protection On All Pins (HBM) 4 kV
Notice: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5.5V, V
SS
= 0V,
T
A
= -40C to +85C, f
SAMPLE
= 100 ksps and f
CLK
= 18*f
SAMPLE
.
Parameter Sym Min. Typ. Max. Units Conditions
Conversion Rate:
Conversion Time t
CONV
12 clock
cycles
Analog Input Sample Time t
SAMPLE
1.5 clock
cycles
Throughput Rate f
SAMPL
100
50
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
DC Accuracy:
Resolution 12 bits
Integral Nonlinearity INL
0.75
1
1
2
LSB
LSB
MCP3202-B
MCP3202-C
Differential Nonlinearity DNL 0.5 1 LSB No missing codes over
temperature
Offset Error 1.25 3 LSB
Gain Error 1.25 5 LSB
Dynamic Performance:
Total Harmonic Distortion THD -82 dB V
IN
= 0.1V to 4.9V@1 kHz
Signal-to-Noise and Distortion
(SINAD)
SINAD 72 dB V
IN
= 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range SFDR 86 dB V
IN
= 0.1V to 4.9V@1 kHz
Analog Inputs:
Input Voltage Range for CH0 or
CH1 in Single-Ended Mode
V
SS
V
DD
V
Input Voltage Range for IN+ in
Pseudo-Differential Mode
IN+ IN- V
DD
+IN- See Sections 3.1 and 4.1
Input Voltage Range for IN- in
Pseudo-Differential Mode
IN- V
SS
-100 V
SS
+100 mV See Sections 3.1 and 4.1
Leakage Current .001 1 A
Switch Resistance R
SS
1 k See Figure 4-1
Sample Capacitor C
SAMPLE
20 pF See Figure 4-1
Digital Input/Output:
Data Coding Format Straight Binary
High Level Input Voltage V
IH
0.7 V
DD
V
Low Level Input Voltage V
IL
0.3 V
DD
V
Note 1: This parameter is established by characterization and not 100% tested.
2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 Maintaining Minimum Clock Speed for more information.
1999-2011 Microchip Technology Inc. DS21034F-page 3
MCP3202
TEMPERATURE CHARACTERISTICS
High Level Output Voltage V
OH
4.1 V I
OH
= -1 mA, V
DD
= 4.5V
Low Level Output Voltage V
OL
0.4 V I
OL
= 1 mA, V
DD
= 4.5V
Input Leakage Current I
LI
-10 10 A V
IN
= V
SS
or V
DD
Output Leakage Current I
LO
-10 10 A V
OUT
= V
SS
or V
DD
Pin Capacitance
(All Inputs/Outputs)
C
IN
, C
OUT
10 pF V
DD
= 5.0V (Note 1)
T
A
= +25C, f = 1 MHz
Timing Parameters:
Clock Frequency f
CLK
1.8
0.9
MHz
MHz
V
DD
= 5V (Note 2)
V
DD
= 2.7V (Note 2)
Clock High Time t
HI
2 MHz
Clock Low Time t
LO
2 MHz
CS Fall To First Rising CLK
Edge
t
SUCS
100 ns
Data Input Setup Time t
SU
50 ns
Data Input Hold Time t
HD
50 ns
CLK Fall To Output Data Valid t
DO
200 ns See Test Circuits, Figure 1-2
CLK Fall To Output Enable t
EN
CS Rise To Output Disable t
DIS
Note 1
CS Disable Time t
CSH
500 ns
D
OUT
Rise Time t
R
Note 1
D
OUT
Fall Time t
F
Note 1
Power Requirements:
Operating Voltage V
DD
2.7 5.5 V
Operating Current I
DD
375 550 A V
DD
= 5.0V, D
OUT
unloaded
Standby Current I
DDS
0.5 5 A CS = V
DD
= 5.0V
Electrical Specifications: Unless otherwise indicated, V
DD
= +2.7V to +5.5V, V
SS
= GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T
A
-40 +85 C
Operating Temperature Range T
A
-40 +85 C
Storage Temperature Range T
A
-65 +150 C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP
JA
211 C/W
Thermal Resistance, 8L-PDIP
JA
89.5 C/W
Thermal Resistance, 8L-SOIC
JA
149.5 C/W
Thermal Resistance, 8L-TSSOP
JA
139 C/W
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5.5V, V
SS
= 0V,
T
A
= -40C to +85C, f
SAMPLE
= 100 ksps and f
CLK
= 18*f
SAMPLE
.
Parameter Sym Min. Typ. Max. Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 Maintaining Minimum Clock Speed for more information.
MCP3202
FIGURE 1-1: Serial Timing.
CS
CLK
D
IN MSB IN
t
SU
t
HD
t
SUCS
t
CSH
t
HI
t
LO
D
OUT
t
EN
t
DO
t
R t
F
LSB
MSB OUT
t
DIS
NULL BIT
MCP3202
FIGURE 1-2: Test Circuits.
V
IH
T
DIS
CS
D
OUT
Waveform 1*
D
OUT
Waveform 2
90%
10%
* Waveform 1 is for an output with internal conditions
such that the output is high, unless disabled by the
output control.
Waveform 2 is for an output with internal conditions
such that the output is low, unless disabled by the
output control.
Voltage Waveforms for t
DIS
Test Point
1.4V
D
OUT
Load Circuit for t
R
, t
F
, t
DO
3 k
C
L
= 100 pF
Test Point
D
OUT
Load Circuit for t
DIS
and t
EN
3 k
100 pF
t
DIS
Waveform 2
t
DIS
Waveform 1
CS
CLK
D
OUT
t
EN
1 2
B11
EN
t
EN
Waveform
V
DD
V
DD
/2
V
SS
3 4
D
OUT
t
R
R
, t
F
CLK
D
OUT
t
DO
DO
t
F
V
OH
V
OL
MCP3202
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, V
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
FIGURE 2-1: Integral Nonlinearity (INL)
vs. Sample Rate.
vs. V
DD
.
vs. Code (Representative Part).
vs. Sample Rate (V
DD
= 2.7V).
vs. V
DD
.
vs. Code (Representative Part, V
DD
= 2.7V).
Note: The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 25 50 75 100 125 150
I
N
L
(
L
S
B
)
Sample Rate (ksps)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
3.0 3.5 4.0 4.5 5.0
V
DD
(V)
I
N
L

(
L
S
B
)
Positive INL
Negative INL
fSAMPLE = 100 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
I
N
L

(
L
S
B
)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 20 40 60 80 100
Sample Rate (ksps)
I
N
L

(
L
S
B
)
V
DD
= 2.7V
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
2.5 3.0 3.5 4.0 4.5 5.0
V
DD
(V)
I
N
L

(
L
S
B
)
Positive INL
Negative INL
fSAMPLE = 50 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
I
N
L

(
L
S
B
)
VDD = 2.7V
F
SAMPLE
= 50 ksps
MCP3202
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
vs. Temperature.
FIGURE 2-8: Differential Nonlinearity
(DNL) vs. Sample Rate.
(DNL) vs. V
DD
.
vs. Temperature (V
DD
= 2.7V).
(DNL) vs. Sample Rate (V
DD
= 2.7V).
(DNL) vs. V
DD
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100
Temperature (C)
I
N
L

(
L
S
B
)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 25 50 75 100 125 150
Sample Rate (ksps)
D
N
L

(
L
S
B
)
Positive DNL
Negative DNL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
3.0 3.5 4.0 4.5 5.0
V
DD
(V)
D
N
L

(
L
S
B
)
Positive DNL
Negative DNL
fSAMPLE = 100 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100
Temperature (C)
I
N
L

(
L
S
B
)
Positive INL
VDD = 2.7V
fSAMPLE = 50 ksps
Negative INL
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 20 40 60 80 100
Sample Rate (ksps)
D
N
L

(
L
S
B
)
V
DD
= 2.7V
Positive DNL
Negative DNL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
2.5 3.0 3.5 4.0 4.5 5.0
V
DD
(V)
D
N
L

(
L
S
B
)
Positive DNL
Negative DNL
fSAMPLE = 50 ksps
MCP3202
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
(DNL) vs. Code (Representative Part).
(DNL) vs. Temperature.
FIGURE 2-15: Gain Error vs. V
DD
.
(DNL) vs. Code (Representative Part, V
DD
=
2.7V).
(DNL) vs. Temperature (V
DD
= 2.7V).
FIGURE 2-18: Offset Error vs. V
DD
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
D
N
L

(
L
S
B
)
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100
Temperature (C)
D
N
L

(
L
S
B
)
Positive DNL
Negative DNL
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5 3.0 3.5 4.0 4.5 5.0
V
DD
(V)
G
a
i
n

E
r
r
o
r

(
L
S
B
)
fSAMPLE = 50 ksps
f
SAMPLE
= 100 ksps
f
SAMPLE
= 10 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
D
N
L

(
L
S
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100
Temperature (C)
D
N
L

(
L
S
B
)
Positive DNL
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
Negative DNL
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.5 3.0 3.5 4.0 4.5 5.0
V
DD
(V)
O
f
f
s
e
t

E
r
r
o
r

(
L
S
B
)
f
SAMPLE
= 10 ksps
f
SAMPLE
= 50 ksps
f
SAMPLE
= 100 ksps
MCP3202
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-20: Signal-to-Noise Ratio
(SNR) vs. Input Frequency.
FIGURE 2-21: Total Harmonic Distortion
(THD) vs. Input Frequency.
FIGURE 2-22: Offset Error vs.
Temperature.
FIGURE 2-23: Signal-to-Noise and
Distortion (SINAD) vs. Input Frequency.
FIGURE 2-24: Signal-to-Noise and
Distortion (SINAD) vs. Signal Level.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100
Temperature (C)
G
a
i
n

E
r
r
o
r

(
L
S
B
)
VDD = 5V
fSAMPLE = 100
VDD = 2.7V
fSAMPLE = 50 ksps
0
10
20
30
40
50
60
70
80
90
100
1 10 100
Input Frequency (kHz)
S
N
R

(
d
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
V
DD
= 5V
f
SAMPLE
= 100 ksps
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100
T
H
D

(
d
B
)
VDD= 2.7V
fSAMPLE = 50 ksps
VDD = 5V
fSAMPLE = 100 ksps
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 -25 0 25 50 75 100
Temperature (C)
O
f
f
s
e
t

E
r
r
o
r

(
L
S
B
) VDD = 5V
fSAMPLE = 100 ksps
VDD = 2.7V
fSAMPLE = 50 ksps
0
10
20
30
40
50
60
70
80
90
100
1 10 100
S
I
N
A
D

(
d
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
V
DD
= 5V
f
SAMPLE
= 100 ksps
0
10
20
30
40
50
60
70
80
-40 -35 -30 -25 -20 -15 -10 -5 0
Input Signal Level (dB)
S
I
N
A
D

(
d
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
V
DD
= 5V
f
SAMPLE
= 100 ksps
MCP3202
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
FIGURE 2-25: Effective Number of Bits
(ENOB) vs. V
DD
.
FIGURE 2-26: Spurious Free Dynamic
Range (SFDR) vs. Input Frequency.
FIGURE 2-27: Frequency Spectrum of
10 kHz input (Representative Part).
FIGURE 2-28: Effective Number of Bits
(ENOB) vs. Input Frequency.
FIGURE 2-29: Power Supply Rejection
(PSR) vs. Ripple Frequency.
FIGURE 2-30: Frequency Spectrum of
1 kHz input (Representative Part, V
DD
= 2.7V).
9.0
9.5
10.0
10.5
11.0
11.5
12.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
DD
(V)
E
N
O
B

(
r
m
s
)
f
SAMPLE
= 50ksps
f
SAMPLE
= 100 ksps
0
10
20
30
40
50
60
70
80
90
100
1 10 100
S
F
D
R

(
d
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
V
DD
= 5V
f
SAMPLE
= 100 ksps
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 10000 20000 30000 40000 50000
Frequency (Hz)
A
m
p
l
i
t
u
d
e

(
d
B
)
V
DD
= 5V
f
SAMPLE
= 100 ksps
f
INPUT
= 9.985 kHz
4096 points
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
1 10 100
E
N
O
B

(
r
m
s
)
V
DD
= 5V
F
SAMPLE
= 100 ksps
V
DD
= 2.7V
F
SAMPLE
= 50 ksps
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1000 10000
Ripple Frequency (kHz)
P
o
w
e
r

S
u
p
p
l
y

R
e
j
e
c
t
i
o
n

(
d
B
)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5000 10000 15000 20000 25000
Frequency (Hz)
A
m
p
l
i
t
u
d
e

(
d
B
)
V
DD
= 2.7V
f
SAMPLE
= 50 ksps
f
INPUT
= 998.76 Hz
4096 points
MCP3202
DD
= 5V, V
SS
= 0V, f
SAMPLE =
100 ksps,

f
CLK
= 18* f
SAMPLE
, T
A
= +25C.
FIGURE 2-31: I
DD
vs. V
DD
.
FIGURE 2-32: I
DD
vs. Clock Frequency.
FIGURE 2-33: I
DD
vs. Temperature.
FIGURE 2-34: I
DDS
vs. V
DD
.
FIGURE 2-35: I
DDS
vs. Temperature.
FIGURE 2-36: Analog Input leakage
current vs. Temperature.
0
50
100
150
200
250
300
350
400
450
500
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
I
D
D

(
A
)
All points at F
CLK
= 1.8 MHz except
at V
DD
= 2.5V, F
CLK
= 900 kHz
0
50
100
150
200
250
300
350
400
450
500
10 100 1000 10000
Clock Frequency (kHz)
I
D
D

(
A
)
V
DD
= 5V
V
DD
= 2.7V
0
50
100
150
200
250
300
350
400
450
500
-50 -25 0 25 50 75 100
Temperature (C)
I
D
D

(
A
)
VDD = 5V
F
CLK
= 1.8 MHz
V
DD
= 2.7V
F
CLK
= 900 kHz
0
10
20
30
40
50
60
70
80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
I
D
D
S

(
p
A
)
CS = V
DD
0.01
0.10
1.00
10.00
100.00
- 50 -25 0 25 50 75 100
Temperature (C)
I
D
D
S

(
n
A
)
VDD =CS =5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 -25 0 25 50 75 100
Temperature (C)
A
n
a
l
o
g

I
n
p
u
t

L
e
a
k
a
g
e

(
n
A
)
V
DD
= 5V
F
CLK
= 1.8 MHz
MCP3202
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3.1.
Additional descriptions of the device pins follows.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Inputs (CH0/CH1)
Analog inputs for channels 0 and 1 respectively. These
channels can be programmed to be used as two
independent channels in Single-Ended mode or as a
single pseudo-differential input where one channel is
IN+ and one channel is IN-. See Section 5.0 Serial
Communications for information on programming
the channel configuration.
3.2 Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a
conversion and put the device in low power standby
when pulled high. The CS/SHDN pin must be pulled
high between conversions.
3.3 Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 Maintaining Minimum Clock
Speed for constraints on clock speed.
3.4 Serial Data Input (D
IN
)
The SPI port serial data input pin is used to clock in
input channel configuration data.
3.5 Serial Data Output (D
OUT
)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
MSOP, PDIP, SOIC,
TSSOP
Name Function
1 CS/SHDN Chip Select/Shutdown Input
2 CH0 Channel 0 Analog Input
3 CH1 Channel 1 Analog Input
4 V
SS
Ground
5 D
IN
Serial Data In
6 D
OUT
Serial Data Out
7 CLK Serial Clock
8 V
DD
/V
REF
+2.7V to 5.5V Power Supply and Reference Voltage Input
MCP3202
4.0 DEVICE OPERATION
The MCP3202 A/D converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of
the serial clock after the start bit has been received.
Following this sample time, the input switch of the con-
verter opens and the device uses the collected charge
on the internal sample and hold capacitor to produce a
serial 12-bit digital output code.
Conversion rates of 100 ksps are possible on the
MCP3202. See Section 6.2 Maintaining Minimum
Clock Speed for information on minimum clock rates.
Communication with the device is done using a 3-wire
SPI-compatible interface.
4.1 Analog Inputs
The MCP3202 device offers the choice of using the
analog input channels configured as two single-ended
inputs or a single pseudo-differential input. Configura-
tion is done as part of the serial command before each
conversion begins. When used in the pseudo-differen-
tial mode, CH0 and CH1 are programmed as the IN+
and IN- inputs as part of the command string transmit-
ted to the device. The IN+ input can range from IN- to
V
REF
(V
DD
+ IN-). The IN- input is limited to 100 mV
from the V
SS
rail. The IN- input can be used to cancel
small signal common-mode noise which is present on
both the IN+ and IN- inputs.
For the A/D converter to meet specification, the charge
holding capacitor (C
SAMPLE
) must be given enough
time to acquire a 12-bit accurate voltage level during
the 1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(R
S
) adds to the internal sampling switch (R
SS
) imped-
ance, directly affecting the time that is required to
charge the capacitor, C
SAMPLE
. Consequently, larger
source impedances increase the offset, gain, and
integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational
amplifier such as the MCP601 which has a closed loop
output impedance of tens of ohms. The adverse affects
of higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[V
DD
+(IN-)] -1 LSB}, then the output
code will be FFFh. If the voltage level at IN- is more
than 1 LSB below V
SS
, then the voltage level at the IN+
input will have to go below V
SS
to see the 000h output
code. Conversely, if IN- is more than 1 LSB above V
SS
,
then the FFFh code will not be seen unless the IN+
input level goes above V
DD
level.
4.2 Digital Output Code
The digital output code produced by an A/D converter
is a function of the input signal and the reference volt-
age. For the MCP3202, V
DD
is used as the reference
voltage. As the V
DD
level is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D converter is shown below.
EQUATION 4-1:
Digital Output Code
4096V
IN
V
DD
----------------------- =
where:
V
IN
= analog input voltage
V
DD
= supply voltage
MCP3202
FIGURE 4-1: Analog Input Model.
FIGURE 4-2: Maximum Clock Frequency
vs. Input Resistance (R
S
) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.
C
PIN
VA
R
SS
CHx
7 pF
V
T
= 0.6V
V
T
= 0.6V
I
LEAKAGE
Sampling
Switch
SS R
S
= 1 kW
C
SAMPLE
= DAC capacitance
V
SS
V
DD
= 20 pF
1 nA
Legend
VA = signal source
R
SS
= source impedance
CHx = input channel pad
C
PIN
= input pin capacitance
V
T
= threshold voltage
I
LEAKAGE
= leakage current at the pin due to various junctions
SS = sampling switch
R
S
= sampling switch resistor
C
SAMPLE
= sample/hold capacitance
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
100 1000 10000
Input Resistance (Ohms)
C
l
o
c
k

F
r
e
q
u
e
n
c
y

(
M
H
z
) V
DD
= 5V
V
DD
= 2.7V
MCP3202
5.0 SERIAL COMMUNICATIONS
5.1 Overview
Communication with the MCP3202 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See Figure 5-1. If the device was powered
up with the CS pin low, it must be brought high and
back low to initiate communication. The first clock
received with CS low and D
IN
high will constitute a start
bit. The SGL/DIFF bit and the ODD/SIGN bit follow the
start bit and are used to select the input channel config-
uration. The SGL/DIFF is used to select Single-Ended
or Pseudo-Differential mode. The ODD/SIGN bit
selects which channel is used in Single-Ended mode,
and is used to determine polarity in Pseudo-Differential
mode. Following the ODD/SIGN bit, the MSBF bit is
transmitted to and is used to enable the LSB first format
for the device. If the MSBF bit is high, then the data will
come from the device in MSB first format and any fur-
ther clocks with CS low will cause the device to output
zeros. If the MSBF bit is low, then the device will output
the converted word LSB first after the word has been
transmitted in the MSB first format. See Figure 5-2.
Table 5-1 shows the configuration bits for the
MCP3202. The device will begin to sample the analog
input on the second rising edge of the clock, after the
start bit has been received. The sample period will end
on the falling edge of the third clock following the start
bit.
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential
12 clocks will output the result of the conversion with
MSB first as shown in Figure 5-1. Data is always output
from the device on the falling edge of the clock. If all
12 data bits have been transmitted and the device con-
tinues to receive clocks while the CS is held low, (and
MSBF = 1), the device will output the conversion result
LSB first as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the D
IN
line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 Using the MCP3202 with Microcon-
troller (MCU) SPI Ports for more details on using the
MCP3202 devices with hardware SPI ports.
FIGURE 5-1: Communication with the MCP3202 using MSB first format only.
TABLE 5-1: CONFIGURATION BITS FOR
THE MCP3202
Config
Bits
Channel
Selection
GND
SGL/
DIFF
ODD/
SIGN
0 1
Single-Ended
Mode
1 0 + -
1 1 + -
Pseudo-
Differential
Mode
0 0 IN+ IN-
0 1 IN- IN+
CS
CLK
D
IN
D
OUT
MS
HI-Z
Null
Bit
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
t
SAMPLE
t
CONV
SGL/
DIFF
Start
t
CYC
t
CSH
t
CYC
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely. See Figure 5-2 below for details on obtaining LSB first data.
** t
DATA
: during this time, the bias current and the comparator power down while the reference input becomes a
high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
t
DATA
**
t
SUCS
ODD/
SIGN
BF
Dont Care
SGL/
DIFF
Start ODD/
SIGN
MCP3202
FIGURE 5-2: Communication with MCP3202 using LSB first format.
Null
Bit
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
CS
CLK
D
OUT
HI-Z
HI-Z
(MSB)
t
CONV
t
DATA
**
Power Down
t
SAMPLE
D
IN
t
CYC
t
CSH
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely.
** t
DATA
: During this time, the bias circuit and the comparator power down while the reference input becomes a
high-impedance node, leaving the CLK running to clock out LSB first data or zeroes.
t
SUCS
O
D
D
/
S
I
G
N
S
t
a
r
t
S
G
L
/
D
I
F
F
M
S
B
F
Dont Care
*
MCP3202
6.0 APPLICATIONS INFORMATION
6.1 Using the MCP3202 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on
the rising edge. Depending on how communication
routines are used, it is very possible that the number of
clocks required for communication will not be a multiple
of eight. Therefore, it may be necessary for the MCU to
send more clocks than are actually required. This is
usually done by sending leading zeros before the start
bit, which are ignored by the device.
As an example, Figure 6-1 and Figure 6-2 show how
the MCP3202 can be interfaced to a MCU with a
hardware SPI port.
Figure 6-1 depicts the operation shown in SPI Mode
0,0, which requires that the SCLK from the MCU idles
in the low state, while Figure 6-2 shows the similar
case of SPI Mode 1,1 where the clock idles in the high
state.
As shown in Figure 6-1, the first byte transmitted to the
A/D converter contains seven leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D con-
verter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCU receive buffer will contain three unknown bits (the
output is at high-impedance until the null bit is clocked
out), the null bit and the highest order four bits of the
conversion. After the third byte has been sent to the
device, the receive register will contain the lowest order
eight bits of the conversion results. Easier manipulation
of the converted data can be obtained by using this
method.
FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SCLK
D
IN
X = Dont Care Bits
17 18 19 20 21 22 23 24
D
OUT
NULL
BIT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
HI-Z
MCU latches data from A/D converter
Data is clocked out of
A/D converter on falling edges
on rising edges of SCLK
M
S
B
F
Dont Care
O
D
D
/
S
I
G
N
Start
X X X X X X X X X X X X X X X X X X
B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
0
X X X X X X X X X X X
1
Start
Bit
(Null)
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
MSBF
SGL/
DIFF
X X
SGL/
DIFF
ODD/
SIGN
Data stored into MCU receive
register after transmission of
first 8 bits
second 8 bits
last 8 bits
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SCLK
D
IN
X = Dont Care Bits
17 18 19 20 21 22 23 24
D
OUT
Dont Care
NULL
BIT
B11 B10 B9 B8 B6 B5 B4 B3 B2 B1 B0
HI-Z
0 0 0 0 0 0 X X X X X X X X X X X X X
B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
0
X X X X X X X X X X X
MCU latches data from A/D converter
on rising edges of SCLK
Data is clocked out of
A/D converter on falling edges
Start
Bit
(Null)
Start
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
B7
1
S
G
L
/
D
I
F
F
M
S
B
F
O
D
D
/
S
I
G
N
0
SGL/
DIFF
ODD/
SIGN
MSBF
first 8 bits
second 8 bits
last 8 bits
MCP3202
6.2 Maintaining Minimum Clock Speed
When the MCP3202 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85C (worst case condition), the part will maintain
proper charge on the sample capacitor for at least
1.2 ms after the sample period has ended. This means
that the time between the end of the sample period and
the time that all 12 data bits have been clocked out
must not exceed 1.2 ms (effective clock frequency of
10 kHz). Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D converter does not require a
constant clock speed or duty cycle, as long as all timing
specifications are met.
6.3 Buffering/Filtering the Analog
Inputs
If the signal source for the A/D converter is not a low-
impedance source, it will have to be buffered or
inaccurate conversion results may occur. It is also
recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results. This is illustrated in Figure 6-3 below where an
op amp is used to drive the analog input of the
MCP3202. This amplifier provides a low-impedance
output for the converter input and a low-pass filter,
which eliminates unwanted high frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchips interactive FilterLab
software. FilterLab
will calculate capacitor and resistor values, as well as,
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 Anti-Aliasing Analog
Filters for Data Acquisition Systems.
FIGURE 6-3: The MCP601 Operational

Amplifier is used to implement a 2nd order anti-
aliasing filter for the signal being converted by
the MCP3202.
6.4 Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass
capacitor value of 0.1 F is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
DD
connections to
devices in a star configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D converters, refer to AN688 Layout
Tips for 12-Bit A/D Converter Applications (DS00688).
FIGURE 6-4: V
DD
traces arranged in a
Star configuration in order to reduce errors
caused by current return paths.
MCP3202
V
DD
10 F
IN-
IN+
-
+ V
IN
C1
C
2
0.1 F
MCP601
R
1
R
2
R
3
R
4
V
DD
Connection
Device 1
Device 2
Device 3
Device 4
MCP3202
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
XXXXXXXX
XXXXXNNN
YYWW
NNN
8-Lead SOIC (3.90 mm) Example
3202-BI
SN 1130
3
8-Lead PDIP (300 mil) Example
8-Lead MSOP (3x3 mm) Example
3202-B
I/P 256
1130
3
3202CI
130256
MCP3202
Package Marking Information (Continued)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
8-Lead TSSOP (4.4 mm) Example
202C
1130
256
MCP3202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP3202
MCP3202
MCP3202
8-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Units NCHES
Dimension Limits MN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
N
E1
NOTE 1
D
1 2 3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018B
MCP3202
Note: Forthemostcurrentpackagedrawings,pleaseseetheMicrochipPackagingSpecificationlocatedat
MCP3202
Note: Forthemostcurrentpackagedrawings,pleaseseetheMicrochipPackagingSpecificationlocatedat
MCP3202
8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
MCP3202
8-Lead PIastic Thin Shrink SmaII OutIine (ST) - 4.4 mm Body [TSSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Units MLLMETERS
Dimension Limits MN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0 8
Lead Thickness c 0.09 0.20
Lead Width b 0.19 0.30
D
N
E
E1
NOTE 1
1 2
b
e
c
A
A1
A2
L1 L
Microchip Technology Drawing C04-086B

MCP3202
MCP3202
APPENDIX A: REVISION HISTORY
Revision F (November 2011)
Updated Product Identification System
Corrected MSOP package marking drawings.
Updated Package Specification Drawings with new
additions.
Revision E (December 2008)
Updates to packaging outline drawings.
Revision D (December 2006)
Updates to packaging outline drawings.
Revision C (August 2001)
Undocumented changes.
Revision B (June 2000)
Undocumented changes.
Revision A (August 1999)
Initial release of this document.
MCP3202
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Package Temperature
Range
Device

Device MCP3202: 12-Bit Serial A/d Converter
MCP3202T: 12-Bit Serial A/D Converter (Tape and Reel)
(MSOP, SOIC and TSSOP package only)
Performance Grade: B = 1 LSB INL (TSSOP not available)
C = 2 LSB INL
Temperature Range I = -40C to +85C (Industrial)
E = -40C to +125C (Extended)
Package MS = Plastic Micro Small Outline (MSOP), 8-Lead
P = Plastic DIP (300 mil Body), 8-Lead
SN = Plastic SOIC (150 mil Body), 8-Lead
ST = TSSOP (4.4 mm Body), 8-Lead (C Grade only)
Examples:
a) MCP3202-CI/MS: Industrial temperature,
8LD MSOP package.
b) MCP3202-BI/P: B Performance grade,
Industrial temperature,
8LD PDIP package
c) MCP3202-BI/SN: C Performance grade,
8LD SOIC package
d) MCP3202T-BI/SN: Tape and Reel,
B Performance grade,
Industrial temperature.,
8LD SOIC package
e) MCP3202T-CI/ST: Tape and Reel,
C Performance grade,
8LD TSSOP package.
Performance
Grade
X
MCP3202
NOTES:
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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suits, or expenses resulting from such use. No licenses are
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC
32
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
1999-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-757-7
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC

MCUs and dsPIC
DSCs, KEELOQ

code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
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08/02/11

2.7V Dual Channel 12-Bit A/D Converter With SPI Serial Interface

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1999-2011 Microchip Technology Inc.

FIGURE 6-3: The MCP601 Operational

Microchip Technology Drawing C04-086B

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