SPITM Slave Library Module (Interrupt-driven)

1. 2. 3. 4. 5.

Introduction ...................................................................................................................... 2 Module Features............................................................................................................... 2 List of Component Modules............................................................................................ 3 Using the Library Module in a Project............................................................................ 3 List of Shared Parameters............................................................................................... 4 Shared Data Bytes ............................................................................................................. 4 Shared Functions ............................................................................................................... 4 Shared Macros ................................................................................................................... 4

6. 7. 8.

Functions .......................................................................................................................... 5 Macros............................................................................................................................... 6 Error and Status Flags..................................................................................................... 9

SPI Slave Library Module (Interrupt-driven)

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1. Introduction
The SPISInt is a general-purpose library module. It configures the MSSP/SSP/BSSP module in the Slave mode and helps in communicating with the SPITM Master. The module code is linkable and relocatable, which provides the user the facility to use it without modifications. It provides the interrupt-based operation and has its own Tx & Rx buffer, which provides maximum benefit of parallel processing. By using this Module one can write his application to interact with any of the SPI Master. The module allows the user to concentrate more on his applications development by providing these library functions.

2. Module Features
It supports following features:-

It provides simple and primitive functions to communicate with the SPI Master. User defined length of the Tx & Rx Buffer. Interrupt driven transmission and reception. It generates Error flags on the occurrence of an error. All error conditions are passed through the SPISIntStatus Register.

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3. List of Component Modules

SPISInt.P16.ex.txt SPISInt.P18.ex.txt SPISInt.asm 16SPISI.asm

18SPISI.asm

SPISInt.inc

P16xxx.inc P18xxx.inc

This is an example file developed to demonstrate the use of the library functions for the PIC16 family. This is an example file developed to demonstrate the use of the library functions for the PIC18 family. This is the SPI Slave code implementation file. One needs to include this file in their project. This is the SPI Slave code implementation file for the PIC16 family. The SPISInt.asm file will include this file if the PIC16 family processor is used. This is the SPI Slave code implementation file for the PIC18 family. The SPISInt.asm file will include this file if the PIC18 family processor is used. This file contains the definitions of all the shared parameters and the macros. One needs to include this in the Assembly file where the library functions and macros are called. This file takes care of the definitions of all Extern Global parameters, so one can directly call the library routines in their program. General purpose processor definition file for the PIC16 family General purpose processor definition file for the PIC18 family

4. Using the Library Module in a Project

Please follow the steps below to use this library module in your project. 1. 2. 3. 4. 5. 6. 7. 8. Use the Application Maestro to configure the module as required. At the Generate Files step, save the output to the directory where your project code resides. Launch the MPLAB, and open the projects workspace. Verify that the Microchip language tool suite is selected (Project>Select Language Toolsuite). In the Workspace view, right-click on the Source Files node. Select the Add Files option. Select the file SPISInt.asm and click OK. Now right-click on the Linker Scripts node and select Add Files. Add the appropriate linker file (.lkr) for the projects target microcontroller. Add any other files that the project may require. Save and close the project. In your main source (assembler) file, add the include directive at the head of the code listing to include the file SPISInt.inc. By doing so, all files required to make the generated code work in your project will be included by reference when you build the project. To use the module in your application, invoke the functions or macros as needed.

9.

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5. List of Shared Parameters

Shared Data Bytes
vSPISIntStatus It is the Error/Status register. The details of each bit of this register is explained in Section 8"

Shared Functions
SPISIntInit It is used for the Synchronous Serial Port Initialization It initializes the Port according to the options opted through the Application Maestro. It is called from the interrupt handler. It is used for discarding the buffer.

SPISIntISR SPISIntDiscardRxBuf

Shared Macros
This sets the Idle state of the Clock line, Hi (High) or Lo (Low). mSPISIntSetTransmitOnClockEdge This sets the Clock edge at which the data is to be Transmitted, IdleToActive or ActiveToIdle. mSPISIntPut It is used for transmitting a byte on the SPI Bus. (This macro is included only if, in Application Maestro option Transmit Buffer Size, opted is non-zero). mSPISIntGet It is used for reading the received byte. (This macro is included only if, in the Application Maestro option Receive Buffer Size, opted is nonzero). mSPISIntSaveReceivedByte Sets a flag Save to indicate that the received byte should be saved. (This macro is included only if, in the Application Maestro option Receive Buffer Size, opted is a non-zero). mSPISIntDiscardReceivedByte Clears the flag Save to indicate that the received byte should not be saved. (This macro is included only if, in the Application Maestro option Receive Buffer Size, opted is a non-zero). mSPISIntDisable Disables the Synchronous Serial Port. mSetSPISIntHighPriority This sets the interrupt priority of SSP as High. mSetSPISIntLowPriority This sets the interrupt priority of SSP as Low. mSPISIntSetClockIdleState

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6. Functions
Function Preconditions SPISIntInit The TRIS bits of the SDO pin should be made output. The TRIS bit of the pins SCK and SDI should be made input. The TRIS bit of the Slave Select pin (if used) should be made input. This function is used for initializing the MSSP/SSP/BSSP module. It initializes the module according to the Application Maestro options. Application Maestro options None Bank selection bits and W register are changed 1 level deep 15 Cycles by the PIC16 family 12 Cycles by the PIC18 family

Overview Input Output Side Effects Stack Requirement Maximum T-Cycles taken

Function Preconditions Overview Input Output

Side Effects Maximum T-Cycles taken

SPISIntISR This function should be called from the interrupt handler. This is the interrupt service routine for SSPIF. This handles the transmission and reception of bytes. None While transmission is going on, if the buffer is full then, the bit vSPISIntStatus<SPISTxBufFull> is set. While reception is going on, if buffer is empty then, the bit vSPISIntStatus<SPISRxBufEmpty> is set. Bank selection bits and W register are changed Tx & Rx Buffer lengths PIC16 family PIC18 family Tx Buf >1, Rx Buf >1 100 Cycles 92 Cycles Tx Buf =1, Rx Buf >1 65 Cycles 60 Cycles Tx Buf >1, Rx Buf =1 60 Cycles 54 Cycles Tx Buf =0, Rx Buf >1 62 Cycles 58 Cycles Tx Buf >1, Rx Buf =0 56 Cycles 49 Cycles Tx Buf =1, Rx Buf =1 25 Cycles 22 Cycles Tx Buf =0, Rx Buf =1 22 Cycles 20 Cycles Tx Buf =1, Rx Buf =0 21 Cycles 17 Cycles

Function Preconditions Overview Input Output Side Effects Stack Requirement Maximum T-Cycles taken

SPISIntDiscardBuf The bit vSPISIntStatus<SPISRxBufEmpty> should be 0. This function flushes the buffer. None None Bank selection bits and W register are changed 1 level deep 10 Cycles by the PIC16 family 9 Cycles by the PIC18 family

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7. Macros
Macro Overview Input mSPISIntSetClockIdleState This Macro is used to specify the Idle State of the Clock pin (SCK). The Clock pin Idle state: Hi (for High) Lo (for Low) Example- To set the Clock pin Idle State as High, mSPISIntSetClockIdleState Hi None Bank selection bits are changed. None 3 Cycles by the PIC16 family 1 Cycle by the PIC18 family

Output Side Effects Stack Requirement Maximum T-Cycles taken

Macro Overview Input

Output Side Effects Stack Requirement Maximum T-Cycles taken

mSPISIntSetTransmitOnClockEdge This Macro is used to specify on what edge of the Clock the transmission should take place. Transmission at the clock edge: IdleToActive ActiveToIdle Example- To transmit on the Clock edge Idle to Active mSPISIntSetTransmitOnClockEdge IdleToActive None Bank selection bits are changed. None 3 Cycles by the PIC16 family 1 Cycle by the PIC18 family

Macro Overview

Input Output

Side Effects Stack Requirement Maximum T-Cycles taken

mSPISIntPut Preconditions: In the Application Maestro option the Transmit Buffer Size opted should be a non-zero and the function SPISIntInit should have been called. This function sends the byte in the W Reg. over the SPI bus if the bus is free, else saves the byte in the buffer. 'W' Register. If W is written into the buffer then, the bit vSPISIntStatus<SPISTxBufEmpty> is cleared. If the buffer gets full then, the bit vSPISIntStatus<SPISTxBufFull> is set. Bank selection bits and W register are changed 1 level deep Tx & Rx Buffer lengths PIC16 family PIC18 family Tx Buf > 1 42 Cycles 38 Cycles Tx Buf = 1 3 Cycles 3 Cycles

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Macro Overview

Input Output

Side Effects Stack Requirement Maximum T-Cycles taken

mSPISIntGet Preconditions: In the Application Maestro option Receive Buffer Size, opted should be a non-zero and the bit vSPISIntStatus<SPISRxBufEmpty> should return a 0. This function reads the byte received. None W Register will have the read byte. The bit vSPISIntStatus<SPISRxBufFull> is cleared. If the buffer gets empty then, the bit vSPISIntStatus<SPISRxBufEmpty> is set. Bank selection bits and W register are changed 1 level deep Tx & Rx Buffer lengths PIC16 family PIC18 family Rx Buf > 1 45 Cycles 35 Cycles Rx Buf = 1 3 Cycles 3 Cycles

Macro Overview

Input Output Side Effects Stack Requirement Maximum T-Cycles taken

mSPISIntSaveReceivedByte Sets a flag Save to indicate that the received byte should be saved. (This macro is included only if in the Application Maestro option, the Receive Buffer Size opted is a non-zero). None SPISIntStatus Bank selection bits are changed. None 1 Cycle

Macro Overview

Input Output Side Effects Stack Requirement Maximum T-Cycles taken

mSPISIntDoNotSaveReceivedByte Clears the flag Save to indicate that the received byte should not be saved. (This macro is included only if in the Application Maestro option, the Receive Buffer Size opted is a non-zero). None SPISIntStatus Bank selection bits are changed. None 1 Cycle

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Macro Overview Input Output Side Effects Stack Requirement Maximum T-Cycles taken

MSPISIntDisable Disables the MSSP/SSP/BSSP module. None None Bank selection bits are changed. None 3 Cycles by the PIC16 family 1 Cycle by the PIC18 family

Macro Overview Input Output Side Effects Stack Requirement Maximum T-Cycles taken

mSetSPISIntHighPriority (Valid only family devices). This sets the interrupt priority of SSP as High. None None Bank selection bits are changed. None 1 Cycle by the PIC18 family

for

the

PIC18

Macro Overview Input Output Side Effects Stack Requirement Maximum T-Cycles taken

mSetSPISIntLowPriority (Valid only for the PIC18 family devices). This sets the interrupt priority of SSP as Low. None None Bank selection bits are changed. None 1 Cycle by the PIC18 family

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8. Error and Status Flags

All errors/statuses are set as a content of the W Register. The individual errors/statuses are unique. Please refer the list below for the information.

SPISSave SPISTxBufFull SPISTxBufEmpty SPISRxBufFull SPISRxBufEmpty SPISRxBufOverFlow

This indicates that the received byte should be saved in the buffer. This indicates that the transmit buffer is full. This indicates that the transmit buffer is empty. This indicates that the receive buffer is full. This indicates that the receive buffer is empty. This indicates that the receive buffer is over flowing.

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