DRV 8834

DRV8834
www.ti.com SLVSB19A FEBRUARY 2012 REVISED MARCH 2012
DUAL BRIDGE STEPPER OR DC MOTOR DRIVER

Check for Samples: DRV8834
1
FEATURES
Dual-H-Bridge Current-Control Motor Driver Capable of Driving Two DC Motors or One Stepper Motor Two Control Modes: Built-In Indexer Logic With Simple STEP/DIRECTION Control and Up to 1/32-Step Microstepping PHASE/ENABLE Control, With the Ability to Drive External References for > 1/32-Step Microstepping Output Current 1.5-A Continuous, 2.2-A Peak per H-Bridge (at VM = 5 V, 25C) Low RDS(ON): 305-m HS + LS (at VM = 5 V, 25C) Wide Power Supply Voltage Range: 2.5 V 10.8 V Dynamic tBLANK and Mixed Decay Modes for Smooth Microstepping PWM Winding Current Regulation and Limiting Thermally Enhanced Surface Mount Package
APPLICATIONS
Battery-Powered Toys POS Printers Video Security Cameras Office Automation Machines Gaming Machines Robotics
DESCRIPTION
The DRV8834 provides a flexible motor driver solution for toys, printers, cameras, and other mechatronic applications. The device has two H-bridge drivers, and is intended to drive a bipolar stepper motor or two DC motors. The output driver block of each H-bridge consists of N-channel power MOSFETs configured as an H-bridge to drive the motor windings. Each H-bridge includes circuitry to regulate or limit the winding current. With proper PCB design, each H-bridge of the DRV8834 is capable of driving up to 1.5-A RMS (or DC) continuously, at 25C with a VM supply of 5 V. It can support peak currents of up to 2.2 A per bridge. Current capability is reduced slightly at lower VM voltages. Internal shutdown functions with a fault output pin are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. A low-power sleep mode is also provided. The DRV8834 is packaged in a 24-pin HTSSOP or VQFN package with PowerPAD (Eco-friendly: RoHS & no Sb/Br). ORDERING INFORMATION (1)
PACKAGE (2) PowerPAD (HTSSOP) - PWP PowerPAD (VQFN) - RGE (1) (2) Reel of 2000 Tube of 60 Reel of 3000 Reel of 250 ORDERABLE PART NUMBER DRV8834PWPR DRV8834PWP DRV8834RGER DRV8834RGET TOP-SIDE MARKING DRV8834 8834
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
Copyright 2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
DRV8834
SLVSB19A FEBRUARY 2012 REVISED MARCH 2012 www.ti.com
DEVICE INFORMATION
Functional Block Diagram
VM VM + 0.01F 10F VINT 2.2F VREFO VREFO nENBL / AENBL STEP / BENBL DIR / BPHASE CONFIG M0 / APHASE M1 nSLEEP nFAULT Logic ISEN
VM VM
VM
VCP VINT, refs, Int. supp.
VM Internal Ref & Regs Charge Pump VCP 0.01F

PUC, UVLO VM
AOUT1 Gate Drive & OCP
VM
DCM
Step Motor
AOUT2
AISEN
ADECAY BDECAY Gate Drive & OCP OverTemp
BOUT1
VM
DCM
VREFO AVREF BVREF
BOUT2
ISEN
BISEN
GND
Submit Documentation Feedback Product Folder Link(s): DRV8834
DRV8834
Table 1. TERMINAL FUNCTIONS

NAME PIN (PWP) 21, PPAD 18, 19 PIN (RGE) 18, PPAD 15, 16 I/O (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS Both the GND pin and device PowerPAD must be connected to ground Connect to motor supply. A 10-F (minimum) capacitor to GND is recommended. Bypass to GND with 2.2-F (minimum), 6.3-V capacitor. Can be used to provide logic high voltage for configuration pins (except nSLEEP). May be connected to AVREF/BVREF inputs. Do not place a bypass capacitor on this pin. Connect a 0.01-F, 16-V (minimum) X7R ceramic capacitor to VM. Indexer mode: Logic low enables all outputs. Phase/enable mode: Logic low enables the AOUTx outputs. Internal pulldown. Indexer mode: Rising edge moves indexer to next step. Phase/enable mode: Logic low enables the BOUTx outputs. Internal pulldown. Indexer mode: Level sets direction of step. Phase/enable mode: Logic high sets BOUT1 high, BOUT2 low. Internal pulldown. Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M1. Phase/enable mode: Logic high sets AOUT1 high, AOUT2 low. Internal pulldown. Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M0. Phase/enable mode: Determines the state of the outputs when xENBL = 0. Internal pulldown. Logic high to put the device in indexer mode. Logic low to put the device into phase/enable mode. State is latched at power-up and sleep exit. Internal pulldown. Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. Reference voltage for winding current set. Can be driven individually with an external DACs for micro-stepping, or tied to a reference voltage (e.g., VREFO). Reference voltage for winding current set. Can be driven individually with an external DACs for micro-stepping, or tied to a reference voltage (e.g., VREFO). Determines decay mode for H-Bridge A (or A and B in indexer mode) slow, fast or mixed decay Determines decay mode for H-Bridge B slow, fast or mixed decay
POWER AND GROUND GND VM Device ground Bridge A power supply
VINT
20
17
Internal supply
VREFO VCP
24 17
21 14
O O
Reference voltage output High-side gate drive voltage
CONTROL (Indexer Mode or Phase/Enable Mode) nENBL/AENBL 10 7 I Step motor enable/Bridge A enable
STEP/BENBL
11
Step input/Bridge B enable
DIR/BPHASE
12
Direction input/Bridge B Phase
M0/APHASE
13
10
Microstep mode/Bridge A phase
M1
14
11
Microstep mode/Disable state
CONFIG
15
12
Device configuration
nSLEEP
22
Sleep mode input
AVREF
22
19
Bridge A current set reference input
BVREF
23
20
Bridge B current set reference input
ADECAY BDECAY (1)
3 2
24 23
I I
Decay mode for bridge A Decay mode for bridge B
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
DRV8834
Table 1. TERMINAL FUNCTIONS (continued)

NAME STATUS nFAULT OUTPUT AISEN BISEN AOUT1 AOUT2 BOUT1 BOUT2 5 8 4 6 9 7 2 5 1 3 6 4
PWP PACKAGE (TOP VIEW)
PIN (PWP)
PIN (RGE)
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS Logic low when in fault condition (overtemp, overcurrent, undervoltage) Connect to current sense resistor for bridge A, or GND if current control not needed Connect to current sense resistor for bridge B, or GND if current control not needed Connect to motor winding A Connect to motor winding B
16
13
OD
Fault output
IO IO O O O O
Bridge A ground/Isense Bridge B ground/Isense Bridge A output 1 Bridge A output 2 Bridge B output 1 Bridge B output 2
RGE PACKAGE (TOP VIEW)
BDECAY
ADECAY
nS LE E P
V R E FO
nSLEEP BDECAY ADECAY AOUT1 AISEN AOUT2 BOUT2 BISEN BOUT1 nENBL / AENBL STEP / BENBL DIR / BPHASE
1 2 3 4 5 6 7 8 9 10 11 12 GND (PPAD)
24 23 22 21 20 19 18 17 16 15 14 13
VREFO BVREF AVREF GND VINT VM VM VCP nFAULT CONFIG M1 M0 / APHASE
AVREF
BVREF
24
23
22
21
20
AOUT 1 AISEN AOUT 2 BOUT 2 BISEN BOUT 1
19
1 2 3 4 5 6
18 17
GND VINT VM VM VCP nFAULT
GND (PPAD)
16 15 14 13
10
11
nE N B L / A E N B L
S TE P / B E N B L
D IR / B P H A S E
M0 / APHASE
M1
C O N FIG
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DRV8834
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)
VM AVREF, BVREF, VINT, ADECAY, BDECAY Power supply voltage range
(1) (2)
VALUE 0.3 to 11.8
UNIT V
Analog input pin voltage range
-0.5 to 3.6
Digital input pin voltage range xISEN pin voltage Peak motor drive output current, t < 1 s TJ Tstg (1) (2) Operating virtual junction temperature range Storage temperature range
0.5 to 7 0.3 to 0.5 Internally limited 40 to 150 60 to 150
V V A C C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
THERMAL METRIC JA JCtop JB JT JB JCbot Junction-to-ambient thermal resistance (1) Junction-to-case (top) thermal resistance (2) Junction-to-board thermal resistance (3) Junction-to-top characterization parameter
(4)
PWP 24 PINS 40.2 23.7 21.9 0.7 21.7 3.9
RGE 24 PINS 35.1 36.6 12.2 0.6 12.2 4.0
UNITS
C/W
Junction-to-board characterization parameter (5) Junction-to-case (bottom) thermal resistance (6)
xxx
(1) (2) (3) (4) (5) (6) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS

TA = 25C, over operating free-air temperature range (unless otherwise noted)
MIN VM VREF IVINT IVREF VDIGIN IOUT (1) (2) (3) Motor power supply voltage range VREF input voltage range (2) VINT external load current VREF external load current Digital input pin voltage range Continuous RMS or DC output current per bridge (3) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V. Operational at VREF between 0 V and 1 V, but accuracy is degraded. Power dissipation and thermal limits must be observed. -0.3
(1)
NOM
MAX 10.8 2 1 400 5.75 1.5
UNIT V V mA A V A
2.5 1
DRV8834
ELECTRICAL CHARACTERISTICS
PARAMETER POWER SUPPLY IVM IVMQ VUVLO VINT VREFO VM operating supply current VM sleep mode supply current VM undervoltage lockout voltage VINT voltage VREF voltage VM = 5 V, excluding winding current VM = 10 V, excluding winding current VM = 5 V VM = 10 V VM falling VM > 3.3 V, IOUT = 0 A to 1 mA IOUT = 0 A to 400 A nSLEEP All other digital input pins nSLEEP All other digital input pins nSLEEP All except nSLEEP nSLEEP All except nSLEEP, M0 VIN = 0 -20 VIN = 3.3 V, nSLEEP VIN = 3.3 V, all except nSLEEP 312 IO = 5 mA VO = 3.3 V VM = 5 V, I O = 500 mA, TJ = 25C HS FET on resistance RDS(ON) LS FET on resistance VM = 5 V, IO = 500 mA, TJ = 85C VM = 2.7 V, I O = 500 mA, TJ = 25C VM = 2.7 V, IO = 500 mA, TJ = 85C VM = 5 V, I O = 500 mA, TJ = 25C VM = 5 V, IO = 500 mA, TJ = 85C VM = 2.7 V, I O = 500 mA, TJ = 25C VM = 2.7 V, IO = 500 mA, TJ = 85C IOFF fPWM tBLANK tR tF IOCP tOCP Off-state leakage current Current control PWM frequency Current sense blanking time Rise time Fall time Overcurrent protection trip level Overcurrent protection period VREF > 375 mV or DAC codes > 29% VREF < 375 mV or DAC codes < 29% Internal PWM frequency VREF > 375 mV or DAC codes > 29% VREF < 375 mV or DAC codes < 29% VM = 5 V, 16 to GND, 10% to 90% VM VM = 5 V, 16 to GND, 10% to 90% VM 2 1.6 1.1 2 42.5 2.4 1.6 120 100 MOTOR DRIVER kHz s ns ns A s 160 190 200 240 145 180 190 235 2 A 285 240 295 m 6.6 16.5 2.5 2 0.2 0.4 500 200 1 20 13 33 468 0.5 1 250 2.85 1.9 3 2 2.4 2.75 0.6 9.6 2.39 3.15 2.1 0.5 0.7 2 4 mA A V V V TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL REGULATORS
LOGIC-LEVEL INPUTS VIL VIH VHYS RPD IIL IIN IIH tDEG VOL IOH Input low voltage Input high voltage Input hysteresis Input pull-down resistance Input low current Input current (M0) Input high current Input deglitch time Output low voltage Output high leakage current V V V k A A A ns V A
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
H-BRIDGE FETS
PROTECTION CIRCUITS
DRV8834
ELECTRICAL CHARACTERISTICS (continued)

PARAMETER tTSD IREF VTRIP AISENSE Thermal shutdown temperature VREF input current xISEN trip voltage Current sense amplifier gain CURRENT CONTROL VREF = 3.3 V For 100% current step Reference only -1 400 5 1 A mV V/V TEST CONDITIONS Die temperature MIN 150 TYP 160 MAX 180 UNIT C
TIMING REQUIREMENTS
NO. 1 2 3 4 5 6 fSTEP tWH(STEP) tWL(STEP) tSU(STEP) tH(STEP) tWAKE PARAMETER Step frequency Pulse duration, STEP high Pulse duration, STEP low Setup time, command to STEP rising Hold time, command to STEP rising Wakeup time, nSLEEP inactive to STEP
1 2 3
CONDITIONS
MIN 1.9 1.9 200 1
MAX 250
UNIT kHz s s ns s
ms
STEP DIR, M0, M1

4 5
nSLEEP
6
DRV8834
FUNCTIONAL DESCRIPTION Device Configuration

The DRV8834 supports two configurations: phase/enable mode, where the outputs are controlled by phase (direction) and enable signals for each H-bridge, and indexer mode, which allow control of a stepper motor using simple step and direction inputs. DC motors can only be controlled in phase/enable mode; indexer mode is not applicable to DC motors. Stepper motors can be controlled using either phase/enable lode, or indexer mode. The device is configured to be controlled either way using CONFIG pin. Logic HIGH on the CONFIG pin puts the device in the STEP/DIR mode; logic LOW lets the motor to be controlled using the xPHASE/xENBL pins. The state of the CONFIG pin is latched at power-up, and also whenever exiting sleep mode. CONFIG has an internal pull-down resistor.
PWM Motor Drivers

DRV8834 contains two identical H-bridge motor drivers with current-control PWM circuitry. A block diagram of the circuitry is shown below:
OCP VCP, VM VM VM
xOUT1 xON Predrive xOUT 2 xPHASE PWM OCP

Step Motor
From Logic
xISEN
Optional
DAC xI[4:0] 4
/5
xVREF
Figure 1. Motor Control Circuitry
Current Control
The current through the motor windings may be regulated by a fixed-frequency PWM current regulation, or current chopping. With stepping motors, current control is normally used at all times. Often it is used to vary the current in the two windings in a sinusoidal fashion to provide smooth motion. This is referred to as microstepping. The DRV8834 can provide up to 1/32 step microstepping, using internal 5-bit DACs. Finer microstepping can be implemented using the xPHASE/xENBL signals to control the stepper motor, and varying the xVREF voltages. The current flowing through the corresponding H-bridge varies according to the equation given below. A very high degree of microstepping can be achieved through this technique. With DC motors, current control can be used to limit the start-up current of the motor to less than the stall current of the motor.
DRV8834
Current regulation works as follows: When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Note that immediately after the current is enabled, the voltage on the xISEN pin is ignored for a period of time before enabling the current sense circuitry. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode. Note that the blanking time also sets the minimum PWM duty cycle. This can cause current control errors near the zero current level when microstepping. To help eliminate this error, the DRV8834 has a "dynamic" tBLANK time. When the commanded current is low, the blanking period is reduced, which in turn lowers the minimum duty cycle. This provides a smoother current transition across the zero crossing region of the current waveform. The end result is smoother and quieter motor operation. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, with a reference voltage supplied to the AVREF and BVREF pins. In indexer mode, the reference voltages are scaled by internal DACs to provide scaled currents used to perform microstepping. The chopping current is calculated as follows:
ICHOP = 5xVREF RISENSE
(1)
Example: If xVREF is 2 V (as it would be if xVREF is connected directly to VREFO) and a 400-m sense resistor is used, the chopping current will be 2 V/5 x 400 m = 1 A. In indexer mode, this current value is scaled by between 5% and 100% by the internal DACs, as shown in the step table in the "Microstepping Indexer" section of the datasheet. Note that if current control is not needed, the xISEN pins may be connected directly to ground. in this case it is also recommended to connect AVREF and BVREF directly to VREFO.
Current Recirculation and Decay Modes

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 2 as case 1. The current flow direction shown indicates positive current flow in the step table below for indexer mode, or the current flow with xPHASE = 1 in phase/enable mode. Once the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of the motor, the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in through the opposing FETs. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 2 as case 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown as case 3 below.
DRV8834
xVM
1 Drive Current 1 xOUT1 2 xOUT2 2 Fast decay 3 Slow decay
Figure 2. Decay Modes The DRV8834 supports fast, slow, and also mixed decay modes. With DC motors, slow decay is nearly always used to minimize current ripple and optimize speed control; with stepper motors, the decay mode is chosen for a given stepper motor and operating conditions to minimize mechanical noise and vibration. In mixed decay mode, the current recirculation begins as fast decay, but at a fixed period of time (determined by the state of the xDECAY pins shown in Table 2) switches to slow decay mode for the remainder of the fixed PWM period. Table 2. Decay Pin Configuration
RESISTANCE ON xDECAY PIN < 1 k 20 k 5% 50 k 5% 100 k 5% k -OR- VOLTAGE FORCED ON xDECAY PIN < 0.1 V 0.2 V 5% 0.5 V 5% 1 V 5% >2V % OF PWM CYCLE IS FAST DECAY 0% 25% 50% 75% 100%
10
DRV8834
Figure 3 illustrates the current waveforms in slow, fast, and 25% and 75% mixed decay modes.
PWM ON PWM OFF (tOFF)
Slow Decay
Fast Decay
Mixed Decay 25%
Mixed Decay 75% Itrip 25% of cycle PWM CYCLE 75% of cycle
Figure 3. PWM Cycle Decay mode is selected by the voltage present on the xDECAY pins. Internal current sources of 10 A (typical) are connected to the pins, which allows setting of the decay mode by a resistor connected to ground if desired. It is possible to drive the xDECAY pin with a tri-state GPIO pin and also place the resistor to ground. This allows a microcontroller to select fast, slow, or mixed decay modes by driving the pin high, low, or high-impedance. Note that the logic-low voltage must be less than 0.1 V with 10-A of current sourced from the DRV8834 to attain slow decay. In indexer mode, only the ADECAY pin is used, and slow decay mode is always used when at any point in the step table where the current is increasing. When current is decreasing or remaining constant, the decay mode used will be fast, slow, or mixed, as commanded by the ADECAY pin.
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DRV8834
Phase/Enable Mode
In phase/enable mode, the xPHASE input pins control the direction of current flow through each H-bridge. This sets the direction of rotation of a DC motor, or the direction of the current flow in a stepper motor winding. Driving the xENBL input pins active high enables the H-bridge outputs. This can be used as PWM speed control of a DC motor, or to enable/disable the current in a stepper motor. In phase/enable mode, the M1 input pin controls the state of the H-bridges when xENBL = 0. If M1 is high, the outputs are disabled (high impedance) when xENBL = 0; this corresponds to asynchronous fast decay mode, and is usually used in stepper motor applications to command a "zero current" state. If M1 is low, then the outputs are both driven low; this corresponds to slow decay or brake mode, and is usually used when controlling the speed of a DC motor by PWMing the xENBL pin. Table 3. H-Bridge Control Using Phase/Enable Mode
M1 1 0 X X xENBL 0 0 1 1 xPHASE X X 0 1 xOUT1 Z 0 L H xOUT2 Z 0 H L
Indexer Mode
To allow a simple step and direction interface to control stepper motors, the DRV8834 contains a microstepping indexer. The indexer controls the state of the H-bridges automatically. Whenever there's a rising edge at the STEP input, the indexer moves to the next step, according to the direction set by the DIR pin. The nENBL pin is used to disable the output stage in indexer mode. When nENBL = 1, the indexer inputs are still active and will respond to the STEP and DIR input pins; only the output stage is disabled. The indexer logic in the DRV8834 allows a number of different stepping configurations. The M0 and M1 pins are used to configure the stepping format as shown in Table 4. Table 4. Stepping Format
M1 0 0 0 1 1 1 M0 0 1 Z 0 1 Z STEP MODE Full step (2-phase excitation) 1/2 step (1-2 phase excitation) 1/4 step (W1-2 phase excitation) 8 microsteps/step 16 microsteps/step 32 microsteps/step
Note that the M0 pin is a tri-level input. It can be driven logic low, logic high, or high-impedance (Z). The M0 and M1 pins can be statically configured by connecting to VINT, GND, or left open, or can be driven with standard tri-state microcontroller I/O port pins. Their state is latched at each rising edge of the STEP input. The step mode may be changed on-the-fly while the motor is moving. The indexer will advance to the next valid state for the new M0/M1 setting at the next rising edge of STEP. The home state is 45. This state is entered after power-up, after exiting undervoltage lockout, or after exiting sleep mode. This is shown in Table 5 by cells shaded yellow. The following table shows the relative current and step directions for different step mode settings. At each rising edge of the STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.
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DRV8834
Table 5. Current and Step Directions

1/32 STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 24 23 12 22 21 11 6 20 19 10 18 17 9 5 3 16 15 8 14 13 7 4 12 11 6 10 9 5 3 2 1 8 7 4 6 5 3 2 4 3 2 2 1/16 STEP 1 1/8 STEP 1 1/4 STEP 1 1/2 STEP 1 FULL STEP 70% WINDING CURRENT A 100% 100% 100% 99% 98% 97% 96% 94% 92% 90% 88% 86% 83% 80% 77% 74% 71% 67% 63% 60% 56% 51% 47% 43% 38% 34% 29% 24% 20% 15% 10% 5% 0% -5% -10% -15% -20% -24% -29% -34% -38% -43% -47% -51% -56% -60% -63% WINDING CURRENT B 0% 5% 10% 15% 20% 24% 29% 34% 38% 43% 47% 51% 56% 60% 63% 67% 71% 74% 77% 80% 83% 86% 88% 90% 92% 94% 96% 97% 98% 99% 100% 100% 100% 100% 100% 99% 98% 97% 96% 94% 92% 90% 88% 86% 83% 80% 77% ELECTRICAL ANGLE 0 3 6 8 11 14 17 20 23 25 28 31 34 37 39 42 45 48 51 53 56 59 62 65 68 70 73 76 79 82 84 87 90 93 96 98 101 104 107 110 113 115 118 121 124 127 129 13
DRV8834
Table 5. Current and Step Directions (continued)

1/32 STEP 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 14 Submit Documentation Feedback Product Folder Link(s): DRV8834 47 24 46 45 23 12 44 43 22 42 41 21 11 6 3 40 39 20 38 37 19 10 36 35 18 34 33 17 9 5 32 31 16 30 29 15 8 28 27 14 26 25 13 7 4 2 1/16 STEP 1/8 STEP 1/4 STEP 1/2 STEP FULL STEP 70% WINDING CURRENT A -67% -71% -74% -77% -80% -83% -86% -88% -90% -92% -94% -96% -97% -98% -99% -100% -100% -100% -100% -100% -99% -98% -97% -96% -94% -92% -90% -88% -86% -83% -80% -77% -74% -71% -67% -63% -60% -56% -51% -47% -43% -38% -34% -29% -24% -20% -15% WINDING CURRENT B 74% 71% 67% 63% 60% 56% 51% 47% 43% 38% 34% 29% 24% 20% 15% 10% 5% 0% -5% -10% -15% -20% -24% -29% -34% -38% -43% -47% -51% -56% -60% -63% -67% -71% -74% -77% -80% -83% -86% -88% -90% -92% -94% -96% -97% -98% -99% ELECTRICAL ANGLE 132 135 138 141 143 146 149 152 155 158 160 163 166 169 172 174 177 180 183 186 188 191 194 197 200 203 205 208 211 214 217 219 222 225 228 231 233 236 239 242 245 248 250 253 256 259 262
DRV8834
Table 5. Current and Step Directions (continued)

1/32 STEP 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 32 62 61 31 16 60 59 30 58 57 29 15 8 4 56 55 28 54 53 27 14 52 51 26 50 49 25 13 7 1/16 STEP 48 1/8 STEP 1/4 STEP 1/2 STEP FULL STEP 70% WINDING CURRENT A -10% -5% 0% 5% 10% 15% 20% 24% 29% 34% 38% 43% 47% 51% 56% 60% 63% 67% 71% 74% 77% 80% 83% 86% 88% 90% 92% 94% 96% 97% 98% 99% 100% 100% WINDING CURRENT B -100% -100% -100% -100% -100% -99% -98% -97% -96% -94% -92% -90% -88% -86% -83% -80% -77% -74% -71% -67% -63% -60% -56% -51% -47% -43% -38% -34% -29% -24% -20% -15% -10% -5% ELECTRICAL ANGLE 264 267 270 273 276 278 281 284 287 290 293 295 298 301 304 307 309 312 315 318 321 323 326 329 332 335 338 340 343 346 349 352 354 357
nSLEEP Operation
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset (note that this returns the indexer to the home state), the VINT supply is disabled, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high. Since the VINT supply is disabled during sleep mode, it cannot be used to provide a logic high signal to the nSLEEP pin. To simplify board design, the nSLEEP can be pulled up directly to the supply (VM) if it is not actively driven. Unless VM is less than 5.75 V, a pullup resistor is required. The nSLEEP pin is protected by a zener diode that will clamp the pin voltage to approximately 6.5 V. The pullup resistor limits the current to the input in case VM is higher than 6.5 V. The recommended pullup resistor is 20 k - 50 k.
15
DRV8834
When exiting sleep mode, the nFAULT pin will be briefly driven active low as the internal power supplies turn on. nFAULT will return to inactive high once the internal power supplies (including charge pump) have stabilized. This process takes some time (up to 1 ms), before the motor driver becomes fully operational.
Protection Circuits
The DRV8834 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (approximately 1.2 ms) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally. Overcurrent conditions are detected independently on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, so functions even without presence of the xISEN resistors. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume and nFAULT will become inactive. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. The nFAULT pin is driven low during an undervoltage condition, and also at power-up or sleep mode, until the internal power supplies have stabilized.
16
DRV8834
APPLICATIONS INFORMATION
The DRV8834 is a very flexible motor driver. It can be used to drive two DC motors or a stepper motor, in a number of different configurations. The following applications schematics show various configurations and connections for the DRV8834. Note that component values, especially for RSENSE and the DECAY pins, may be different depending on your motor and application. Refer to the information above to determine the best values for these components in your application.
Phase/Enable Mode Driving Two DC Motors

In this configuration, the DRV8834 is used to drive two independent DC motors. Current up to 1 A per motor is possible. The M1 pin is pulled low to allow slow decay PWM from the controller (if desired) to control the motor speed by PWMing the xENBL inputs, and ADECAY and BDECAY are connected to ground to set slow decay mode during current limiting. The value of the RSENSE resistors shown is for a 1-A current limit; if current limiting is not needed, the AISEN and BISEN pins may be connected directly to ground. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-k resistor.
Figure 4. Phase/Enable Mode Driving Two DC Motors
17
DRV8834
Phase/Enable Mode Driving a Stepper Motor

Phase/enable mode can be used with a simple interface to a controller to operate a stepper motor in full, half, or quarter step modes. The decay mode can be set by changing the values of the resistors connected to the ADECAY and BDECAY pins. The M1 pin is driven to logic high (by connecting to the VINT supply), to allow a zero-current (off) state when the xENBL pin is set low. Coil current is set by the RSENSE resistors. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-k resistor.
Figure 5. Phase/Enable Mode Driving a Stepper Motor

1 Step APHASE BPHASE AENBL BENBL A Current
1 Step APHASE BPHASE AENBL BENBL A Current
B Current
B Current
Figure 6. Full Step Sequence (2-Phase)
Figure 7. Half Step Sequence (1-2 Phase)
18
DRV8834
Indexer Mode Driving a Stepper Motor

In indexer mode, only a rising edge on the STEP pin is needed to move the motor to the next step. The DIR pin sets which direction the motor rotates, by reversing the step sequence. The internal indexer can operate in fullstep, half-step, and smaller microsteps up to 1/32-step, depending on the state of the M0 and M1 pins. The M0 and M1 pins can also be connected directly to ground or to VINT to program the step modes, if desired. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-k resistor. Step sequences for full and half step are shown below.
Figure 8. Indexer Mode Driving a Stepper Motor

1 Step STEP DIR A Current
1 Step STEP DIR A Current
B Current
B Current
Figure 9. Full Step Sequence (2-Phase)
Figure 10. Half Step Sequence (1-2 Phase)
19
DRV8834
High-Resolution Microstepping Using a Microcontroller to Modulate VREF Signals

Using a microcontroller with two DAC outputs, very high resolution microstepping can be performed with the DRV8834. In this mode, the coil current direction is controlled by the PHASE pins, and the current in each coil is independently set using the two VREF input pins, which are connected to DACs. In addition, the microcontroller can set the decay mode for each coil dynamically, by driving the xDECAY pin low for slow decay, high for fast decay, or high-impedance which sets mixed decay (based on the value of a resistor connected to ground). If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-k resistor. For more details on this technique, please refer to TI Application Report (SLVA416), "High Resolution Microstepping Driver With the DRV88xx Series".
Figure 11. High-Resolution Microstepping

1 Step APHASE BPHASE AVREF BVREF A Current
B Current
Figure 12. Microstepping Sequence
20
DRV8834
THERMAL INFORMATION Maximum Output Current

In actual operation, the maximum output current achievable with a motor driver is a function of die temperature. This in turn is greatly affected by ambient temperature and PCB design. Basically, the maximum motor current will be the amount of current that results in a power dissipation level that, along with the thermal resistance of the package and PCB, keeps the die at a low enough temperature to stay out of thermal shutdown. The thermal data given in the datasheet can be used as a guide to calculate the approximate maximum power dissipation that can be expected to be possible without entering thermal shutdown for several different PCB constructions. However, for accurate data, the actual PCB design must be analyzed via measurement or thermal simulation.
Thermal Protection
The DRV8834 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 160C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8834 is dominated by the DC power dissipated in the output FET resistance, or RDS(ON). There is additional power dissipated due to PWM switching losses, which are dependent on PWM frequency, rise and fall times, and VM supply voltages. These switching losses are typically on the order of 10% to 20% of the DC power dissipation. The DC power dissipation of one H-bridge can be roughly estimated by Equation 2.
PTOT = (HS - RDS(ON) IOUT(RMS) ) + (LS - RDS(ON) IOUT(RMS) )
(2)
where PTOT is the total power dissipation, HS - RDS(ON) is the resistance of the high side FET, LS - RDS(ON) is the resistance of the low side FET, and IOUT(RMS) is the RMS output current being applied to the motor. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated.
21
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2012
PACKAGING INFORMATION
Orderable Device DRV8834PWP DRV8834PWPR DRV8834RGER DRV8834RGET Status
(1)
Package Type Package Drawing HTSSOP HTSSOP VQFN VQFN PWP PWP RGE RGE
Pins 24 24 24 24
Package Qty 60 2000 3000 250
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing HTSSOP VQFN VQFN PWP RGE RGE 24 24 24
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 180.0 16.4 12.4 12.4 6.95 4.25 4.25
B0 (mm) 8.3 4.25 4.25
K0 (mm) 1.6 1.15 1.15
P1 (mm) 8.0 8.0 8.0
W Pin1 (mm) Quadrant 16.0 12.0 12.0 Q1 Q2 Q2
DRV8834PWPR DRV8834RGER DRV8834RGET
2000 3000 250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jun-2012
*All dimensions are nominal
Device DRV8834PWPR DRV8834RGER DRV8834RGET
Package Type HTSSOP VQFN VQFN
Package Drawing PWP RGE RGE
Pins 24 24 24
SPQ 2000 3000 250
Length (mm) 346.0 346.0 210.0
Width (mm) 346.0 346.0 185.0
Height (mm) 33.0 29.0 35.0
Pack Materials-Page 2
IMPORTANT NOTICE
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www.ti.com SLVSB19A FEBRUARY 2012 REVISED MARCH 2012

DUAL BRIDGE STEPPER OR DC MOTOR DRIVER

VM Internal Ref & Regs Charge Pump VCP 0.01F

AOUT1 Gate Drive & OCP

ADECAY BDECAY Gate Drive & OCP OverTemp

VREFO AVREF BVREF

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Copyright 2012, Texas Instruments Incorporated

Table 1. TERMINAL FUNCTIONS

POWER AND GROUND GND VM Device ground Bridge A power supply

Reference voltage output High-side gate drive voltage

Step input/Bridge B enable

Direction input/Bridge B Phase

Microstep mode/Bridge A phase

Microstep mode/Disable state

Sleep mode input

Bridge A current set reference input

Bridge B current set reference input

ADECAY BDECAY (1)

Decay mode for bridge A Decay mode for bridge B

Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

Copyright 2012, Texas Instruments Incorporated

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Table 1. TERMINAL FUNCTIONS (continued)

RGE PACKAGE (TOP VIEW)

VREFO BVREF AVREF GND VINT VM VM VCP nFAULT CONFIG M1 M0 / APHASE

AOUT 1 AISEN AOUT 2 BOUT 2 BISEN BOUT 1

GND VINT VM VM VCP nFAULT

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Copyright 2012, Texas Instruments Incorporated

ABSOLUTE MAXIMUM RATINGS

VALUE 0.3 to 11.8

Analog input pin voltage range

0.5 to 7 0.3 to 0.5 Internally limited 40 to 150 60 to 150

PWP 24 PINS 40.2 23.7 21.9 0.7 21.7 3.9

RGE 24 PINS 35.1 36.6 12.2 0.6 12.2 4.0

Junction-to-board characterization parameter (5) Junction-to-case (bottom) thermal resistance (6)

RECOMMENDED OPERATING CONDITIONS

MAX 10.8 2 1 400 5.75 1.5

Copyright 2012, Texas Instruments Incorporated

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nFAULT OUTPUT (OPEN-DRAIN OUTPUT)

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Copyright 2012, Texas Instruments Incorporated

ELECTRICAL CHARACTERISTICS (continued)

MIN 1.9 1.9 200 1

STEP DIR, M0, M1

Copyright 2012, Texas Instruments Incorporated

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FUNCTIONAL DESCRIPTION Device Configuration

PWM Motor Drivers

xOUT1 xON Predrive xOUT 2 xPHASE PWM OCP

Figure 1. Motor Control Circuitry

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Copyright 2012, Texas Instruments Incorporated

ICHOP = 5xVREF RISENSE

Current Recirculation and Decay Modes

Copyright 2012, Texas Instruments Incorporated