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ABSTRACT
A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (MUX), and in such an implementation the output of one MUX is connected to the input of the next MUX in a way that depends on the shift distance. The number of multiplexers required for an n-bit word is n X log2(n). A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic. A barrel shifter, comprising: an n-bit by n-bit transistor array arranged into n rows and n columns, wherein the source of a transistor in one row is connected to the source of a transistor in the next row; a first plurality of multiplexors, each having a first and a second input and an output; a second plurality of multiplexors each having inputs and an output, each multiplexor selecting one of three inputs depending on the data length; and a third plurality of multiplexors, each having a first and a second input and an output, the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in the second row and continuing with transistors in ascending bit positions.

HDL LANGUAGE SIMULATOR SYNTHESIS TOOL TARGET DEVICE FAMILY

: VHDL : ISE SIMULATOR : XILINX 9.1i : FPGA : SPARTAN 3E

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BLOCK DIAGRAM :

data(16- bits) clk rst load_shift no. of bits to be shifted(16-bit) dataout(16bits)

BARREL SHIFTER

right/left/circular right/circular left shift

Fig : Block Diagram of Barrel Shifter

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LIST OF FIGURES:

BLOCK DIAGRAM OF BARREL SHIFTER STRUCTURE OF ARRAY SHIFTER STRUCTURE OF LOG SHIFTER CLB LOCATION SPARTON-3E CLB RESOURCES BASYS PROGRAMMING CIRCUIT FLOWCHART STANDARD USB TYPE A/TYPE B CABLE SIMULATION RESULTS LEFT SHIFT RIGHT SHIFT CIRCULAR LEFT SHIFT CIRCULAR RIGHT SHIFT LOGICAL LEFT SHIFT LOGICAL RIGHT SHIFT LOGICAL CIRCULAR RIGHT SHIFT LOGICAL CIRCULAR LEFT SHIFT REGISTER TRANSFER LOGIC TECHNOLOGY SCHEMATIC DESIGN SUMMARY PIN ASSIGNMENT PIN ALLOCATION

2 6 7 24 24 26 30 38 42 43 43 44 44 45 45 46 47 48 48 49 49

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CHAPTER 1 INTRODUCTION 1.1 Introduction to barrel shifter

A hardware device that can shift or rotate a data word by any number of bits in a single operation. It is implemented like a {multiplexer}, each output can be connected to any input depending on the shift distance. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits. It can be implemented as a sequence of multiplexers. In this implementation, the output of one MUX is connected to the input of the next MUX in a way that depends on the shift distance. The number of multiplexers required is n*log2(n), for an n bit word. Four common word sizes and the number of multiplexers needed are listed below:

64-bit 64 * log2(64) = 64 * 6 = 384 32-bit 32 * log2(32) = 32 * 5 = 160 16-bit 16 * log2(16) = 16 * 4 = 64 8-bit 8 * log2(8) = 8 * 3 = 24

Basically, a barrel shifter works to shift data by incremental stages which avoids extra clocks to the register and reduces the time spent shifting or rotating data (the specified number of bits are moved/shifted/rotated the desired number of bit positions in a single clock cycle). A barrel shifter is commonly used in computer-intensive applications, such as Digital Signal Processing (DSP), and is useful for most applications that shift data left or right - a normal style for C programming code.

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Rotation (right) is similar to shifting in that it moves bits to the left. With rotation, however, bits which "fall off" the left side get tacked back on the right side as lower order bits, while in shifting the empty space in the lower order bits after shifting is filled with zeros. Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of mobile computing, power has become as important as speed for circuit designs. In this project we present a range of 32-bit barrel shifters that vary at the gate, architecture, and environment levels.

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CHAPTER 2 FUNCTION OF BARREL SHIFTER

Each shifter will be designed as a 16-bit shifter that receives a 16-bit input data value along with a twos compliment encoded shift value, and will produce a 16- bit shifted result. This section will describe the internal design characteristics for each shifter.

2.1 Architecture
There are two common architectural layouts for shifts, array shifter and logarithmic shifters. An array shifter(Fig. 1) decodes the shift value into individual shift bit lines that mesh across all input data values. At each crossing point, a gate will either allow or not allow the input data value to pass to the output line, controlled by a shift bit line. The advantage of this design is that there is only ever one gate between the input data lines and the output data lines, so it is fast. The disadvantages of this design are the requirement for a decoder, and the fact that each input data line sees a load from every shift bit line.

Fig. 1: Structure of an array shifter.

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In a logarithmic shifter(Fig. 2), the shifter is divided into loga(n) stages, where n is the input data length. Each bit of the encoded shift value is sent to a different stage of the shifter. Each stage handles a single, powerof- two shift. The input data will be shifted or not shifted by each of the stages in sequence. Five stages would be required when considering 32 bit data. The advantage of a log shifter is that it has small area and does not require a decoder, but the disadvantage is that there are five levels of gates separating the input data from the output data. There are two types of gates that are required for these shifters: the array shifter requires switches that will either propagate or not propagate an input data

bit, and the log shifter requires 2-to-1 muxes to propagate either a shifted or a non-shifted bit. In this project we will consider two types of CMOS switches: (1) ntype pass transistor switch; and (2) a full transmission gate switch; and we will consider four types of mux

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designs: (1) n-type pass transistor mux; (2) full transmission mux; (3) a static CMOS mux; and (4) a dynamic logic mux. The pass transistor and transmission gates are simple and fast, but will require occasional buffering to strengthen the signals in the log shifters. The static and dynamic gates are self buffering so no additional buffers are needed, but contain more transistors. The dynamic gate design is the only type that requires a clock signal for a precharge stage. Figure 3 shows schematics for each gate design.

2.2 ARRAY SHIFT:

An array shifter consists of four different shifts in each type of shift the data is shifted uniquely, depending on the direction and specification of the data to be shifted the shifts are titled. In the enclosed vhdl code for barrel shifter condition 1 specifies whether the shift desired is an array shift or logical shift. If the condition 1 is high then the array shift is implemented for shifting the bits in the user specified data. After the declaration of condition1 the desired shift is implemented by the next condition i.e condition2. In this condition the user can specify one of the four types of shifts by passing binary digits specified. The four types of array shifts are as follows Left shifting Right shifting Right Rotation Left Rotation

2.2.1 LEFT SHIFTING:

In the left shifting the given 16 bit data is shifted bit wise in left side. The number of bits to be shifted is intialized by the condition3. Depending on the number of bits to be shifted specified in condition 3 the given data is shifted bit wise to left and zeros are appended in the other side. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 00 i.e left shifter and condition3 as 0001 i.e a single bit shift in left direction. Now the 4 bit data present in din is shifted to its left by one bit continuously till all the 4 bits are shifted. Therefore the Dout=1100,1000,0000. output data is

2.2.2 RIGHT SHIFTING:

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In the right shifting the given 4 bit data is shifted bit wise in right side. The number of bits to be shifted is intialized by the condition3. Depending on the number of bits to be shifted specified in condition 3 the given data is shifted bit wise to right and zeros are appended in the other side. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 01 i.e right shifter and condition3 as 0001 i.e a single bit shift in right direction. Now the 4 bit data present in din is shifted to its right by one bit continuously till all the 4 bits are shifted. Therefore the Dout=0011,0001,0000 output data is

2.2.3 RIGHT ROTATION:

Right rotation is similar to right shifting, except that additional hardware is required to determine which values get shifted into the upper bits of the output. We consider three options: (1) a wrap around least significant bit for right rotation; (2) a sign bit for arithmetic right shifting; and (3) GND for signed magnitude right shifting. A 3-to-1 control mux was added to each wrap around bit line. This mux allows either the rotation wrap-around bit, the sign bit, or GND to be selected. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 10 i.e right rotation and condition3 as 0001 i.e a single bit shift . Now the 4 bit data present in din is shifted to its right by one bit continuously till all the 4 bits are shifted. Therefore the Dout=0011,1001,1100 output data is

2.2.4 LEFT ROTATION:

Left rotations can be accomplished by rotating right 32 - Rotatereft bits. Rotate,i,ht can be calculated by taking the two's-compliment of the Rotateleft value, which requires inverting all the Rotateleft bits and adding one. The inversion of the Rotateleft bits can be accomplished by adding muxes that pass either the shift bit or its inverse. The addition of one to Rotateleft can be accomplished in two ways: (1) include a 5 bit incrementor; or (2) add an additional one-bit shift stage.

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Left shifting can be performed by right shifting 16 - S h i f t l e f t bits, and including an additional row of pull down gates that mask out the lower n bits of the n bit left shift. A second method is to initially reverse the input data bits and perform a right shift of length Shiftleft, and finally reverse the output bits. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 11 i.e. left rotation and condition3 as 0001 i.e a single bit shift . Now the 4 bit data present in din is shifted to its left by one bit continuously till all the 4 bits are shifted. Therefore the output data is Dout=1100,1001,0011,0110.

2.3 LOGICAL SHIFT:

A logical shifter consists of four different shifts in each type of shift the data is shifted uniquely, depending on the direction and specification of the data to be shifted the shifts are titled. In the enclosed vhdl code for barrel shifter condition 1 specifies whether the shift desired is an a logical shift or array shift. If the condition 1 is low then the logical shift is implemented for shifting the bits in the user specified data. After the declaration of condition1 the desired shift is implemented by the next condition i.e condition2. In this condition the user can specify one of the four types of shifts by passing binary digits specified. The four types of a logical shifts are as follows Logical Left shifting Logical Right shifting Logical Right Rotation Logical Left Rotation

2.3.1 LOGICAL LEFT SHIFTING:

In the logical left shifting the given 16 bit data is shifted bit wise in left side. The number of bits to be shifted is not user defined. In the logical shift 2n bits are sifted at a time where n=0,1,2,3. The condition3 is not significant for logical shift. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 and zeros are appended in the other side. For example let us consider a 4 bit input data as Din=

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0110. Let us assume the condition2 as 00 i.e logical left shifter . Now the 4 bit data present in din is shifted to its left by one bit initially and goes on till all the 4 bits are shifted. Therefore the output data is Dout= 1100,0000.

2.3.2 LOGICAL RIGHT SHIFTING:

In the logical right shifting the given 16 bit data is shifted bit wise in right side. The number of bits to be shifted is not user defined. In the logical shift 2n bits are shifted at a time where n=0,1,2,3. The condition3 is not significant for logical shift. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 and zeros are appended in the other side. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 01 i.e logical right shifter . Now the 4 bit data present in din is shifted to its right by one bit initially and goes on till all the 4 bits are shifted. Therefore the output data is Dout= 0011,0000.

2.3.3 LOGICAL RIGHT ROTATION:

In the logical right rotation the given 16 bit data is shifted bit wise in right side. The number of bits to be shifted is not user defined. In the logical shift 2n bits are shifted at a time where n=0,1,2,3. The condition3 is not significant for logical shift. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 . instead of zeros getting appended the most significant bits are shifted to least significant bit positions. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 10 i.e logical right rotation . Now the 4 bit data present in din is shifted to its right by one bit initially and goes on till all the 4 bits are shifted. Therefore the output data is Dout= 0011,1100.

2.3.4 LOGICAL LEFT ROTATION:

In the logical left rotation the given 16 bit data is shifted bit wise in left side. The number of bits to be shifted is not user defined. In the logical shift 2n bits are shifted at a time where n=0,1,2,3. The condition3 is not significant for logical shift. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 .

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instead of zeros getting appended the most significant bits are shifted to least significant bit positions. For example let us consider a 4 bit input data as Din= 0110. Let us assume the condition2 as 11 i.e logical left rotation . Now the 4 bit data present in din is shifted to its left by one bit initially and goes on till all the 4 bits are shifted. Therefore the output data is Dout= 0011,1100.

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CHAPTER 3 AN INTRODUCTION TO XILINX 9.1i and SPARTAN 3E FPGA KIT

The ISE 9.1i provides Xilinx PLD designers with the basic design process using ISE 9.1i. This chapter contains the following sections: Create a New Project Create an HDL Source Design Simulation Create Timing Constraints Implement Design and Verify Constraints Reimplement Design and Verify Pin Locations Download Design to the Spartan-3E Demo Board

3.1 Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field.

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3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3E Device: XC3S250E Package: TQ144 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL (or Verilog) Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:

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7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.

3.2 Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the Creating a VHDL Source section below, or skip to the Creating a Verilog Source section. Creating a VHDL Source Create a VHDL source file for the project as follows: 1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next.

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6. Declare the ports for the counter design by filling in the port information. 7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. 8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

3.3 Design Simulation

Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: The counter must operate correctly with an input clock frequency = 25 MHz. The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. Page 16

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The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: Clock High Time: 20 ns. Clock Low Time: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Offset: 0 ns. Global Signals: GSR (FPGA) Initial Length of Test Bench: 1500 ns.

Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.

Leave the default values in the remaining fields. 8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down.

Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons. 10. Save the waveform. 11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.

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12. Close the test bench waveform.

3.4 Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window. 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To view your simulation results, select the Simulation tab and zoom in on the transitions. The simulation waveform results will look like the following: Note: You can ignore any rows that start with TX. 4. Verify that the counter is counting up and down as expected. 5. Close the simulation view. If you are prompted with the following message, You have an active simulation open. Are you sure you want to close it?, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.

3.5 Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. The timing is specified by entering constraints that guide the placement and routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which

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your design must operate inside the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.

3.5.1 Entering Timing Constraints

To constrain the design do the following: 1. Select Synthesis/Implementation from the drop-down list in the Sources window. 2. Select the counter HDL source file. 3. Click the + sign next to the User Constraints processes group, and double-click the Create Timing Constraints process.ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). 4. Click Yes to add the UCF file to your project. The counter.ucf file is added to your project and is visible in the Sources window. The Xilinx constraints Editor opens automatically. Note: You can also create a UCF file for your project by selecting Project Create New Source. In the next step, enter values in the fields associated with CLOCK in the Constraints Editor Global tab. 5. Select CLOCK in the Clock Net Name field, then select the Period toolbar button or double-click the empty Period field to display the Clock Period dialog box. 6. Enter 40 ns in the Time field.

3.6 Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the previous section.

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Implementing the Design 1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process In the Processes tab. 3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings. 5. Locate the Performance Summary table near the bottom of the design Summary. 6. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify that the design meets the specified timing requirements.

Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 Startup Kit demo board. To constrain the design ports to package pins, do the following: 1. Verify that counter is selected in the Sources window. 2. Double-click the Assign Package Pins process found in the User constraints process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. 3. Select the Package View tab. 4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information: CLOCK input port connects to FPGA pin T9 (GCK0 signal on board) COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board) COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board) COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board) COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board)

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DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)

Notice that the assigned pin locations are shown in blue:

5. Select File Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE. Notice that the Implement Design processes have an orange question mark next to them, indicating they are out-of-date with one or more of the design files. This is because the UCF file has been modified.

3.7 Download Design to the Spartan-3E Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3E Starter Kit demo board. 1. Connect the 5V DC power cable to the power input on the demo board (J4).

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2. Connect the download cable between the PC and demo board (J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select counter in the Sources window. 5. In the Processes window, click the + sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx WebTalk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project only and click OK. iMPACT opens and the Configure Devices dialog box is displayed. 9. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 10. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter. bit file and click Open. 14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens. 17. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 18. Close iMPACT without saving.

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3.8 Introduction to FPGA:

As described in Architectural Overview, the Spartan-3E FPGA architecture consists of five fundamental functional elements: Input/output Blocks (IOBs) Configurable Logic Block (CLB) Block RAM Dedicated Multipliers Digital Clock Managers (DCMs)

3.8.1 Input/output Blocks (IOBs)

The Input/Output Block (IOB) provides a programmable, unidirectional or bidirectional interface between a package pin and the FPGAs internal logic. The IOB is similar to that of the Spartan-3 family with the following differences: Input-only blocks are added Programmable input delays are added to all blocks DDR flip-flops can be shared between adjacent IOBs

3.8.2 Configurable Logic Block (CLB)

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB contains four slices, and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be used as flip-flops or latches. The LUTs can be used as a 16x1 memory (RAM16) or as a 16-bit shift register (SRL16), and additional

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multiplexers and carry logic simplify wide logic and arithmetic functions. Most generalpurpose logic in a design is automatically mapped to the slice resources in the CLBs. Each CLB is identical, and the Spartan-3E family CLB structure is identical to that for the Spartan-3E family.

CLB Array
The CLBs are arranged in a regular array of rows and columns as shown in Figure 14. Each density varies by the number of rows and columns of CLBs.

Fig 3 CLB Locations

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Table 1. Spartan-3E CLB Resources

3.8.3 Interconnect
Interconnect is the programmable network of signal pathways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DCMs, and block RAM.

3.8.4 Overview
Interconnect, also called routing, is segmented for optimal connectivity. Functionally, interconnect resources are identical to that of the Spartan-3 architecture. There are four kinds of interconnects: long lines, hex lines, double lines, and direct lines. The Xilinx Place and Route (PAR) software exploits the rich interconnect array to deliver optimal system performance and the fastest compile times.

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Fig4.Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)

3.9 Introduction to Spartan 3E FPGA:

The Basys board is a circuit design and implementation platform that anyone can use to gain experience building real digital circuits. Built around a Xilinx Spartan-3E Field Programmable Gate Array and a Cypress EZUSB controller, the Basys board provides complete, ready-to-use hardware suitable for hosting circuits ranging from basic logic devices to complex controllers. A large collection of on-board I/O devices and all required FPGA support circuits are included, so countless designs can be created without the need for any other components.

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Four standard expansion connectors allow designs to grow beyond the Basys board using breadboards, user-designed circuit boards, or Pmods (Pmods are inexpensive analog and digital I/O modules that offer A/D & D/A conversion, motor drivers, sensor inputs, and many other features). Signals on the 6-pin connectors are protected against ESD damage and short-circuits, ensuring a long operating life in any environment. The Basys board works seamlessly with all versions of the Xilinx ISE tools, including the free WebPack. It ships with a USB cable that provides power and a programming interface, so no other power supplies or programming cables are required

Figure 5. Basys programming circuit locations

3.9.1 Board Power

The Basys board is typically powered from a USB cable, but a power jack and battery connector are also provided so that external supplies can be used. To use USB power, set the power source switch (SW8) to USB and attach the USB cable. To use an external wallplug power supply, set SW8 to EXT and attach a 5VDC to 9VDC supply to the centerpositive, 2.1/5.5mm power jack. To use battery power, set SW8 to EXT and attach a 4V9V battery pack to the 2-pin, 100-mil spaced battery connector (four AA cells in series

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make a good 6+/- volt supply). Voltages higher than 9V on either power connector may cause permanent damage. SW8 can also be used to turn off main power by setting it to the unused power input (e.g., if USB power is used, setting SW8 to EXT will shut off board power without unplugging the USB cable). Input power is routed through the power switch (SW8) to the four 6- pin expansion connectors and to a National Semiconductor LP8345 voltage regulator. The LP8345 produces the main 3.3V supply for the board, and it also drives secondary regulators to produce the 2.5V and 1.2V supply voltages required by the FPGA. Total board current is dependent on FPGA configuration, clock frequency, and external connections. In test circuits with roughly 20K gates routed, a 50MHz clock source, and all LEDs illuminated, about 100mA of current is drawn from the 1.2V supply, 50mA from the 2.5V supply, and 50mA from the 3.3V supply. Required current will increase if larger circuits are configured in the FPGA, or if peripheral boards are attached.

3.9.2 Configuration
After power-on, the FPGA on the Basys board must be configured before it can perform any useful functions. During configuration, a bit file is transferred into memory cells within the FPGA to define the logical functions and circuit interconnects. The free ISE/WebPack CAD software from Xilinx can be used to create bit files from VHDL, Verilog, or schematic-based source files. Digilents PC-based program called Adept can be used to configure the FPGA with any suitable bit file stored on the computer. Adept uses the USB cable to transfer a selected bit file from the PC to the FPGA (via the FPGAs JTAG programming port). Adept can also program a bit file into an on-board non-volatile ROM called Platform Flash. Once programmed, the Platform Flash can automatically transfer a stored bit file to the FPGA at a subsequent power-on or reset event if the Mode Jumper is set to ROM. The FPGA will remain configured until it is reset by a power-cycle event or by the FPGA reset button (BTNR) being pressed. The Platform Flash ROM will retain a bit file until it is reprogrammed, regardless of power-cycle events.

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To program the Basys board, attach the USB cable to the board. Start the Adept software, and wait for the FPGA and the Platform Flash ROM to be recognized. Use the browse function to associate the desired .bit file with the FPGA, and/or the desired .mcs file with the Platform Flash ROM. Right-click on the device to be programmed, and select the program function. The configuration file will be sent to the FPGA or Platform Flash, and the software will indicate whether programming was successful. The configuration done LED (LD_D) will also illuminate after the FPGA has been successfully configured.

3.9.3 Oscillators
The Basys board includes a primary, user settable silicon oscillator that produces 25MHz, 50MHz, or 100MHz based on the position of the clock select jumper at JP4. A socket for a second oscillator is provided at IC7 (the IC7 socket can accommodate any 3.3V CMOS oscillator in a half-size DIP package). The primary and secondary oscillators are connected to global clock input pins at pin 54 and pin 53 respectively

3.9.4 User I/O

Four pushbuttons and eight slide switches are provided for circuit inputs. Pushbutton inputs are normally low and driven high only when the pushbutton is pressed. Slide switches generate constant high or low inputs depending on position. Pushbuttons and slide switches all have series resistors for protection against short circuits (a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). Eight LEDs and a four-digit seven segment LED display are provided for circuit outputs. LED anodes are driven from the FPGA via current-limiting resistors, so they will illuminate when a logic 1 is written to the corresponding FPGA pin. A ninth LED is provided as a power-indicator LED, and a tenth LED (LD-D) illuminates any time the FPGA has been successfully programmed.

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3.9.5 PS/2 Port
The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. Most PS/2 devices can operate from a 3.3V supply, but some older devices may require a 5VDC supply. A jumper on the Basys board (JP1) selects whether 3.3V or VU is supplied to the PS/2 connector. For 5V, set JP1 to VU and ensure that Basys is powered with a 5VDC wall plug supply. For 3.3V, set the jumper to 3.3V. For 3.3V operation, any board power supply (including USB) can be used. Both the mouse and keyboard use a two-wire serial bus (clock and data) to communicate with a host device. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers The clock and data signals are only driven when data transfers occur, and otherwise they are held in the idle state at logic 1. The timings define signal requirements for mouseto-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.

CHAPTER 4 IMPLEMENTATION 4.1 FLOW CHART:

Start

Specifications Of Barrel Shifter

Analysis
VHDL Design of Barrel Shifter

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Functional Simulation

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YES Error ?

Synthesis

Floor Planning, Placement & Routing

Bit file

Dumping on Spartan 3E FPGA

4.2 VHDL CODE FOR BARREL SHIFTER:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity barrel_shft is Port ( clk : in STD_LOGIC;

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rst : in STD_LOGIC; --din : in STD_LOGIC_VECTOR (15 downto 0); cond1 : in STD_LOGIC; cond2 : in STD_LOGIC_VECTOR (1 downto 0); cond3 : in STD_LOGIC_VECTOR (3 downto 0); dout : out STD_LOGIC_VECTOR (15 downto 0)); end barrel_shft; architecture Behavioral of barrel_shft is signal i: std_logic_vector(15 downto 0); signal din : STD_LOGIC_VECTOR (15 downto 0):="0011001111001100"; signal sclk: std_logic:='0'; signal logical:std_logic_vector(3 downto 0); signal cnt:std_logic_vector(2 downto 0):="000"; begin process(rst,clk) begin if(rst='1') then i<=din; elsif(clk'event and clk='1') then if(cond1='1') then case cond2 is when "00" => case cond3 is when "0000" => i<=i; when "0001" => i<=i(14 downto 0)& '0';

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when "0010" => i<=i(13 downto 0) & "00"; when "0011" => i<=i(12 downto 0) & "000"; when "0100" => i<=i(11 downto 0) & "0000"; when "0101" => i<=i(10 downto 0) & "00000"; when "0110" => i<=i(9 downto 0) & "000000"; when "0111" => i<=i(8 downto 0) & "0000000"; when "1000" => i<=i(7 downto 0) & "00000000"; when "1001" => i<=i(6 downto 0) & "000000000"; when "1010" => i<=i(5 downto 0) & "0000000000"; when "1011" => i<=i(4 downto 0) & "00000000000"; when "1100" => i<=i(3 downto 0) & "000000000000"; when "1101" => i<=i(2 downto 0) & "0000000000000"; when "1110" => i<=i(1 downto 0) & "00000000000000"; when "1111" => i<=i(0) when others => i<=i; end case; & "000000000000000";

when "01" => case cond3 is when "0000" => i<=i; when "0001" => i<= '0' & i(15 downto 1); when "0010" => i<= "00" & i(15 downto 2); when "0011" => i<="000" & i(15 downto 3); when "0100" => i<="0000" & i(15 downto 4) ; when "0101" => i<="00000" & i(15 downto 5) ; when "0110" => i<="000000" & i(15 downto 6) ; when "0111" => i<="0000000" & i(15 downto 7) ; when "1000" => i<="00000000" & i(15 downto 8) ; when "1001" => i<="000000000" & i(15 downto 9) ;

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when "1010" => i<="0000000000" & i(15 downto 10); when "1011" => i<="00000000000" & i(15 downto 11); when "1100" => i<="000000000000" & i(15 downto 12) ; when "1101" => i<="0000000000000" & i(15 downto 13) ; when "1110" => i<="00000000000000" & i(15 downto 14) ; when "1111" => i<="000000000000000" &i(15) when others => i<=i; end case; when "10" => case cond3 is when "0000" => i<=i; when "0001" => i<=i(14 downto 0)& i(15); when "0010" => i<=i(13 downto 0) & i(15 downto 14); when "0011" => i<=i(12 downto 0) & i(15 downto 13); when "0100" => i<=i(11 downto 0) & i(15 downto 12); when "0101" => i<=i(10 downto 0) & i(15 downto 11); when "0110" => i<=i(9 downto 0) & i(15 downto 10); when "0111" => i<=i(8 downto 0) & i(15 downto 9); when "1000" => i<=i(7 downto 0) & i(15 downto 8); when "1001" => i<=i(6 downto 0) & i(15 downto 7); when "1010" => i<=i(5 downto 0) & i(15 downto 6); when "1011" => i<=i(4 downto 0) & i(15 downto 5); when "1100" => i<=i(3 downto 0) & i(15 downto 4); when "1101" => i<=i(2 downto 0) & i(15 downto 3); when "1110" => i<=i(1 downto 0) & i(15 downto 2); when "1111" => i<=i(0) when others => i<=i; end case; & i(15 downto 1); ;

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when "11" => case cond3 is when "0000" => i<=i; when "0001" => i<=i(0)& i(15 downto 1); when "0010" => i<=i(1 downto 0) & i(15 downto 2); when "0011" => i<=i(2 downto 0) & i(15 downto 3); when "0100" => i<=i(3 downto 0) & i(15 downto 4); when "0101" => i<=i(4 downto 0) & i(15 downto 5); when "0110" => i<=i(5 downto 0) & i(15 downto 6); when "0111" => i<=i(6 downto 0) & i(15 downto 7); when "1000" => i<=i(7 downto 0) & i(15 downto 8); when "1001" => i<=i(8 downto 0) & i(15 downto 9); when "1010" => i<=i(9 downto 0) & i(15 downto 10); when "1011" => i<=i(10 downto 0) & i(15 downto 11); when "1100" => i<=i(11 downto 0) & i(15 downto 12); when "1101" => i<=i(12 downto 0) & i(15 downto 13); when "1110" => i<=i(13 downto 0) & i(15 downto 14); when "1111" => i<=i(14 downto 0) & i(15); when others => i<=i; end case;

when others => i<= i; end case; elsif(cond1='0') then cnt<=cnt+"001"; case cnt is

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when "000" => logical<="0000"; when "001" => logical <="0001"; when"010" => logical <="0010"; when "011"=> logical <="0100"; when "100"=> logical <="1000"; when others => logical<="0000"; end case; case cond2 is when "00" => case logical is when "0000" => i<=i; when "0001" => i<=i(14 downto 0)& '0'; when "0010" => i<=i(13 downto 0) & "00"; when "0100" => i<=i(11 downto 0) & "0000"; when "1000" => i<=i(7 downto 0) & "00000000"; when others => i<=i; end case;

when "01" => case logical is when "0000" => i<=i; when "0001" => i<= '0' & i(15 downto 1); when "0010" => i<= "00" & i(15 downto 2); when "0100" => i<="0000" & i(15 downto 4) ; when "1000" => i<="00000000" & i(15 downto 8) ; when others => i<=i; end case;

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when "10" => case logical is when "0000" => i<=i; when "0001" => i<=i(14 downto 0)& i(15); when "0010" => i<=i(13 downto 0) & i(15 downto 14); when "0100" => i<=i(11 downto 0) & i(15 downto 12); when "1000" => i<=i(7 downto 0) & i(15 downto 8); when others => i<=i; end case;

when "11" => case logical is when "0000" => i<=i; when "0001" => i<=i(0)& i(15 downto 1); when "0010" => i<=i(1 downto 0) & i(15 downto 2); when "0100" => i<=i(3 downto 0) & i(15 downto 4); when "1000" => i<=i(7 downto 0) & i(15 downto 8); when others => i<=i; end case;

when others => i<= i; end case; if(cnt="100")then

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cnt<="000"; end if; end if; end if; dout<=i; end process; process(clk) variable cnt:integer:=0; begin if(clk'event and clk='1') then cnt:=cnt +1; if(cnt=25000000)then sclk<=not sclk; cnt:=0; end if; end if; end process; end Behavioral;

4.3 Dumping Procedure Programming through JTAG

For programming the FPGA we need a JTAG cable which is a 6 pin cable converted to a parallel port cable connected to CPU, So the FPGA is programmed through this cable. And this type of programming is called flash programming.

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Connecting the USB Cable The kit includes a standard USB Type A/Type B cable, similar to the one shown in Figure . The actual cable colour might vary from the picture.

Standard USB Type A/Type B Cable

The wider and narrower Type A connector fits the USB connector at the back of the computer. After installing the Xilinx software, connect the square Type B connector to the Spartan-3E Starter Kit board, as shown in Figure 19 . The USB connector is on the left side of the board, immediately next to the Ethernet connector. When the board is powered on, the Windows operating system should recognize and install the associated driver software. When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating a good connection. Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable to the starter kit board and apply power to the board. Then, double-click Configure Device (iMPACT) from within Project Navigator, as shown in Figure20.

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Double-Click to Invoke iMPACT If the board is connected properly, the iMPACT programming software automatically recognizes the three devices in the JTAG programming file, as shown in Figure 21. If not already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it. Right-click the FPGA and select Assign New Configuration File. Select the desired FPGA configuration file and click OK.

Right-Click to Assign a Configuration File to the Spartan-3E FPGA If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in Figure 22. This message can be safely

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ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.

iMPACT Issues a Warning if the StartUp Clock Was Not CCLK

To start programming the FPGA, right-click the FPGA and select Program. The iMPACT software reports status during programming process. Direct programming to the FPGA takes a few seconds to less than a minute, depending on the speed of the PCs USB port and the iMPACT settings.

Figure 23: Right-Click to Program the Spartan-3E FPGA

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When the FPGA successfully programs, the iMPACT software indicates success, as shown in Figure 24 The FPGA application is now executing on the board and the DONE pin LED (see Figure 17) lights up.

iMPACT Programming Succeeded, the FPGAs DONE Pin is High

CHAPTER 5 RESULTS

5.1 SIMULATION RESULTS FOR ARRAY SHIFT

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Fig .1: simulation result for left shift

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Fig.2: Simulation results for right shift

Fig3: Simulation results for circular left shift

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Fig4: simulation results for circular right shift

5.2 SIMULATION RESULTS FOR LOGICAL SHIFT

Fig6: logical left shift

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Fig7: logical right shift

Fig8: logical circular right shift

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Fig9: logical circular left shift

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5.3 REGISTER TRANSFER LOGIC FOR BARREL SHIFTER:

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Fig 10: Register Transfer Logic for Barrel shifter

Fig11:technology schematic for barrel shifter

Fig 12: Design summary for Barrel shifter

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Fig 13: Pin assignment for barrel shifter

Fig 14: Pin allocation

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5.4 REPORTS 5.4.1 SYNTHESIS REPORT:

Release 9.2i - xst J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 1.00 s --> Reading design: barrel_shft.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT

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================================================================= ======== * ======== ---- Source Parameters Input File Name Input Format : "barrel_shft.prj" : mixed Synthesis Options Summary * =================================================================

Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES Page 52 : barrel_shft : YES : Auto : No : "barrel_shft" : NGC : xc3s250e-4-tq144

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ROM Style Mux Extraction Resource Sharing Multiplier Style : Auto : YES : YES : NO : No : auto

Asynchronous To Synchronous Automatic Register Balancing ---- Target Options Add IO Buffers Global Maximum Fanout Register Duplication Slice Packing Use Clock Enable Use Synchronous Set Use Synchronous Reset Pack IO Registers into IOBs Equivalent register Removal ---- General Options Optimization Goal Optimization Effort Library Search Order Keep Hierarchy RTL Output Global Optimization Read Cores Write Timing Constraints Cross Clock Analysis Hierarchy Separator :/ : YES

: 500 : 24 : YES : YES : Yes : Yes : Yes : auto : YES

Add Generic Clock Buffer(BUFG)

Optimize Instantiated Primitives : NO

: Speed :1 : barrel_shft.lso : NO : Yes : AllClockNets : YES : NO : NO

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Bus Delimiter Case Specifier Slice Utilization Ratio BRAM Utilization Ratio Verilog 2001 Auto BRAM Packing Slice Utilization Ratio Delta : <> : maintain : 100 : 100 : YES : NO :5

================================================================= ========

================================================================= ======== * ======== Compiling vhdl file "D:/Xilinx/a/barrel_shft.vhd" in Library work. Architecture behavioral of Entity barrel_shft is up to date. ================================================================= ======== * ======== Analyzing hierarchy for entity <barrel_shft> in library <work> (architecture <behavioral>). Design Hierarchy Analysis * ================================================================= HDL Compilation * =================================================================

================================================================= ======== * HDL Analysis * Page 54

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================================================================= ======== Analyzing Entity <barrel_shft> in library <work> (Architecture <behavioral>). INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 76: Mux is complete : default of case is discarded INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 99: Mux is complete : default of case is discarded INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 121: Mux is complete : default of case is discarded INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 143: Mux is complete : default of case is discarded INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 143: Mux is complete : default of case is discarded INFO:Xst:1561 - "D:/Xilinx/a/barrel_shft.vhd" line 213: Mux is complete : default of case is discarded WARNING:Xst:819 - "D:/Xilinx/a/barrel_shft.vhd" line 47: The following signals are missing in the process sensitivity list: din, i. Entity <barrel_shft> analyzed. Unit <barrel_shft> generated.

================================================================= ======== * ======== Performing bidirectional port resolution... Synthesizing Unit <barrel_shft>. Related source file is "D:/Xilinx/a/barrel_shft.vhd". HDL Synthesis * =================================================================

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WARNING:Xst:653 - Signal <din> is used but never assigned. Tied to value 0011001111001100. Using one-hot encoding for signal <logical>. WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. Found 3-bit up counter for signal <cnt>. Found 32-bit up counter for signal <cnt0>. Found 32-bit adder for signal <cnt0$addsub0000> created at line 234. Found 16-bit register for signal <i>. Found 1-bit 16-to-1 multiplexer for signal <i_0$mux0001> created at line 127. Found 1-bit 16-to-1 multiplexer for signal <i_15$mux0001> created at line 104. Found 5-bit register for signal <logical>. Found 1-bit register for signal <sclk>. Summary: inferred 2 Counter(s). inferred 22 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 2 Multiplexer(s). Unit <barrel_shft> synthesized.

================================================================= ======== HDL Synthesis Report Macro Statistics # Adders/Subtractors 32-bit adder # Counters 3-bit up counter 32-bit up counter # Registers :1 :2 :1 :1 : 17 Page 56 :1

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1-bit register 5-bit register # Multiplexers 1-bit 16-to-1 multiplexer : 16 :1 :2 :2

================================================================= ======== ================================================================= ======== * ======== Loading device for application Rf_Device from file '3s250e.nph' in environment D:\Xilinx. WARNING:Xst:2677 - Node <logical_0> of sequential type is unconnected in block <barrel_shft>. ================================================================= ======== Advanced HDL Synthesis Report Macro Statistics # Counters 3-bit up counter # Registers Flip-Flops # Multiplexers 1-bit 16-to-1 multiplexer :1 :1 : 20 : 20 :2 :2 Advanced HDL Synthesis * =================================================================

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================================================================= ======== ================================================================= ======== * ======== Optimizing unit <barrel_shft> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block barrel_shft, actual ratio is 9. FlipFlop i_0 has been replicated 1 time(s) FlipFlop i_1 has been replicated 1 time(s) FlipFlop i_10 has been replicated 1 time(s) FlipFlop i_11 has been replicated 1 time(s) FlipFlop i_12 has been replicated 1 time(s) FlipFlop i_13 has been replicated 1 time(s) FlipFlop i_14 has been replicated 1 time(s) FlipFlop i_15 has been replicated 1 time(s) FlipFlop i_2 has been replicated 1 time(s) FlipFlop i_3 has been replicated 1 time(s) FlipFlop i_4 has been replicated 1 time(s) FlipFlop i_5 has been replicated 1 time(s) FlipFlop i_6 has been replicated 1 time(s) FlipFlop i_7 has been replicated 1 time(s) FlipFlop i_8 has been replicated 1 time(s) FlipFlop i_9 has been replicated 2 time(s) FlipFlop logical_1 has been replicated 1 time(s) Low Level Synthesis * =================================================================

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FlipFlop logical_2 has been replicated 2 time(s) FlipFlop logical_3 has been replicated 2 time(s) FlipFlop logical_4 has been replicated 1 time(s) Final Macro Processing ... ================================================================= ======== Final Register Report Macro Statistics # Registers Flip-Flops : 46 : 46

================================================================= ======== ================================================================= ======== * ======== Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------Partition Report * =================================================================

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================================================================= ======== * ======== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # # # # # # # # # # GND LUT2 LUT2_L LUT3 LUT3_D LUT3_L LUT4 LUT4_D LUT4_L MUXF5 MUXF6 MUXF7 FDCP : 448 :1 : 20 : 10 : 43 :4 : 11 : 277 :5 : 57 : 14 :4 :2 : 46 : 33 Page 60 : 25 : NGC : Speed : NO : barrel_shft.ngr : barrel_shft Final Report * =================================================================

# FlipFlops/Latches

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# # # # FDE BUFGP IBUF OBUF : 13 :1 :1 : 24 :8 : 16

# Clock Buffers # IO Buffers

================================================================= ======== Device utilization summary: --------------------------Selected Device : 3s250etq144-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs: --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. --------------------------25 25 out of 108 23% 1 out of 24 4% 237 out of 2448 46 out of 4896 427 out of 4896 9% 0% 8%

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================================================================= ======== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal clk | Clock buffer(FF name) | Load | | BUFGP | 46 | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: --------------------------------------------------------------------------+------------------------+-------+ Control Signal rst N0(XST_GND:G) | Buffer(FF name) | IBUF | 33 | | NONE(i_5_1) | 33 | | Load | -----------------------------------+------------------------+-------+

-----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 6.600ns (Maximum Frequency: 151.515MHz)

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Minimum input arrival time before clock: 11.163ns Maximum output required time after clock: 5.125ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) ================================================================= ======== Timing constraint: Default period analysis for Clock 'clk' Clock period: 6.600ns (frequency: 151.515MHz) Total number of paths / destination ports: 1565 / 46 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 6.600ns (Levels of Logic = 5) i_6_1 (FF) i_15 (FF) clk rising

Destination Clock: clk rising Data Path: i_6_1 to i_15 Gate Cell:in->out FDCP:C->Q LUT4:I2->O LUT4:I2->O LUT2:I1->O LUT4_L:I3->LO LUT4:I2->O FDCP:D Net fanout Delay Delay Logical Name (Net Name) 5 0.591 0.668 i_6_1 (i_6_1) 1 0.704 0.455 i_15_mux0000160 (i_15_mux0000_map42) 1 0.704 0.499 i_15_mux0000186 (i_15_mux0000_map52) 1 0.704 0.424 i_15_mux0000195 (i_15_mux0000_map53) 1 0.704 0.135 i_15_mux0000223 (i_15_mux0000_map57) 2 0.704 0.000 i_15_mux0000248 (i_15_mux0000) 0.308 i_15 Page 63

---------------------------------------- ------------

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---------------------------------------Total 6.600ns (4.419ns logic, 2.181ns route) (67.0% logic, 33.0% route) ================================================================= ======== Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 4835 / 46 ------------------------------------------------------------------------Offset: Source: Destination: 11.163ns (Levels of Logic = 8) cond3<0> (PAD) i_13 (FF)

Destination Clock: clk rising Data Path: cond3<0> to i_13 Gate Cell:in->out IBUF:I->O LUT4:I0->O LUT3:I0->O LUT4:I0->O LUT4_L:I3->LO LUT4:I1->O LUT4_L:I2->LO LUT4:I3->O FDCP:D Total Net fanout Delay Delay Logical Name (Net Name) 33 1.218 1.438 cond3_0_IBUF (cond3_0_IBUF) 17 0.704 1.226 i_15_cmp_eq00181 (i_15_cmp_eq0018) 7 0.704 0.883 i_8_mux0000141 (N57) 1 0.704 0.424 i_13_mux000090 (i_13_mux0000_map24) 1 0.704 0.179 i_13_mux0000103 (i_13_mux0000_map30) 1 0.704 0.455 i_13_mux0000177 (i_13_mux0000_map49) 1 0.704 0.104 i_13_mux000077_SW0 (N2154) 2 0.704 0.000 i_13_mux0000286 (i_13_mux0000) 0.308 i_13

---------------------------------------- ------------

---------------------------------------11.163ns (6.454ns logic, 4.709ns route) (57.8% logic, 42.2% route)

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================================================================= ======== Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------Offset: Source: Destination: Source Clock: 5.125ns (Levels of Logic = 1) i_4 (FF) dout<4> (PAD) clk rising

Data Path: i_4 to dout<4> Gate Cell:in->out FDCP:C->Q OBUF:I->O Total Net fanout Delay Delay Logical Name (Net Name) 31 0.591 1.262 i_4 (i_4) 3.272 dout_4_OBUF (dout<4>)

---------------------------------------- ------------

---------------------------------------5.125ns (3.863ns logic, 1.262ns route) (75.4% logic, 24.6% route) ================================================================= ======== CPU : 13.23 / 13.48 s | Elapsed : 13.00 / 14.00 s --> Total memory usage is 174492 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 4 ( 0 filtered) Number of infos : 6 ( 0 filtered

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5.4.2 PLACE AND ROUTE REPORT:
Release 9.2i par J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. ARJUN-PC:: Sat Jul 25 18:32:45 2009 par -w -intstyle ise -ol std -t 1 barrel_shft_map.ncd barrel_shft.ncd barrel_shft.pcf

Constraints file: barrel_shft.pcf. Loading device for application Rf_Device from file '3s250e.nph' in environment D:\Xilinx. "barrel_shft" is an NCD, version 3.1, device xc3s250e, package tq144, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". Device speed data version: "PRODUCTION 1.26 2007-04-13".

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Design Summary Report: Number of External IOBs Number of External Input IOBs Number of External Input IBUFs Number of External Output IOBs Number of External Output IOBs Number of External Bidir IOBs 25 out of 108 23% 9 9 16 16 0

Number of BUFGMUXs Number of Slices Number of SLICEMs

1 out of 24 239 out of 2448 9%

4%

4 out of 1224 1%

Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard

Starting Placer Phase 1.1 Phase 1.1 (Checksum:989db0) REAL time: 3 secs

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Phase 2.7 Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs Phase 4.2 ...... ..... Phase 4.2 (Checksum:989e4f) REAL time: 3 secs Phase 5.30 Phase 5.30 (Checksum:2faf07b) REAL time: 3 secs Phase 6.3 Phase 6.3 (Checksum:39386fa) REAL time: 3 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs Phase 8.8 .......... ....... .......... .................... .... Phase 8.8 (Checksum:a7c507) REAL time: 6 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 6 secs

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Phase 10.18 Phase 10.18 (Checksum:5f5e0f6) REAL time: 7 secs Phase 11.5 Phase 11.5 (Checksum:68e7775) REAL time: 7 secs REAL time consumed by placer: 7 secs CPU time consumed by placer: 6 secs Writing design to file barrel_shft.ncd

Total REAL time to Placer completion: 8 secs Total CPU time to Placer completion: 7 secs Starting Router Phase 1: 1737 unrouted; Phase 2: 1693 unrouted; Phase 3: 532 unrouted; REAL time: 9 secs REAL time: 9 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs

Phase 4: 532 unrouted; (711) Phase 5: 543 unrouted; (0) Phase 6: 0 unrouted; (0) Phase 7: 0 unrouted; (0)

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Phase 8: 0 unrouted; (0) Phase 9: 0 unrouted; (0) REAL time: 10 secs REAL time: 10 secs

Total REAL time to Router completion: 10 secs Total CPU time to Router completion: 9 secs Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| clk_BUFGP | BUFGMUX_X1Y10| No | 43 | 0.012 | 0.098 | +---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays.

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The Delay Summary Report

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: The MAXIMUM PIN DELAY IS: 4.956 1.231

The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.531 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------819 630 200 68 31 0

Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. -----------------------------------------------------------------------------------------------------Constraint | | Check | Worst Case | Best Case | Timing | Timing | Slack | Achievable | Errors | Score | | N/A| 0| 8.100ns| 0 N/A|

-----------------------------------------------------------------------------------------------------Autotimespec constraint for clock net clk | SETUP 0 _BUFGP | HOLD | 1.392ns| ------------------------------------------------------------------------------------------------------

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All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.

Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 11 secs Total CPU time to PAR completion: 10 secs Peak Memory Usage: 150 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file barrel_shft.ncd

PAR done!

5.4.3 BITGEN REPORT:

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Release 9.2i - Bitgen J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Loading device for application Rf_Device from file '3s250e.nph' in environment D:\Xilinx. "barrel_shft" is an NCD, version 3.1, device xc3s250e, package tq144, speed -4 Opened constraints file barrel_shft.pcf. Sat Jul 25 18:33:06 2009 D:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No barrel_shft.ncd Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Compress | Readback | CRC | Current Setting | (Not Specified)* | (Not Specified)* | Enable** | No** | 1** | Page 73 | | | | | +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ | DebugBitstream | ConfigRate +----------------------+----------------------+

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+----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DonePin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | TmsPin | UnusedPin | GWE_cycle | GTS_cycle | LCK_cycle | DONE_cycle | Persist | DriveDone | DonePipe | Security | Pullup** | Pullup** | Pulldown** | 6** | 5** | NoWait** | 4** | No* | No** | No** | None** | | | | | | | | | | | +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+

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| UserID | MultiBootMode | ActivateGclk | ActiveReconfig | PartialMask0 | PartialMask1 | PartialMask2 | PartialGclk | PartialLeft | PartialRight | IEEE1532 | Binary | 0xFFFFFFFF** | No* | No* | No* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | No* | No** | | | | | | | | | | | |

+----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "barrel_shft.bit".

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Bitstream generation is complete.

CHAPTER 6
6.1 CONCLUSION:

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Hence we have designed the IP Core for Barrel Shifter using VHDL. The simulation has been done using ISE Simulator. The synthesis has been done using XILINX ISE 9.1i. The bit file has been generated and the output is dumped on the FPGA Device (Spartan3E).

6.2 Applications of barrel shifter

Digital Signal Processing Array Processing Graphics Database Addressing High Speed Arithmetic Processors

6.3 FUTURE SCOPE:

The design has been done for the 16-bit Barrel Shifter. The core can be used to design for further designs of 32-bit , 64-bit and so on to be utilized in DSP Processors and any communication systems like USB transmitters etc.

REFERENCES
1. www.wikipedia.com 2. www.google.com 3. www.xilinx.com 4. www.digilent.com (for reference manual)

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5. Digital Design Principles and Practices by John F. Wakerly, Fourth Edition 6. Advanced VHDL Design by J. Basker

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